Sylvain Munaut 641ac1e3ef gateware: Switch to using Vex CPU ... It's a good ~ 3.5x faster than the PicoRV32 (in number of cycles), which allows to shutdown the system clock more and reduce power a bit as well. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>		2023-03-23 11:18:14 +01:00
..
VexRiscv.v	gateware: Switch to using Vex CPU	2023-03-23 11:18:14 +01:00
led_ctrl.v	gateware: Initial import of the FPGA gateware	2023-03-11 23:54:12 +01:00
picorv32.v	gateware: Initial import of the FPGA gateware	2023-03-11 23:54:12 +01:00
picorv32_ice40_regs.v	gateware: Initial import of the FPGA gateware	2023-03-11 23:54:12 +01:00
pmu.v	gateware/firmware: Add better support for buttons	2023-03-16 09:59:06 +01:00
soc_bram.v	gateware: Initial import of the FPGA gateware	2023-03-11 23:54:12 +01:00
soc_picorv32_base.v	gateware: Initial import of the FPGA gateware	2023-03-11 23:54:12 +01:00
soc_picorv32_bridge.v	gateware: Initial import of the FPGA gateware	2023-03-11 23:54:12 +01:00
soc_spram.v	gateware: Initial import of the FPGA gateware	2023-03-11 23:54:12 +01:00
soc_usb_buf_bridge.v	gateware: Initial import of the FPGA gateware	2023-03-11 23:54:12 +01:00
soc_vex_base.v	gateware: Switch to using Vex CPU	2023-03-23 11:18:14 +01:00
soc_vex_bridge.v	gateware: Switch to using Vex CPU	2023-03-23 11:18:14 +01:00
sysmgr_1.v	gateware: Switch clk_sys to 12 MHz	2023-03-22 21:54:35 +01:00
sysmgr_2.v	gateware: Switch clk_sys to 12 MHz	2023-03-22 21:54:35 +01:00
sysmgr_3.v	gateware: Switch clk_sys to 12 MHz	2023-03-22 21:54:35 +01:00
top.v	gateware: Switch to using Vex CPU	2023-03-23 11:18:14 +01:00
xclk_cnt.v	gateware: Initial import of the FPGA gateware	2023-03-11 23:54:12 +01:00
xclk_pulse.v	gateware: Initial import of the FPGA gateware	2023-03-11 23:54:12 +01:00