333 lines
5.9 KiB
Verilog
333 lines
5.9 KiB
Verilog
/*
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* top.v
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*
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* vim: ts=4 sw=4
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*
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* Copyright (C) 2019-2020 Sylvain Munaut <tnt@246tNt.com>
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* SPDX-License-Identifier: CERN-OHL-P-2.0
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*/
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`default_nettype none
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module top (
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// SPI
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inout wire [3:0] spi_io,
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output wire spi_clk,
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output wire spi_cs_n,
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// USB
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inout wire usb_dp,
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inout wire usb_dn,
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output wire usb_pu,
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// Power
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input wire pwr_usb_n,
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input wire pwr_chg_n,
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output wire pwr_off,
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// Buttons
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input wire [1:0] btn,
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// I2C
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inout wire scl,
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inout wire sda,
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// Speaker
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output wire hp_p,
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output wire hp_n,
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// LED matrix
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output wire [13:0] led_a,
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output wire [2:0] led_c
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);
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localparam integer WN = 6;
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genvar i;
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// Signals
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// -------
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// Wishbone
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wire [15:0] wb_addr;
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wire [31:0] wb_rdata [0:WN-1];
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wire [31:0] wb_wdata;
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wire [3:0] wb_wmsk;
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wire [WN-1:0] wb_cyc;
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wire wb_we;
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wire [WN-1:0] wb_ack;
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wire [(32*WN)-1:0] wb_rdata_flat;
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// I2C
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wire i2c_scl_oe;
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wire i2c_scl_i;
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wire i2c_sda_oe;
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wire i2c_sda_i;
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// USB Core
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// Wishbone in 48 MHz domain
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wire [11:0] ub_addr;
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wire [15:0] ub_wdata;
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wire [15:0] ub_rdata;
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wire ub_cyc;
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wire ub_we;
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wire ub_ack;
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// EP Buffer
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wire [ 8:0] ep_tx_addr_0;
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wire [31:0] ep_tx_data_0;
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wire ep_tx_we_0;
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wire [ 8:0] ep_rx_addr_0;
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wire [31:0] ep_rx_data_1;
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wire ep_rx_re_0;
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// Clock Control
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wire wakeup;
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wire sys_start;
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wire sys_stop;
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wire usb_ena;
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// Clock / Reset
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wire clk_led;
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wire rst_led;
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wire clk_sys;
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wire rst_sys;
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wire clk_usb;
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wire rst_usb;
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// SoC
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// ---
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soc_vex_base #(
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.WB_N (WN),
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.WB_DW (32),
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.WB_AW (16),
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.BRAM_AW (8), // 1k BRAM
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.SPRAM_AW (14) // 64k SPRAM
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) base_I (
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.wb_addr (wb_addr),
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.wb_rdata (wb_rdata_flat),
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.wb_wdata (wb_wdata),
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.wb_wmsk (wb_wmsk),
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.wb_we (wb_we),
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.wb_cyc (wb_cyc),
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.wb_ack (wb_ack),
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.clk (clk_sys),
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.rst (rst_sys)
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);
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for (i=0; i<WN; i=i+1)
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assign wb_rdata_flat[i*32+:32] = wb_rdata[i];
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// PMU [0]
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// ---
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pmu pmu_I (
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.wb_addr (wb_addr[15:0]),
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.wb_rdata (wb_rdata[0]),
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.wb_wdata (wb_wdata),
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.wb_we (wb_we),
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.wb_cyc (wb_cyc[0]),
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.wb_ack (wb_ack[0]),
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.btn (btn),
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.pwr_usb_n (pwr_usb_n),
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.pwr_chg_n (pwr_chg_n),
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.pwr_off (pwr_off),
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.sys_start (sys_start),
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.sys_stop (sys_stop),
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.usb_ena (usb_ena),
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.wakeup (wakeup),
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.clk (clk_sys),
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.rst (rst_sys)
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);
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// SPI [1]
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// ---
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ice40_spi_wb #(
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.N_CS(1),
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.WITH_IOB(1),
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.UNIT(0)
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) spi_I (
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.pad_mosi (spi_io[0]),
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.pad_miso (spi_io[1]),
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.pad_clk (spi_clk),
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.pad_csn (spi_cs_n),
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.wb_addr (wb_addr[3:0]),
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.wb_rdata (wb_rdata[1]),
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.wb_wdata (wb_wdata),
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.wb_we (wb_we),
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.wb_cyc (wb_cyc[1]),
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.wb_ack (wb_ack[1]),
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.clk (clk_sys),
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.rst (rst_sys)
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);
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assign spi_io[3:2] = 4'bzz;
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// I2C [2]
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// ---
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// Controller
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i2c_master_wb #(
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.DW(4),
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.TW(15),
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.CLOCK_STRETCH(1),
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.FIFO_DEPTH(0)
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) i2c_I (
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.scl_oe (i2c_scl_oe),
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.scl_i (i2c_scl_i),
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.sda_oe (i2c_sda_oe),
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.sda_i (i2c_sda_i),
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.wb_rdata(wb_rdata[2]),
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.wb_wdata(wb_wdata),
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.wb_we (wb_we),
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.wb_cyc (wb_cyc[2]),
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.wb_ack (wb_ack[2]),
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.clk (clk_sys),
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.rst (rst_sys)
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);
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// IOBs
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SB_IO #(
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.PIN_TYPE(6'b110100),
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.PULLUP(1'b1),
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.IO_STANDARD("SB_LVCMOS")
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) i2c_iob_I[1:0] (
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.PACKAGE_PIN ({scl, sda}),
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.INPUT_CLK (clk_sys),
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.OUTPUT_CLK (clk_sys),
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.OUTPUT_ENABLE({i2c_scl_oe, i2c_sda_oe}),
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.D_OUT_0 (1'b0),
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.D_IN_0 ({i2c_scl_i, i2c_sda_i})
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);
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// USB Buffer [3]
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// ----------
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soc_usb_buf_bridge usb_buf_I (
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.wb_addr (wb_addr),
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.wb_rdata (wb_rdata[3]),
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.wb_wdata (wb_wdata),
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.wb_wmsk (wb_wmsk),
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.wb_we (wb_we),
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.wb_cyc (wb_cyc[3]),
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.wb_ack (wb_ack[3]),
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.ep_tx_addr_0 (ep_tx_addr_0),
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.ep_tx_data_0 (ep_tx_data_0),
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.ep_tx_we_0 (ep_tx_we_0),
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.ep_rx_addr_0 (ep_rx_addr_0),
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.ep_rx_data_1 (ep_rx_data_1),
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.ep_rx_re_0 (ep_rx_re_0),
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.clk (clk_sys),
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.rst (rst_sys)
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);
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// USB core [4]
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// --------
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// Cross-clock
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xclk_wb #(
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.DW(16),
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.AW(12)
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) wb_48m_xclk_I (
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.s_addr (wb_addr[11:0]),
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.s_wdata (wb_wdata[15:0]),
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.s_rdata (wb_rdata[4][15:0]),
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.s_cyc (wb_cyc[4]),
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.s_ack (wb_ack[4]),
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.s_we (wb_we),
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.s_clk (clk_sys),
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.m_addr (ub_addr),
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.m_wdata (ub_wdata),
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.m_rdata (ub_rdata),
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.m_cyc (ub_cyc),
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.m_ack (ub_ack),
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.m_we (ub_we),
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.m_clk (clk_usb),
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.rst (rst_usb)
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);
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assign wb_rdata[4][31:16] = 0;
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// Core
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usb #(
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.EPDW(32)
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) usb_I (
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.pad_dp (usb_dp),
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.pad_dn (usb_dn),
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.pad_pu (usb_pu),
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.ep_tx_addr_0 (ep_tx_addr_0),
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.ep_tx_data_0 (ep_tx_data_0),
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.ep_tx_we_0 (ep_tx_we_0),
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.ep_rx_addr_0 (ep_rx_addr_0),
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.ep_rx_data_1 (ep_rx_data_1),
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.ep_rx_re_0 (ep_rx_re_0),
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.ep_clk (clk_sys),
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.wb_addr (ub_addr),
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.wb_rdata (ub_rdata),
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.wb_wdata (ub_wdata),
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.wb_we (ub_we),
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.wb_cyc (ub_cyc),
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.wb_ack (ub_ack),
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.clk (clk_usb),
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.rst (rst_usb)
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);
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// LED matrix controller [5]
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// ---------------------
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led_ctrl led_I (
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.led_a (led_a),
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.led_c (led_c),
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.led_clk (clk_led),
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.led_rst (rst_led),
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.trig_out (wakeup),
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.wb_addr (wb_addr[15:0]),
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.wb_rdata (wb_rdata[5]),
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.wb_wdata (wb_wdata),
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.wb_we (wb_we),
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.wb_cyc (wb_cyc[5]),
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.wb_ack (wb_ack[5]),
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.wb_clk (clk_sys),
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.wb_rst (rst_sys)
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);
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// CRG
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// ---
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`ifdef SIM
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sysmgr_sim crg_I (
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`else
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sysmgr crg_I (
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`endif
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.sys_start (sys_start),
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.sys_stop (sys_stop),
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.usb_ena (usb_ena),
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.clk_led (clk_led),
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.rst_led (rst_led),
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.clk_sys (clk_sys),
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.rst_sys (rst_sys),
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.clk_usb (clk_usb),
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.rst_usb (rst_usb)
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);
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// Unused
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// ------
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assign hp_p = 1'bz;
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assign hp_n = 1'bz;
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endmodule // top
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