35 lines
640 B
Verilog
35 lines
640 B
Verilog
/*
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* xclk_cnt.v
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*
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* vim: ts=4 sw=4
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*
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* Helper to pass a counter value from one domain to another
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* (assuming the counter is increment/decrement/wrap only !)
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*
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* Copyright (C) 2023 Sylvain Munaut <tnt@246tNt.com>
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* SPDX-License-Identifier: CERN-OHL-P-2.0
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*/
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`default_nettype none
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module xclk_cnt #(
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parameter integer WIDTH = 4
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)(
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input wire [WIDTH-1:0] i_val,
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input wire i_clk,
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output wire [WIDTH-1:0] o_val,
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input wire o_clk,
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input wire rst
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);
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// Encode to gray in source domain
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// Capture in destination domain
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// Decode from gray in destination domain
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// FIXME
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assign o_val = i_val;
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endmodule // xclk_cnt
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