187 lines
4.2 KiB
Verilog
187 lines
4.2 KiB
Verilog
/*
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* soc_picorv32_bridge.v
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*
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* vim: ts=4 sw=4
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*
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* Copyright (C) 2020 Sylvain Munaut <tnt@246tNt.com>
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* SPDX-License-Identifier: CERN-OHL-P-2.0
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*/
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`default_nettype none
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module soc_picorv32_bridge #(
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parameter integer WB_N = 8,
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parameter integer WB_DW = 32,
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parameter integer WB_AW = 16,
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parameter integer WB_AI = 2,
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parameter integer WB_REG = 0 // [0] = cyc / [1] = addr/wdata/wstrb / [2] = ack/rdata
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)(
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/* PicoRV32 bus */
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input wire [31:0] pb_addr,
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output wire [31:0] pb_rdata,
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input wire [31:0] pb_wdata,
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input wire [ 3:0] pb_wstrb,
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input wire pb_valid,
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output wire pb_ready,
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/* BRAM */
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output wire [14:0] bram_addr,
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input wire [31:0] bram_rdata,
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output wire [31:0] bram_wdata,
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output wire [ 3:0] bram_wmsk,
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output wire bram_we,
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/* SPRAM */
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output wire [14:0] spram_addr,
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input wire [31:0] spram_rdata,
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output wire [31:0] spram_wdata,
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output wire [ 3:0] spram_wmsk,
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output wire spram_we,
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/* Wishbone buses */
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output wire [WB_AW-1:0] wb_addr,
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input wire [(WB_DW*WB_N)-1:0] wb_rdata,
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output wire [WB_DW-1:0] wb_wdata,
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output wire [(WB_DW/8)-1:0] wb_wmsk,
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output wire wb_we,
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output wire [WB_N-1:0] wb_cyc,
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input wire [WB_N-1:0] wb_ack,
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/* Clock / Reset */
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input wire clk,
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input wire rst
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);
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// Signals
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// -------
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wire ram_sel;
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reg ram_rdy;
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wire [31:0] ram_rdata;
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(* keep *) wire [WB_N-1:0] wb_match;
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(* keep *) wire wb_cyc_rst;
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reg [31:0] wb_rdata_or;
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wire [31:0] wb_rdata_out;
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wire wb_rdy;
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// RAM access
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// ----------
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// BRAM : 0x00000000 -> 0x0001ffff
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// SPRAM : 0x00020000 -> 0x0003ffff
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assign bram_addr = pb_addr[16:2];
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assign spram_addr = pb_addr[16:2];
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assign bram_wdata = pb_wdata;
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assign spram_wdata = pb_wdata;
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assign bram_wmsk = ~pb_wstrb;
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assign spram_wmsk = ~pb_wstrb;
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assign bram_we = pb_valid & ~pb_addr[31] & |pb_wstrb & ~pb_addr[17];
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assign spram_we = pb_valid & ~pb_addr[31] & |pb_wstrb & pb_addr[17];
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assign ram_rdata = ~pb_addr[31] ? (pb_addr[17] ? spram_rdata : bram_rdata) : 32'h00000000;
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assign ram_sel = pb_valid & ~pb_addr[31];
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always @(posedge clk)
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ram_rdy <= ram_sel && ~ram_rdy;
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// Wishbone
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// --------
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// wb[x] = 0x8x000000 - 0x8xffffff
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// Access Cycle
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genvar i;
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for (i=0; i<WB_N; i=i+1)
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assign wb_match[i] = (pb_addr[27:24] == i);
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if (WB_REG & 1) begin
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// Register
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reg [WB_N-1:0] wb_cyc_reg;
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always @(posedge clk)
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if (wb_cyc_rst)
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wb_cyc_reg <= 0;
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else
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wb_cyc_reg <= wb_match & ~wb_ack;
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assign wb_cyc = wb_cyc_reg;
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end else begin
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// Direct connection
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assign wb_cyc = wb_cyc_rst ? { WB_N{1'b0} } : wb_match;
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end
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// Addr / Write-Data / Write-Mask / Write-Enable
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if (WB_REG & 2) begin
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// Register
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reg [WB_AW-1:0] wb_addr_reg;
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reg [WB_DW-1:0] wb_wdata_reg;
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reg [(WB_DW/8)-1:0] wb_wmsk_reg;
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reg wb_we_reg;
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always @(posedge clk)
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begin
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wb_addr_reg <= pb_addr[WB_AW+WB_AI-1:WB_AI];
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wb_wdata_reg <= pb_wdata[WB_DW-1:0];
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wb_wmsk_reg <= ~pb_wstrb[(WB_DW/8)-1:0];
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wb_we_reg <= |pb_wstrb;
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end
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assign wb_addr = wb_addr_reg;
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assign wb_wdata = wb_wdata_reg;
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assign wb_wmsk = wb_wmsk_reg;
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assign wb_we = wb_we_reg;
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end else begin
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// Direct connection
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assign wb_addr = pb_addr[WB_AW+WB_AI-1:WB_AI];
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assign wb_wdata = pb_wdata[WB_DW-1:0];
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assign wb_wmsk = pb_wstrb[(WB_DW/8)-1:0];
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assign wb_we = |pb_wstrb;
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end
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// Ack / Read-Data
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always @(*)
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begin : wb_or
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integer i;
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wb_rdata_or = 0;
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for (i=0; i<WB_N; i=i+1)
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wb_rdata_or[WB_DW-1:0] = wb_rdata_or[WB_DW-1:0] | wb_rdata[WB_DW*i+:WB_DW];
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end
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if (WB_REG & 4) begin
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// Register
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reg wb_rdy_reg;
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reg [31:0] wb_rdata_reg;
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always @(posedge clk)
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wb_rdy_reg <= |wb_ack;
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always @(posedge clk)
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if (wb_cyc_rst)
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wb_rdata_reg <= 32'h00000000;
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else
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wb_rdata_reg <= wb_rdata_or;
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assign wb_cyc_rst = ~pb_valid | ~pb_addr[31] | wb_rdy_reg;
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assign wb_rdy = wb_rdy_reg;
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assign wb_rdata_out = wb_rdata_reg;
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end else begin
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// Direct connection
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assign wb_cyc_rst = ~pb_valid | ~pb_addr[31];
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assign wb_rdy = |wb_ack;
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assign wb_rdata_out = wb_rdata_or;
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end
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// Final data combining
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// --------------------
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assign pb_rdata = ram_rdata | wb_rdata_out;
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assign pb_ready = ram_rdy | wb_rdy;
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endmodule // soc_picorv32_bridge
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