44 lines
924 B
Verilog
44 lines
924 B
Verilog
/*
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* picorv32_ice40_regs.v
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*
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* vim: ts=4 sw=4
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*
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* Implementation of register file for the PicoRV32 on iCE40
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*
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* Copyright (C) 2020 Sylvain Munaut <tnt@246tNt.com>
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* SPDX-License-Identifier: CERN-OHL-P-2.0
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*/
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`default_nettype none
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module picorv32_ice40_regs (
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input wire clk,
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input wire wen,
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input wire [5:0] waddr,
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input wire [5:0] raddr1,
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input wire [5:0] raddr2,
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input wire [31:0] wdata,
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output wire [31:0] rdata1,
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output wire [31:0] rdata2
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);
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ice40_ebr #(
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.READ_MODE(0),
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.WRITE_MODE(0),
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.MASK_WORKAROUND(0),
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.NEG_WR_CLK(0),
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.NEG_RD_CLK(1)
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) regs[3:0] (
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.wr_addr ({ 4{2'b00, waddr} }),
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.wr_data ({ 2{wdata} }),
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.wr_mask (64'h0000000000000000),
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.wr_ena (wen),
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.wr_clk (clk),
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.rd_addr ({2'b00, raddr2, 2'b00, raddr2, 2'b00, raddr1, 2'b00, raddr1}),
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.rd_data ({rdata2, rdata1}),
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.rd_ena (1'b1),
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.rd_clk (clk)
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);
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endmodule // picorv32_ice40_regs
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