175 lines
3.7 KiB
Verilog
175 lines
3.7 KiB
Verilog
/*
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* soc_vex_base.v
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*
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* vim: ts=4 sw=4
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*
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* Copyright (C) 2019-2023 Sylvain Munaut <tnt@246tNt.com>
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* SPDX-License-Identifier: CERN-OHL-P-2.0
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*/
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`default_nettype none
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module soc_vex_base #(
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parameter integer WB_N = 6,
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parameter integer WB_DW = 32,
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parameter integer WB_AW = 16,
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parameter integer BRAM_AW = 8, /* Default 1k */
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parameter integer SPRAM_AW = 14, /* 14 => 64k, 15 => 128k */
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/* auto */
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parameter integer WB_MW = WB_DW / 8,
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parameter integer WB_RW = WB_DW * WB_N,
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parameter integer WB_AI = $clog2(WB_MW)
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)(
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// Wishbone
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output wire [WB_AW-1:0] wb_addr,
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input wire [WB_RW-1:0] wb_rdata,
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output wire [WB_DW-1:0] wb_wdata,
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output wire [WB_MW-1:0] wb_wmsk,
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output wire wb_we,
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output wire [WB_N -1:0] wb_cyc,
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input wire [WB_N -1:0] wb_ack,
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// Clock / Reset
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input wire clk,
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input wire rst
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);
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// Signals
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// -------
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// Vex ISimpleBus
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wire ic_valid;
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wire ic_ready;
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wire [31:0] ic_pc;
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wire ir_valid;
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wire ir_error;
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wire [31:0] ir_inst;
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// Vex DSimpleBus
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wire dc_valid;
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wire dc_ready;
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wire dc_wr;
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wire [31:0] dc_address;
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wire [31:0] dc_data;
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wire [ 1:0] dc_size;
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wire dr_ready;
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wire dr_error;
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wire [31:0] dr_data;
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// RAM
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// BRAM
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wire [14:0] bram_addr;
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wire [31:0] bram_rdata;
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wire [31:0] bram_wdata;
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wire [ 3:0] bram_wmsk;
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wire bram_we;
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// SPRAM
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wire [14:0] spram_addr;
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wire [31:0] spram_rdata;
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wire [31:0] spram_wdata;
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wire [ 3:0] spram_wmsk;
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wire spram_we;
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// CPU
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// ---
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VexRiscv cpu_I (
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.iBus_cmd_valid (ic_valid),
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.iBus_cmd_ready (ic_ready),
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.iBus_cmd_payload_pc (ic_pc),
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.iBus_rsp_valid (ir_valid),
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.iBus_rsp_payload_error (ir_error),
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.iBus_rsp_payload_inst (ir_inst),
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.dBus_cmd_valid (dc_valid),
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.dBus_cmd_ready (dc_ready),
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.dBus_cmd_payload_wr (dc_wr),
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.dBus_cmd_payload_address (dc_address),
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.dBus_cmd_payload_data (dc_data),
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.dBus_cmd_payload_size (dc_size),
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.dBus_rsp_ready (dr_ready),
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.dBus_rsp_error (dr_error),
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.dBus_rsp_data (dr_data),
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.clk (clk),
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.reset (rst)
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);
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// Bus interface
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// -------------
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soc_vex_bridge #(
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.WB_N (WB_N),
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.WB_DW(WB_DW),
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.WB_AW(WB_AW),
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.WB_AI(WB_AI)
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) vb_I (
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.ic_valid (ic_valid),
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.ic_ready (ic_ready),
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.ic_pc (ic_pc),
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.ir_valid (ir_valid),
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.ir_error (ir_error),
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.ir_inst (ir_inst),
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.dc_valid (dc_valid),
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.dc_ready (dc_ready),
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.dc_wr (dc_wr),
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.dc_address (dc_address),
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.dc_data (dc_data),
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.dc_size (dc_size),
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.dr_ready (dr_ready),
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.dr_error (dr_error),
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.dr_data (dr_data),
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.bram_addr (bram_addr),
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.bram_rdata (bram_rdata),
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.bram_wdata (bram_wdata),
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.bram_wmsk (bram_wmsk),
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.bram_we (bram_we),
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.spram_addr (spram_addr),
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.spram_rdata (spram_rdata),
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.spram_wdata (spram_wdata),
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.spram_wmsk (spram_wmsk),
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.spram_we (spram_we),
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.wb_addr (wb_addr),
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.wb_wdata (wb_wdata),
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.wb_wmsk (wb_wmsk),
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.wb_rdata (wb_rdata),
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.wb_cyc (wb_cyc),
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.wb_we (wb_we),
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.wb_ack (wb_ack),
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.clk (clk),
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.rst (rst)
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);
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// Local memory
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// ------------
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// Boot memory
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soc_bram #(
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.SIZE(1 << BRAM_AW),
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.INIT_FILE("boot.hex")
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) bram_I (
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.addr (bram_addr[BRAM_AW-1:0]),
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.rdata (bram_rdata),
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.wdata (bram_wdata),
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.wmsk (bram_wmsk),
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.we (bram_we),
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.clk (clk)
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);
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// Main memory
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soc_spram #(
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.AW(SPRAM_AW)
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) spram_I (
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.addr (spram_addr[SPRAM_AW-1:0]),
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.rdata (spram_rdata),
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.wdata (spram_wdata),
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.wmsk (spram_wmsk),
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.we (spram_we),
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.clk (clk)
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);
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endmodule // soc_vex_base
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