tnt
/
xmas-snoopy
1
0
Fork 0
Code Pull Requests Releases Wiki Activity

gateware: Switch to using Vex CPU 

It's a good ~ 3.5x faster than the PicoRV32 (in number of cycles),
which allows to shutdown the system clock more and reduce power
a bit as well.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
This commit is contained in:
Sylvain Munaut 2023-03-23 07:55:02 +01:00
parent 5a98883e03
commit 641ac1e3ef
5 changed files with 3537 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
gateware/Makefile
View File

@ -12,7 +12,10 @@ PROJ_RTL_SRCS := $(addprefix rtl/, \
soc_picorv32_bridge.v \
soc_spram.v \
soc_usb_buf_bridge.v \
soc_vex_bridge.v \
soc_vex_base.v \
sysmgr_3.v \
VexRiscv.v \
xclk_cnt.v \
xclk_pulse.v \
)

3156
gateware/rtl/VexRiscv.v Normal file
View File

File diff suppressed because it is too large Load Diff

174
gateware/rtl/soc_vex_base.v Normal file
View File

@ -0,0 +1,174 @@
/*
* soc_vex_base.v
*
* vim: ts=4 sw=4
*
* Copyright (C) 2019-2023 Sylvain Munaut <tnt@246tNt.com>
* SPDX-License-Identifier: CERN-OHL-P-2.0
*/
`default_nettype none
module soc_vex_base #(
parameter integer WB_N = 6,
parameter integer WB_DW = 32,
parameter integer WB_AW = 16,
parameter integer BRAM_AW = 8, /* Default 1k */
parameter integer SPRAM_AW = 14, /* 14 => 64k, 15 => 128k */
/* auto */
parameter integer WB_MW = WB_DW / 8,
parameter integer WB_RW = WB_DW * WB_N,
parameter integer WB_AI = $clog2(WB_MW)
)(
// Wishbone
output wire [WB_AW-1:0] wb_addr,
input wire [WB_RW-1:0] wb_rdata,
output wire [WB_DW-1:0] wb_wdata,
output wire [WB_MW-1:0] wb_wmsk,
output wire wb_we,
output wire [WB_N -1:0] wb_cyc,
input wire [WB_N -1:0] wb_ack,
// Clock / Reset
input wire clk,
input wire rst
);
// Signals
// -------
// Vex ISimpleBus
wire ic_valid;
wire ic_ready;
wire [31:0] ic_pc;
wire ir_valid;
wire ir_error;
wire [31:0] ir_inst;
// Vex DSimpleBus
wire dc_valid;
wire dc_ready;
wire dc_wr;
wire [31:0] dc_address;
wire [31:0] dc_data;
wire [ 1:0] dc_size;
wire dr_ready;
wire dr_error;
wire [31:0] dr_data;
// RAM
// BRAM
wire [14:0] bram_addr;
wire [31:0] bram_rdata;
wire [31:0] bram_wdata;
wire [ 3:0] bram_wmsk;
wire bram_we;
// SPRAM
wire [14:0] spram_addr;
wire [31:0] spram_rdata;
wire [31:0] spram_wdata;
wire [ 3:0] spram_wmsk;
wire spram_we;
// CPU
// ---
VexRiscv cpu_I (
.iBus_cmd_valid (ic_valid),
.iBus_cmd_ready (ic_ready),
.iBus_cmd_payload_pc (ic_pc),
.iBus_rsp_valid (ir_valid),
.iBus_rsp_payload_error (ir_error),
.iBus_rsp_payload_inst (ir_inst),
.dBus_cmd_valid (dc_valid),
.dBus_cmd_ready (dc_ready),
.dBus_cmd_payload_wr (dc_wr),
.dBus_cmd_payload_address (dc_address),
.dBus_cmd_payload_data (dc_data),
.dBus_cmd_payload_size (dc_size),
.dBus_rsp_ready (dr_ready),
.dBus_rsp_error (dr_error),
.dBus_rsp_data (dr_data),
.clk (clk),
.reset (rst)
);
// Bus interface
// -------------
soc_vex_bridge #(
.WB_N (WB_N),
.WB_DW(WB_DW),
.WB_AW(WB_AW),
.WB_AI(WB_AI)
) vb_I (
.ic_valid (ic_valid),
.ic_ready (ic_ready),
.ic_pc (ic_pc),
.ir_valid (ir_valid),
.ir_error (ir_error),
.ir_inst (ir_inst),
.dc_valid (dc_valid),
.dc_ready (dc_ready),
.dc_wr (dc_wr),
.dc_address (dc_address),
.dc_data (dc_data),
.dc_size (dc_size),
.dr_ready (dr_ready),
.dr_error (dr_error),
.dr_data (dr_data),
.bram_addr (bram_addr),
.bram_rdata (bram_rdata),
.bram_wdata (bram_wdata),
.bram_wmsk (bram_wmsk),
.bram_we (bram_we),
.spram_addr (spram_addr),
.spram_rdata (spram_rdata),
.spram_wdata (spram_wdata),
.spram_wmsk (spram_wmsk),
.spram_we (spram_we),
.wb_addr (wb_addr),
.wb_wdata (wb_wdata),
.wb_wmsk (wb_wmsk),
.wb_rdata (wb_rdata),
.wb_cyc (wb_cyc),
.wb_we (wb_we),
.wb_ack (wb_ack),
.clk (clk),
.rst (rst)
);
// Local memory
// ------------
// Boot memory
soc_bram #(
.SIZE(1 << BRAM_AW),
.INIT_FILE("boot.hex")
) bram_I (
.addr (bram_addr[BRAM_AW-1:0]),
.rdata (bram_rdata),
.wdata (bram_wdata),
.wmsk (bram_wmsk),
.we (bram_we),
.clk (clk)
);
// Main memory
soc_spram #(
.AW(SPRAM_AW)
) spram_I (
.addr (spram_addr[SPRAM_AW-1:0]),
.rdata (spram_rdata),
.wdata (spram_wdata),
.wmsk (spram_wmsk),
.we (spram_we),
.clk (clk)
);
endmodule // soc_vex_base

203
gateware/rtl/soc_vex_bridge.v Normal file
View File

@ -0,0 +1,203 @@
/*
* soc_vex_bridge.v
*
* vim: ts=4 sw=4
*
* Copyright (C) 2020-2023 Sylvain Munaut <tnt@246tNt.com>
* SPDX-License-Identifier: CERN-OHL-P-2.0
*/
`default_nettype none
module soc_vex_bridge #(
parameter integer WB_N = 8,
parameter integer WB_DW = 32,
parameter integer WB_AW = 16,
parameter integer WB_AI = 2
)(
/* Vex ISimpleBus */
input wire ic_valid,
output wire ic_ready,
input wire [31:0] ic_pc,
output reg ir_valid,
output wire ir_error,
output wire [31:0] ir_inst,
/* Vex DSimpleBus */
input wire dc_valid,
output wire dc_ready,
input wire dc_wr,
input wire [31:0] dc_address,
input wire [31:0] dc_data,
input wire [ 1:0] dc_size,
output wire dr_ready,
output wire dr_error,
output wire [31:0] dr_data,
/* BRAM */
output wire [14:0] bram_addr,
input wire [31:0] bram_rdata,
output wire [31:0] bram_wdata,
output wire [ 3:0] bram_wmsk,
output wire bram_we,
/* SPRAM */
output wire [14:0] spram_addr,
input wire [31:0] spram_rdata,
output wire [31:0] spram_wdata,
output wire [ 3:0] spram_wmsk,
output wire spram_we,
/* Wishbone buses */
output reg [WB_AW-1:0] wb_addr,
input wire [(WB_DW*WB_N)-1:0] wb_rdata,
output reg [WB_DW-1:0] wb_wdata,
output reg [(WB_DW/8)-1:0] wb_wmsk,
output reg wb_we,
output reg [WB_N-1:0] wb_cyc,
input wire [WB_N-1:0] wb_ack,
/* Clock / Reset */
input wire clk,
input wire rst
);
genvar i;
// Signals
// -------
wire [31:0] ram_addr;
wire [31:0] ram_rdata;
wire [31:0] ram_wdata;
wire [ 3:0] ram_wmsk;
wire ram_we;
wire ram_user; // 0=IBus 1=DBus
reg ram_sel_r;
wire wb_start;
reg wb_busy;
wire [WB_N-1:0] wb_match;
reg wb_ack_r;
reg [ 31:0] wb_rdata_or;
reg [ 31:0] wb_rdata_r;
reg dr_ready_ram;
// RAM access
// ----------
// BRAM : 0x00000000 -> 0x000003ff
// SPRAM : 0x00020000 -> 0x0003ffff
// Commands
assign ram_user = dc_valid & ~dc_address[31];
assign ram_addr = ram_user ? dc_address : ic_pc;
assign ram_wdata = dc_data;
assign ram_wmsk = ~(((1 << (1 << dc_size)) - 1) << dc_address[1:0]);
assign ram_we = ram_user & dc_wr;
// Keep some info about the access
always @(posedge clk)
ram_sel_r <= ram_addr[17];
// BRAM
assign bram_addr = ram_addr[16:2];
assign bram_wdata = ram_wdata;
assign bram_wmsk = ram_wmsk;
assign bram_we = ram_we & ~ram_addr[17];
// SPRAM
assign spram_addr = ram_addr[16:2];
assign spram_wdata = ram_wdata;
assign spram_wmsk = ram_wmsk;
assign spram_we = ram_we & ram_addr[17];
// Read Mux
assign ram_rdata = ram_sel_r ? spram_rdata : bram_rdata;
// Wishbone
// --------
// wb[x] = 0x8x000000 - 0x8xffffff
// Busy
assign wb_start = dc_valid & dc_address[31] & ~wb_busy;
always @(posedge clk)
if (rst)
wb_busy <= 1'b0;
else
wb_busy <= (wb_busy & ~wb_ack_r) | wb_start;
// Register to keep value stable during bus access
// Wishbone need values to be stable
// But the Vex Bus won't do that unless we delay the 'dc_ready'
// and we can't ack the command and provide response in same cycle
// So easier to save those in the same cycle we do the decode
// and ack directly
always @(posedge clk)
begin
if (wb_start) begin
wb_addr <= dc_address[WB_AW+1:2];
wb_wdata <= dc_data;
wb_wmsk <= ~(((1 << (1 << dc_size)) - 1) << dc_address[1:0]);
wb_we <= dc_wr;
end
end
// Cycle
for (i=0; i<WB_N; i=i+1)
assign wb_match[i] = (dc_address[27:24] == i);
always @(posedge clk)
if (rst)
wb_cyc <= 0;
else
wb_cyc <= (wb_cyc & ~wb_ack) | (wb_match & {WB_N{wb_start}});
// Ack
always @(posedge clk)
wb_ack_r <= |wb_ack;
// Read data
always @(*)
begin : wb_or
integer i;
wb_rdata_or = 0;
for (i=0; i<WB_N; i=i+1)
wb_rdata_or[WB_DW-1:0] = wb_rdata_or[WB_DW-1:0] | wb_rdata[WB_DW*i+:WB_DW];
end
always @(posedge clk)
wb_rdata_r <= wb_rdata_or;
// IBus
// ----
assign ic_ready = ~ram_user;
always @(posedge clk)
ir_valid <= ic_valid & ic_ready;
assign ir_error = 1'b0;
assign ir_inst = ram_rdata;
// DBus
// ----
assign dc_ready = (dc_valid & ~dc_address[31]) | wb_start;
always @(posedge clk)
dr_ready_ram <= dc_valid & ~dc_address[31] & ~dc_wr;
assign dr_ready = dr_ready_ram | (wb_ack_r & ~wb_we); // wb_we is still valid
assign dr_error = 1'b0;
assign dr_data = dr_ready_ram ? ram_rdata : wb_rdata_r;
endmodule // soc_vex_bridge

2
gateware/rtl/top.v
View File

@ -101,7 +101,7 @@ module top (
// SoC
// ---
soc_picorv32_base #(
soc_vex_base #(
.WB_N (WN),
.WB_DW (32),
.WB_AW (16),