gateware: Switch to using Vex CPU
It's a good ~ 3.5x faster than the PicoRV32 (in number of cycles), which allows to shutdown the system clock more and reduce power a bit as well. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>master
parent
5a98883e03
commit
641ac1e3ef
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@ -12,7 +12,10 @@ PROJ_RTL_SRCS := $(addprefix rtl/, \
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soc_picorv32_bridge.v \
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soc_spram.v \
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soc_usb_buf_bridge.v \
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soc_vex_bridge.v \
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soc_vex_base.v \
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sysmgr_3.v \
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VexRiscv.v \
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xclk_cnt.v \
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xclk_pulse.v \
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)
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,174 @@
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/*
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* soc_vex_base.v
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*
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* vim: ts=4 sw=4
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*
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* Copyright (C) 2019-2023 Sylvain Munaut <tnt@246tNt.com>
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* SPDX-License-Identifier: CERN-OHL-P-2.0
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*/
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`default_nettype none
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module soc_vex_base #(
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parameter integer WB_N = 6,
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parameter integer WB_DW = 32,
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parameter integer WB_AW = 16,
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parameter integer BRAM_AW = 8, /* Default 1k */
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parameter integer SPRAM_AW = 14, /* 14 => 64k, 15 => 128k */
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/* auto */
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parameter integer WB_MW = WB_DW / 8,
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parameter integer WB_RW = WB_DW * WB_N,
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parameter integer WB_AI = $clog2(WB_MW)
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)(
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// Wishbone
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output wire [WB_AW-1:0] wb_addr,
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input wire [WB_RW-1:0] wb_rdata,
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output wire [WB_DW-1:0] wb_wdata,
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output wire [WB_MW-1:0] wb_wmsk,
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output wire wb_we,
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output wire [WB_N -1:0] wb_cyc,
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input wire [WB_N -1:0] wb_ack,
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// Clock / Reset
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input wire clk,
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input wire rst
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);
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// Signals
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// -------
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// Vex ISimpleBus
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wire ic_valid;
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wire ic_ready;
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wire [31:0] ic_pc;
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wire ir_valid;
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wire ir_error;
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wire [31:0] ir_inst;
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// Vex DSimpleBus
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wire dc_valid;
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wire dc_ready;
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wire dc_wr;
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wire [31:0] dc_address;
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wire [31:0] dc_data;
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wire [ 1:0] dc_size;
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wire dr_ready;
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wire dr_error;
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wire [31:0] dr_data;
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// RAM
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// BRAM
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wire [14:0] bram_addr;
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wire [31:0] bram_rdata;
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wire [31:0] bram_wdata;
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wire [ 3:0] bram_wmsk;
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wire bram_we;
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// SPRAM
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wire [14:0] spram_addr;
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wire [31:0] spram_rdata;
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wire [31:0] spram_wdata;
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wire [ 3:0] spram_wmsk;
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wire spram_we;
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// CPU
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// ---
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VexRiscv cpu_I (
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.iBus_cmd_valid (ic_valid),
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.iBus_cmd_ready (ic_ready),
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.iBus_cmd_payload_pc (ic_pc),
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.iBus_rsp_valid (ir_valid),
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.iBus_rsp_payload_error (ir_error),
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.iBus_rsp_payload_inst (ir_inst),
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.dBus_cmd_valid (dc_valid),
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.dBus_cmd_ready (dc_ready),
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.dBus_cmd_payload_wr (dc_wr),
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.dBus_cmd_payload_address (dc_address),
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.dBus_cmd_payload_data (dc_data),
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.dBus_cmd_payload_size (dc_size),
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.dBus_rsp_ready (dr_ready),
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.dBus_rsp_error (dr_error),
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.dBus_rsp_data (dr_data),
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.clk (clk),
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.reset (rst)
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);
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// Bus interface
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// -------------
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soc_vex_bridge #(
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.WB_N (WB_N),
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.WB_DW(WB_DW),
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.WB_AW(WB_AW),
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.WB_AI(WB_AI)
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) vb_I (
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.ic_valid (ic_valid),
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.ic_ready (ic_ready),
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.ic_pc (ic_pc),
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.ir_valid (ir_valid),
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.ir_error (ir_error),
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.ir_inst (ir_inst),
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.dc_valid (dc_valid),
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.dc_ready (dc_ready),
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.dc_wr (dc_wr),
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.dc_address (dc_address),
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.dc_data (dc_data),
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.dc_size (dc_size),
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.dr_ready (dr_ready),
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.dr_error (dr_error),
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.dr_data (dr_data),
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.bram_addr (bram_addr),
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.bram_rdata (bram_rdata),
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.bram_wdata (bram_wdata),
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.bram_wmsk (bram_wmsk),
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.bram_we (bram_we),
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.spram_addr (spram_addr),
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.spram_rdata (spram_rdata),
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.spram_wdata (spram_wdata),
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.spram_wmsk (spram_wmsk),
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.spram_we (spram_we),
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.wb_addr (wb_addr),
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.wb_wdata (wb_wdata),
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.wb_wmsk (wb_wmsk),
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.wb_rdata (wb_rdata),
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.wb_cyc (wb_cyc),
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.wb_we (wb_we),
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.wb_ack (wb_ack),
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.clk (clk),
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.rst (rst)
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);
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// Local memory
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// ------------
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// Boot memory
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soc_bram #(
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.SIZE(1 << BRAM_AW),
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.INIT_FILE("boot.hex")
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) bram_I (
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.addr (bram_addr[BRAM_AW-1:0]),
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.rdata (bram_rdata),
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.wdata (bram_wdata),
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.wmsk (bram_wmsk),
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.we (bram_we),
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.clk (clk)
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);
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// Main memory
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soc_spram #(
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.AW(SPRAM_AW)
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) spram_I (
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.addr (spram_addr[SPRAM_AW-1:0]),
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.rdata (spram_rdata),
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.wdata (spram_wdata),
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.wmsk (spram_wmsk),
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.we (spram_we),
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.clk (clk)
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);
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endmodule // soc_vex_base
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@ -0,0 +1,203 @@
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/*
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* soc_vex_bridge.v
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*
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* vim: ts=4 sw=4
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*
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* Copyright (C) 2020-2023 Sylvain Munaut <tnt@246tNt.com>
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* SPDX-License-Identifier: CERN-OHL-P-2.0
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*/
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`default_nettype none
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module soc_vex_bridge #(
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parameter integer WB_N = 8,
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parameter integer WB_DW = 32,
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parameter integer WB_AW = 16,
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parameter integer WB_AI = 2
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)(
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/* Vex ISimpleBus */
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input wire ic_valid,
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output wire ic_ready,
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input wire [31:0] ic_pc,
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output reg ir_valid,
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output wire ir_error,
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output wire [31:0] ir_inst,
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/* Vex DSimpleBus */
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input wire dc_valid,
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output wire dc_ready,
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input wire dc_wr,
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input wire [31:0] dc_address,
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input wire [31:0] dc_data,
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input wire [ 1:0] dc_size,
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output wire dr_ready,
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output wire dr_error,
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output wire [31:0] dr_data,
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/* BRAM */
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output wire [14:0] bram_addr,
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input wire [31:0] bram_rdata,
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output wire [31:0] bram_wdata,
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output wire [ 3:0] bram_wmsk,
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output wire bram_we,
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/* SPRAM */
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output wire [14:0] spram_addr,
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input wire [31:0] spram_rdata,
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output wire [31:0] spram_wdata,
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output wire [ 3:0] spram_wmsk,
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output wire spram_we,
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/* Wishbone buses */
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output reg [WB_AW-1:0] wb_addr,
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input wire [(WB_DW*WB_N)-1:0] wb_rdata,
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output reg [WB_DW-1:0] wb_wdata,
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output reg [(WB_DW/8)-1:0] wb_wmsk,
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output reg wb_we,
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output reg [WB_N-1:0] wb_cyc,
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input wire [WB_N-1:0] wb_ack,
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/* Clock / Reset */
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input wire clk,
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input wire rst
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);
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genvar i;
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// Signals
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// -------
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wire [31:0] ram_addr;
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wire [31:0] ram_rdata;
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wire [31:0] ram_wdata;
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wire [ 3:0] ram_wmsk;
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wire ram_we;
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wire ram_user; // 0=IBus 1=DBus
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reg ram_sel_r;
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wire wb_start;
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reg wb_busy;
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wire [WB_N-1:0] wb_match;
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reg wb_ack_r;
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reg [ 31:0] wb_rdata_or;
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reg [ 31:0] wb_rdata_r;
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reg dr_ready_ram;
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// RAM access
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// ----------
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// BRAM : 0x00000000 -> 0x000003ff
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// SPRAM : 0x00020000 -> 0x0003ffff
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// Commands
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assign ram_user = dc_valid & ~dc_address[31];
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assign ram_addr = ram_user ? dc_address : ic_pc;
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assign ram_wdata = dc_data;
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assign ram_wmsk = ~(((1 << (1 << dc_size)) - 1) << dc_address[1:0]);
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assign ram_we = ram_user & dc_wr;
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// Keep some info about the access
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always @(posedge clk)
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ram_sel_r <= ram_addr[17];
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// BRAM
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assign bram_addr = ram_addr[16:2];
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assign bram_wdata = ram_wdata;
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assign bram_wmsk = ram_wmsk;
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assign bram_we = ram_we & ~ram_addr[17];
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// SPRAM
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assign spram_addr = ram_addr[16:2];
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assign spram_wdata = ram_wdata;
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assign spram_wmsk = ram_wmsk;
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assign spram_we = ram_we & ram_addr[17];
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// Read Mux
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assign ram_rdata = ram_sel_r ? spram_rdata : bram_rdata;
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// Wishbone
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// --------
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// wb[x] = 0x8x000000 - 0x8xffffff
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// Busy
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assign wb_start = dc_valid & dc_address[31] & ~wb_busy;
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always @(posedge clk)
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if (rst)
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wb_busy <= 1'b0;
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else
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wb_busy <= (wb_busy & ~wb_ack_r) | wb_start;
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// Register to keep value stable during bus access
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// Wishbone need values to be stable
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// But the Vex Bus won't do that unless we delay the 'dc_ready'
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// and we can't ack the command and provide response in same cycle
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// So easier to save those in the same cycle we do the decode
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// and ack directly
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always @(posedge clk)
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begin
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if (wb_start) begin
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wb_addr <= dc_address[WB_AW+1:2];
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wb_wdata <= dc_data;
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wb_wmsk <= ~(((1 << (1 << dc_size)) - 1) << dc_address[1:0]);
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wb_we <= dc_wr;
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end
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end
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// Cycle
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for (i=0; i<WB_N; i=i+1)
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assign wb_match[i] = (dc_address[27:24] == i);
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always @(posedge clk)
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if (rst)
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wb_cyc <= 0;
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else
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wb_cyc <= (wb_cyc & ~wb_ack) | (wb_match & {WB_N{wb_start}});
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// Ack
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always @(posedge clk)
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wb_ack_r <= |wb_ack;
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// Read data
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always @(*)
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begin : wb_or
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integer i;
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wb_rdata_or = 0;
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for (i=0; i<WB_N; i=i+1)
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wb_rdata_or[WB_DW-1:0] = wb_rdata_or[WB_DW-1:0] | wb_rdata[WB_DW*i+:WB_DW];
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end
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always @(posedge clk)
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wb_rdata_r <= wb_rdata_or;
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// IBus
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// ----
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assign ic_ready = ~ram_user;
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always @(posedge clk)
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ir_valid <= ic_valid & ic_ready;
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assign ir_error = 1'b0;
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assign ir_inst = ram_rdata;
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// DBus
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// ----
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assign dc_ready = (dc_valid & ~dc_address[31]) | wb_start;
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always @(posedge clk)
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dr_ready_ram <= dc_valid & ~dc_address[31] & ~dc_wr;
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assign dr_ready = dr_ready_ram | (wb_ack_r & ~wb_we); // wb_we is still valid
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assign dr_error = 1'b0;
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assign dr_data = dr_ready_ram ? ram_rdata : wb_rdata_r;
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endmodule // soc_vex_bridge
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@ -101,7 +101,7 @@ module top (
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// SoC
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// ---
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soc_picorv32_base #(
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soc_vex_base #(
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.WB_N (WN),
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.WB_DW (32),
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.WB_AW (16),
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Reference in New Issue