44 lines
718 B
Verilog
44 lines
718 B
Verilog
/*
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* soc_spram.v
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*
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* vim: ts=4 sw=4
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*
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* Copyright (C) 2020 Sylvain Munaut <tnt@246tNt.com>
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* SPDX-License-Identifier: CERN-OHL-P-2.0
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*/
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`default_nettype none
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module soc_spram #(
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parameter integer AW = 14
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)(
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input wire [AW-1:0] addr,
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output wire [31:0] rdata,
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input wire [31:0] wdata,
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input wire [ 3:0] wmsk,
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input wire we,
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input wire clk
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);
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wire [7:0] msk_nibble = {
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wmsk[3], wmsk[3],
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wmsk[2], wmsk[2],
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wmsk[1], wmsk[1],
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wmsk[0], wmsk[0]
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};
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ice40_spram_gen #(
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.ADDR_WIDTH(AW),
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.DATA_WIDTH(32)
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) spram_I (
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.addr(addr),
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.rd_data(rdata),
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.rd_ena(1'b1),
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.wr_data(wdata),
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.wr_mask(msk_nibble),
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.wr_ena(we),
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.clk(clk)
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);
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endmodule // soc_spram
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