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xmas-snoopy/gateware/rtl/VexRiscv.v

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Verilog
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// Generator : SpinalHDL v1.8.0 git head : 4e3563a282582b41f4eaafc503787757251d23ea
// Component : VexRiscv
// Git hash : b29eb542f278edb8ee2c91863a5b26e76b5932c9
`timescale 1ns/1ps
module VexRiscv (
output iBus_cmd_valid,
input iBus_cmd_ready,
output [31:0] iBus_cmd_payload_pc,
input iBus_rsp_valid,
input iBus_rsp_payload_error,
input [31:0] iBus_rsp_payload_inst,
output dBus_cmd_valid,
input dBus_cmd_ready,
output dBus_cmd_payload_wr,
output [31:0] dBus_cmd_payload_address,
output [31:0] dBus_cmd_payload_data,
output [1:0] dBus_cmd_payload_size,
input dBus_rsp_ready,
input dBus_rsp_error,
input [31:0] dBus_rsp_data,
input clk,
input reset
);
localparam ShiftCtrlEnum_DISABLE_1 = 2'd0;
localparam ShiftCtrlEnum_SLL_1 = 2'd1;
localparam ShiftCtrlEnum_SRL_1 = 2'd2;
localparam ShiftCtrlEnum_SRA_1 = 2'd3;
localparam BranchCtrlEnum_INC = 2'd0;
localparam BranchCtrlEnum_B = 2'd1;
localparam BranchCtrlEnum_JAL = 2'd2;
localparam BranchCtrlEnum_JALR = 2'd3;
localparam AluBitwiseCtrlEnum_XOR_1 = 2'd0;
localparam AluBitwiseCtrlEnum_OR_1 = 2'd1;
localparam AluBitwiseCtrlEnum_AND_1 = 2'd2;
localparam AluCtrlEnum_ADD_SUB = 2'd0;
localparam AluCtrlEnum_SLT_SLTU = 2'd1;
localparam AluCtrlEnum_BITWISE = 2'd2;
localparam Src2CtrlEnum_RS = 2'd0;
localparam Src2CtrlEnum_IMI = 2'd1;
localparam Src2CtrlEnum_IMS = 2'd2;
localparam Src2CtrlEnum_PC = 2'd3;
localparam Src1CtrlEnum_RS = 2'd0;
localparam Src1CtrlEnum_IMU = 2'd1;
localparam Src1CtrlEnum_PC_INCREMENT = 2'd2;
localparam Src1CtrlEnum_URS1 = 2'd3;
wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_ready;
reg [31:0] _zz_RegFilePlugin_regFile_port0;
reg [31:0] _zz_RegFilePlugin_regFile_port1;
wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready;
wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid;
wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error;
wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst;
wire [0:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy;
wire [51:0] _zz_memory_MUL_LOW;
wire [51:0] _zz_memory_MUL_LOW_1;
wire [51:0] _zz_memory_MUL_LOW_2;
wire [51:0] _zz_memory_MUL_LOW_3;
wire [32:0] _zz_memory_MUL_LOW_4;
wire [51:0] _zz_memory_MUL_LOW_5;
wire [49:0] _zz_memory_MUL_LOW_6;
wire [51:0] _zz_memory_MUL_LOW_7;
wire [49:0] _zz_memory_MUL_LOW_8;
wire [31:0] _zz_execute_SHIFT_RIGHT;
wire [32:0] _zz_execute_SHIFT_RIGHT_1;
wire [32:0] _zz_execute_SHIFT_RIGHT_2;
wire [1:0] _zz_IBusSimplePlugin_jump_pcLoad_payload_1;
wire [1:0] _zz_IBusSimplePlugin_jump_pcLoad_payload_2;
wire [31:0] _zz_IBusSimplePlugin_fetchPc_pc;
wire [2:0] _zz_IBusSimplePlugin_fetchPc_pc_1;
wire [11:0] _zz__zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch;
wire [31:0] _zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch_2;
wire [19:0] _zz__zz_2;
wire [11:0] _zz__zz_4;
wire [31:0] _zz__zz_6;
wire [31:0] _zz__zz_6_1;
wire [19:0] _zz__zz_IBusSimplePlugin_predictionJumpInterface_payload;
wire [11:0] _zz__zz_IBusSimplePlugin_predictionJumpInterface_payload_2;
wire _zz_IBusSimplePlugin_predictionJumpInterface_payload_4;
wire _zz_IBusSimplePlugin_predictionJumpInterface_payload_5;
wire _zz_IBusSimplePlugin_predictionJumpInterface_payload_6;
wire [2:0] _zz_IBusSimplePlugin_pending_next;
wire [2:0] _zz_IBusSimplePlugin_pending_next_1;
wire [0:0] _zz_IBusSimplePlugin_pending_next_2;
wire [2:0] _zz_IBusSimplePlugin_pending_next_3;
wire [0:0] _zz_IBusSimplePlugin_pending_next_4;
wire [2:0] _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter;
wire [0:0] _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_1;
wire [2:0] _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_2;
wire [0:0] _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_3;
wire [31:0] _zz__zz_decode_IS_MUL;
wire [31:0] _zz__zz_decode_IS_MUL_1;
wire [31:0] _zz__zz_decode_IS_MUL_2;
wire [31:0] _zz__zz_decode_IS_MUL_3;
wire _zz__zz_decode_IS_MUL_4;
wire [1:0] _zz__zz_decode_IS_MUL_5;
wire [31:0] _zz__zz_decode_IS_MUL_6;
wire [31:0] _zz__zz_decode_IS_MUL_7;
wire _zz__zz_decode_IS_MUL_8;
wire [31:0] _zz__zz_decode_IS_MUL_9;
wire [0:0] _zz__zz_decode_IS_MUL_10;
wire [31:0] _zz__zz_decode_IS_MUL_11;
wire [31:0] _zz__zz_decode_IS_MUL_12;
wire [16:0] _zz__zz_decode_IS_MUL_13;
wire _zz__zz_decode_IS_MUL_14;
wire [1:0] _zz__zz_decode_IS_MUL_15;
wire [31:0] _zz__zz_decode_IS_MUL_16;
wire [31:0] _zz__zz_decode_IS_MUL_17;
wire _zz__zz_decode_IS_MUL_18;
wire [31:0] _zz__zz_decode_IS_MUL_19;
wire [0:0] _zz__zz_decode_IS_MUL_20;
wire [31:0] _zz__zz_decode_IS_MUL_21;
wire [31:0] _zz__zz_decode_IS_MUL_22;
wire [12:0] _zz__zz_decode_IS_MUL_23;
wire _zz__zz_decode_IS_MUL_24;
wire [1:0] _zz__zz_decode_IS_MUL_25;
wire [31:0] _zz__zz_decode_IS_MUL_26;
wire _zz__zz_decode_IS_MUL_27;
wire [31:0] _zz__zz_decode_IS_MUL_28;
wire [0:0] _zz__zz_decode_IS_MUL_29;
wire [0:0] _zz__zz_decode_IS_MUL_30;
wire [31:0] _zz__zz_decode_IS_MUL_31;
wire [0:0] _zz__zz_decode_IS_MUL_32;
wire [31:0] _zz__zz_decode_IS_MUL_33;
wire [8:0] _zz__zz_decode_IS_MUL_34;
wire [0:0] _zz__zz_decode_IS_MUL_35;
wire [3:0] _zz__zz_decode_IS_MUL_36;
wire [31:0] _zz__zz_decode_IS_MUL_37;
wire [31:0] _zz__zz_decode_IS_MUL_38;
wire _zz__zz_decode_IS_MUL_39;
wire [31:0] _zz__zz_decode_IS_MUL_40;
wire [0:0] _zz__zz_decode_IS_MUL_41;
wire [31:0] _zz__zz_decode_IS_MUL_42;
wire [31:0] _zz__zz_decode_IS_MUL_43;
wire [0:0] _zz__zz_decode_IS_MUL_44;
wire [31:0] _zz__zz_decode_IS_MUL_45;
wire [31:0] _zz__zz_decode_IS_MUL_46;
wire [3:0] _zz__zz_decode_IS_MUL_47;
wire [31:0] _zz__zz_decode_IS_MUL_48;
wire [31:0] _zz__zz_decode_IS_MUL_49;
wire [0:0] _zz__zz_decode_IS_MUL_50;
wire [31:0] _zz__zz_decode_IS_MUL_51;
wire [31:0] _zz__zz_decode_IS_MUL_52;
wire [0:0] _zz__zz_decode_IS_MUL_53;
wire [31:0] _zz__zz_decode_IS_MUL_54;
wire [31:0] _zz__zz_decode_IS_MUL_55;
wire _zz__zz_decode_IS_MUL_56;
wire _zz__zz_decode_IS_MUL_57;
wire [31:0] _zz__zz_decode_IS_MUL_58;
wire [0:0] _zz__zz_decode_IS_MUL_59;
wire [0:0] _zz__zz_decode_IS_MUL_60;
wire [0:0] _zz__zz_decode_IS_MUL_61;
wire [31:0] _zz__zz_decode_IS_MUL_62;
wire [31:0] _zz__zz_decode_IS_MUL_63;
wire [4:0] _zz__zz_decode_IS_MUL_64;
wire [1:0] _zz__zz_decode_IS_MUL_65;
wire _zz__zz_decode_IS_MUL_66;
wire _zz__zz_decode_IS_MUL_67;
wire _zz__zz_decode_IS_MUL_68;
wire [0:0] _zz__zz_decode_IS_MUL_69;
wire [2:0] _zz__zz_decode_IS_MUL_70;
wire [31:0] _zz__zz_decode_IS_MUL_71;
wire [31:0] _zz__zz_decode_IS_MUL_72;
wire [31:0] _zz__zz_decode_IS_MUL_73;
wire [31:0] _zz__zz_decode_IS_MUL_74;
wire [31:0] _zz__zz_decode_IS_MUL_75;
wire [1:0] _zz__zz_decode_IS_MUL_76;
wire _zz__zz_decode_IS_MUL_77;
wire [31:0] _zz__zz_decode_IS_MUL_78;
wire _zz__zz_decode_IS_MUL_79;
wire [31:0] _zz__zz_decode_IS_MUL_80;
wire _zz_RegFilePlugin_regFile_port;
wire _zz_decode_RegFilePlugin_rs1Data;
wire _zz_RegFilePlugin_regFile_port_1;
wire _zz_decode_RegFilePlugin_rs2Data;
wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA;
wire [2:0] _zz__zz_decode_SRC1;
wire [4:0] _zz__zz_decode_SRC1_1;
wire [11:0] _zz__zz_decode_SRC2_2;
wire [31:0] _zz_execute_SrcPlugin_addSub;
wire [31:0] _zz_execute_SrcPlugin_addSub_1;
wire [31:0] _zz_execute_SrcPlugin_addSub_2;
wire [31:0] _zz_execute_SrcPlugin_addSub_3;
wire [31:0] _zz_execute_SrcPlugin_addSub_4;
wire [31:0] _zz_execute_SrcPlugin_addSub_5;
wire [31:0] _zz_execute_SrcPlugin_addSub_6;
wire [19:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_2;
wire [11:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_4;
wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6;
wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1;
wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2;
wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2_2;
wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4;
wire _zz_execute_BranchPlugin_branch_src2_6;
wire _zz_execute_BranchPlugin_branch_src2_7;
wire _zz_execute_BranchPlugin_branch_src2_8;
wire [2:0] _zz_execute_BranchPlugin_branch_src2_9;
wire [65:0] _zz_writeBack_MulPlugin_result;
wire [65:0] _zz_writeBack_MulPlugin_result_1;
wire [31:0] _zz__zz_decode_RS2_2;
wire [31:0] _zz__zz_decode_RS2_2_1;
wire [51:0] memory_MUL_LOW;
wire [31:0] memory_MEMORY_READ_DATA;
wire [33:0] memory_MUL_HH;
wire [33:0] execute_MUL_HH;
wire [33:0] execute_MUL_HL;
wire [33:0] execute_MUL_LH;
wire [31:0] execute_MUL_LL;
wire [31:0] execute_BRANCH_CALC;
wire execute_BRANCH_DO;
wire [31:0] execute_SHIFT_RIGHT;
wire [31:0] writeBack_REGFILE_WRITE_DATA;
wire [31:0] memory_REGFILE_WRITE_DATA;
wire [31:0] execute_REGFILE_WRITE_DATA;
wire [1:0] memory_MEMORY_ADDRESS_LOW;
wire [1:0] execute_MEMORY_ADDRESS_LOW;
wire decode_PREDICTION_HAD_BRANCHED2;
wire [31:0] decode_SRC2;
wire [31:0] decode_SRC1;
wire decode_SRC2_FORCE_ZERO;
wire memory_IS_MUL;
wire execute_IS_MUL;
wire decode_IS_MUL;
wire [1:0] _zz_decode_to_execute_BRANCH_CTRL;
wire [1:0] _zz_decode_to_execute_BRANCH_CTRL_1;
wire [1:0] _zz_execute_to_memory_SHIFT_CTRL;
wire [1:0] _zz_execute_to_memory_SHIFT_CTRL_1;
wire [1:0] decode_SHIFT_CTRL;
wire [1:0] _zz_decode_SHIFT_CTRL;
wire [1:0] _zz_decode_to_execute_SHIFT_CTRL;
wire [1:0] _zz_decode_to_execute_SHIFT_CTRL_1;
wire [1:0] decode_ALU_BITWISE_CTRL;
wire [1:0] _zz_decode_ALU_BITWISE_CTRL;
wire [1:0] _zz_decode_to_execute_ALU_BITWISE_CTRL;
wire [1:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1;
wire decode_SRC_LESS_UNSIGNED;
wire [1:0] decode_ALU_CTRL;
wire [1:0] _zz_decode_ALU_CTRL;
wire [1:0] _zz_decode_to_execute_ALU_CTRL;
wire [1:0] _zz_decode_to_execute_ALU_CTRL_1;
wire decode_MEMORY_STORE;
wire execute_BYPASSABLE_MEMORY_STAGE;
wire decode_BYPASSABLE_MEMORY_STAGE;
wire decode_BYPASSABLE_EXECUTE_STAGE;
wire decode_MEMORY_ENABLE;
wire [31:0] memory_FORMAL_PC_NEXT;
wire [31:0] execute_FORMAL_PC_NEXT;
wire [31:0] decode_FORMAL_PC_NEXT;
wire [31:0] memory_PC;
wire writeBack_IS_MUL;
wire [33:0] writeBack_MUL_HH;
wire [51:0] writeBack_MUL_LOW;
wire [33:0] memory_MUL_HL;
wire [33:0] memory_MUL_LH;
wire [31:0] memory_MUL_LL;
wire [31:0] memory_BRANCH_CALC;
wire memory_BRANCH_DO;
wire [31:0] execute_PC;
wire execute_PREDICTION_HAD_BRANCHED2;
(* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ;
wire execute_BRANCH_COND_RESULT;
wire [1:0] execute_BRANCH_CTRL;
wire [1:0] _zz_execute_BRANCH_CTRL;
wire decode_RS2_USE;
wire decode_RS1_USE;
wire [31:0] _zz_decode_RS2;
wire execute_REGFILE_WRITE_VALID;
wire execute_BYPASSABLE_EXECUTE_STAGE;
wire memory_REGFILE_WRITE_VALID;
wire [31:0] memory_INSTRUCTION;
wire memory_BYPASSABLE_MEMORY_STAGE;
wire writeBack_REGFILE_WRITE_VALID;
reg [31:0] decode_RS2;
reg [31:0] decode_RS1;
wire [31:0] memory_SHIFT_RIGHT;
reg [31:0] _zz_decode_RS2_1;
wire [1:0] memory_SHIFT_CTRL;
wire [1:0] _zz_memory_SHIFT_CTRL;
wire [1:0] execute_SHIFT_CTRL;
wire [1:0] _zz_execute_SHIFT_CTRL;
wire execute_SRC_LESS_UNSIGNED;
wire execute_SRC2_FORCE_ZERO;
wire execute_SRC_USE_SUB_LESS;
wire [31:0] _zz_decode_to_execute_PC;
wire [31:0] _zz_decode_to_execute_RS2;
wire [1:0] decode_SRC2_CTRL;
wire [1:0] _zz_decode_SRC2_CTRL;
wire [31:0] _zz_decode_to_execute_RS1;
wire [1:0] decode_SRC1_CTRL;
wire [1:0] _zz_decode_SRC1_CTRL;
wire decode_SRC_USE_SUB_LESS;
wire decode_SRC_ADD_ZERO;
wire [31:0] execute_SRC_ADD_SUB;
wire execute_SRC_LESS;
wire [1:0] execute_ALU_CTRL;
wire [1:0] _zz_execute_ALU_CTRL;
wire [31:0] execute_SRC2;
wire [31:0] execute_SRC1;
wire [1:0] execute_ALU_BITWISE_CTRL;
wire [1:0] _zz_execute_ALU_BITWISE_CTRL;
wire [31:0] _zz_lastStageRegFileWrite_payload_address;
wire _zz_lastStageRegFileWrite_valid;
reg _zz_1;
wire [31:0] decode_INSTRUCTION_ANTICIPATED;
reg decode_REGFILE_WRITE_VALID;
wire [1:0] _zz_decode_BRANCH_CTRL;
wire [1:0] _zz_decode_SHIFT_CTRL_1;
wire [1:0] _zz_decode_ALU_BITWISE_CTRL_1;
wire [1:0] _zz_decode_ALU_CTRL_1;
wire [1:0] _zz_decode_SRC2_CTRL_1;
wire [1:0] _zz_decode_SRC1_CTRL_1;
reg [31:0] _zz_decode_RS2_2;
wire writeBack_MEMORY_ENABLE;
wire [1:0] writeBack_MEMORY_ADDRESS_LOW;
wire [31:0] writeBack_MEMORY_READ_DATA;
wire memory_MEMORY_STORE;
wire memory_MEMORY_ENABLE;
wire [31:0] execute_SRC_ADD;
(* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ;
wire [31:0] execute_INSTRUCTION;
wire execute_MEMORY_STORE;
wire execute_MEMORY_ENABLE;
wire execute_ALIGNEMENT_FAULT;
wire [1:0] decode_BRANCH_CTRL;
wire [1:0] _zz_decode_BRANCH_CTRL_1;
reg [31:0] _zz_decode_to_execute_FORMAL_PC_NEXT;
wire [31:0] decode_PC;
wire [31:0] decode_INSTRUCTION;
wire [31:0] writeBack_PC;
wire [31:0] writeBack_INSTRUCTION;
wire decode_arbitration_haltItself;
reg decode_arbitration_haltByOther;
reg decode_arbitration_removeIt;
wire decode_arbitration_flushIt;
reg decode_arbitration_flushNext;
reg decode_arbitration_isValid;
wire decode_arbitration_isStuck;
wire decode_arbitration_isStuckByOthers;
wire decode_arbitration_isFlushed;
wire decode_arbitration_isMoving;
wire decode_arbitration_isFiring;
reg execute_arbitration_haltItself;
wire execute_arbitration_haltByOther;
reg execute_arbitration_removeIt;
wire execute_arbitration_flushIt;
wire execute_arbitration_flushNext;
reg execute_arbitration_isValid;
wire execute_arbitration_isStuck;
wire execute_arbitration_isStuckByOthers;
wire execute_arbitration_isFlushed;
wire execute_arbitration_isMoving;
wire execute_arbitration_isFiring;
reg memory_arbitration_haltItself;
wire memory_arbitration_haltByOther;
reg memory_arbitration_removeIt;
wire memory_arbitration_flushIt;
reg memory_arbitration_flushNext;
reg memory_arbitration_isValid;
wire memory_arbitration_isStuck;
wire memory_arbitration_isStuckByOthers;
wire memory_arbitration_isFlushed;
wire memory_arbitration_isMoving;
wire memory_arbitration_isFiring;
wire writeBack_arbitration_haltItself;
wire writeBack_arbitration_haltByOther;
reg writeBack_arbitration_removeIt;
wire writeBack_arbitration_flushIt;
wire writeBack_arbitration_flushNext;
reg writeBack_arbitration_isValid;
wire writeBack_arbitration_isStuck;
wire writeBack_arbitration_isStuckByOthers;
wire writeBack_arbitration_isFlushed;
wire writeBack_arbitration_isMoving;
wire writeBack_arbitration_isFiring;
wire [31:0] lastStageInstruction /* verilator public */ ;
wire [31:0] lastStagePc /* verilator public */ ;
wire lastStageIsValid /* verilator public */ ;
wire lastStageIsFiring /* verilator public */ ;
wire IBusSimplePlugin_fetcherHalt;
wire IBusSimplePlugin_forceNoDecodeCond;
reg IBusSimplePlugin_incomingInstruction;
wire IBusSimplePlugin_predictionJumpInterface_valid;
(* keep , syn_keep *) wire [31:0] IBusSimplePlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ;
reg IBusSimplePlugin_decodePrediction_cmd_hadBranch;
wire IBusSimplePlugin_decodePrediction_rsp_wasWrong;
wire IBusSimplePlugin_pcValids_0;
wire IBusSimplePlugin_pcValids_1;
wire IBusSimplePlugin_pcValids_2;
wire IBusSimplePlugin_pcValids_3;
wire BranchPlugin_jumpInterface_valid;
wire [31:0] BranchPlugin_jumpInterface_payload;
wire BranchPlugin_inDebugNoFetchFlag;
wire IBusSimplePlugin_externalFlush;
wire IBusSimplePlugin_jump_pcLoad_valid;
wire [31:0] IBusSimplePlugin_jump_pcLoad_payload;
wire [1:0] _zz_IBusSimplePlugin_jump_pcLoad_payload;
wire IBusSimplePlugin_fetchPc_output_valid;
wire IBusSimplePlugin_fetchPc_output_ready;
wire [31:0] IBusSimplePlugin_fetchPc_output_payload;
reg [31:0] IBusSimplePlugin_fetchPc_pcReg /* verilator public */ ;
reg IBusSimplePlugin_fetchPc_correction;
reg IBusSimplePlugin_fetchPc_correctionReg;
wire IBusSimplePlugin_fetchPc_output_fire;
wire IBusSimplePlugin_fetchPc_corrected;
reg IBusSimplePlugin_fetchPc_pcRegPropagate;
reg IBusSimplePlugin_fetchPc_booted;
reg IBusSimplePlugin_fetchPc_inc;
wire when_Fetcher_l134;
wire IBusSimplePlugin_fetchPc_output_fire_1;
wire when_Fetcher_l134_1;
reg [31:0] IBusSimplePlugin_fetchPc_pc;
reg IBusSimplePlugin_fetchPc_flushed;
wire when_Fetcher_l161;
wire IBusSimplePlugin_iBusRsp_redoFetch;
wire IBusSimplePlugin_iBusRsp_stages_0_input_valid;
wire IBusSimplePlugin_iBusRsp_stages_0_input_ready;
wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_input_payload;
wire IBusSimplePlugin_iBusRsp_stages_0_output_valid;
wire IBusSimplePlugin_iBusRsp_stages_0_output_ready;
wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_output_payload;
reg IBusSimplePlugin_iBusRsp_stages_0_halt;
wire IBusSimplePlugin_iBusRsp_stages_1_input_valid;
wire IBusSimplePlugin_iBusRsp_stages_1_input_ready;
wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_input_payload;
wire IBusSimplePlugin_iBusRsp_stages_1_output_valid;
wire IBusSimplePlugin_iBusRsp_stages_1_output_ready;
wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_output_payload;
wire IBusSimplePlugin_iBusRsp_stages_1_halt;
wire _zz_IBusSimplePlugin_iBusRsp_stages_0_input_ready;
wire _zz_IBusSimplePlugin_iBusRsp_stages_1_input_ready;
wire IBusSimplePlugin_iBusRsp_flush;
wire _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready;
wire _zz_IBusSimplePlugin_iBusRsp_stages_1_input_valid;
reg _zz_IBusSimplePlugin_iBusRsp_stages_1_input_valid_1;
reg IBusSimplePlugin_iBusRsp_readyForError;
wire IBusSimplePlugin_iBusRsp_output_valid;
wire IBusSimplePlugin_iBusRsp_output_ready;
wire [31:0] IBusSimplePlugin_iBusRsp_output_payload_pc;
wire IBusSimplePlugin_iBusRsp_output_payload_rsp_error;
wire [31:0] IBusSimplePlugin_iBusRsp_output_payload_rsp_inst;
wire IBusSimplePlugin_iBusRsp_output_payload_isRvc;
wire IBusSimplePlugin_injector_decodeInput_valid;
wire IBusSimplePlugin_injector_decodeInput_ready;
wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_pc;
wire IBusSimplePlugin_injector_decodeInput_payload_rsp_error;
wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst;
wire IBusSimplePlugin_injector_decodeInput_payload_isRvc;
reg _zz_IBusSimplePlugin_injector_decodeInput_valid;
reg [31:0] _zz_IBusSimplePlugin_injector_decodeInput_payload_pc;
reg _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_error;
reg [31:0] _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst;
reg _zz_IBusSimplePlugin_injector_decodeInput_payload_isRvc;
wire when_Fetcher_l323;
reg IBusSimplePlugin_injector_nextPcCalc_valids_0;
wire when_Fetcher_l332;
reg IBusSimplePlugin_injector_nextPcCalc_valids_1;
wire when_Fetcher_l332_1;
reg IBusSimplePlugin_injector_nextPcCalc_valids_2;
wire when_Fetcher_l332_2;
reg IBusSimplePlugin_injector_nextPcCalc_valids_3;
wire when_Fetcher_l332_3;
reg IBusSimplePlugin_injector_nextPcCalc_valids_4;
wire when_Fetcher_l332_4;
reg [31:0] IBusSimplePlugin_injector_formal_rawInDecode;
wire _zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch;
reg [18:0] _zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch_1;
wire _zz_2;
reg [10:0] _zz_3;
wire _zz_4;
reg [18:0] _zz_5;
reg _zz_6;
wire _zz_IBusSimplePlugin_predictionJumpInterface_payload;
reg [10:0] _zz_IBusSimplePlugin_predictionJumpInterface_payload_1;
wire _zz_IBusSimplePlugin_predictionJumpInterface_payload_2;
reg [18:0] _zz_IBusSimplePlugin_predictionJumpInterface_payload_3;
wire IBusSimplePlugin_cmd_valid;
wire IBusSimplePlugin_cmd_ready;
wire [31:0] IBusSimplePlugin_cmd_payload_pc;
wire IBusSimplePlugin_pending_inc;
wire IBusSimplePlugin_pending_dec;
reg [2:0] IBusSimplePlugin_pending_value;
wire [2:0] IBusSimplePlugin_pending_next;
wire IBusSimplePlugin_cmdFork_canEmit;
wire when_IBusSimplePlugin_l305;
wire IBusSimplePlugin_cmd_fire;
wire IBusSimplePlugin_rspJoin_rspBuffer_output_valid;
wire IBusSimplePlugin_rspJoin_rspBuffer_output_ready;
wire IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error;
wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst;
reg [2:0] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter;
wire iBus_rsp_toStream_valid;
wire iBus_rsp_toStream_ready;
wire iBus_rsp_toStream_payload_error;
wire [31:0] iBus_rsp_toStream_payload_inst;
wire IBusSimplePlugin_rspJoin_rspBuffer_flush;
wire toplevel_IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_fire;
wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_pc;
reg IBusSimplePlugin_rspJoin_fetchRsp_rsp_error;
wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst;
wire IBusSimplePlugin_rspJoin_fetchRsp_isRvc;
wire when_IBusSimplePlugin_l376;
wire IBusSimplePlugin_rspJoin_join_valid;
wire IBusSimplePlugin_rspJoin_join_ready;
wire [31:0] IBusSimplePlugin_rspJoin_join_payload_pc;
wire IBusSimplePlugin_rspJoin_join_payload_rsp_error;
wire [31:0] IBusSimplePlugin_rspJoin_join_payload_rsp_inst;
wire IBusSimplePlugin_rspJoin_join_payload_isRvc;
wire IBusSimplePlugin_rspJoin_exceptionDetected;
wire IBusSimplePlugin_rspJoin_join_fire;
wire IBusSimplePlugin_rspJoin_join_fire_1;
wire _zz_IBusSimplePlugin_iBusRsp_output_valid;
wire _zz_dBus_cmd_valid;
reg execute_DBusSimplePlugin_skipCmd;
reg [31:0] _zz_dBus_cmd_payload_data;
wire when_DBusSimplePlugin_l428;
reg [3:0] _zz_execute_DBusSimplePlugin_formalMask;
wire [3:0] execute_DBusSimplePlugin_formalMask;
wire when_DBusSimplePlugin_l482;
reg [31:0] writeBack_DBusSimplePlugin_rspShifted;
wire [1:0] switch_Misc_l226;
wire _zz_writeBack_DBusSimplePlugin_rspFormated;
reg [31:0] _zz_writeBack_DBusSimplePlugin_rspFormated_1;
wire _zz_writeBack_DBusSimplePlugin_rspFormated_2;
reg [31:0] _zz_writeBack_DBusSimplePlugin_rspFormated_3;
reg [31:0] writeBack_DBusSimplePlugin_rspFormated;
wire when_DBusSimplePlugin_l558;
wire [23:0] _zz_decode_IS_MUL;
wire _zz_decode_IS_MUL_1;
wire _zz_decode_IS_MUL_2;
wire _zz_decode_IS_MUL_3;
wire [1:0] _zz_decode_SRC1_CTRL_2;
wire [1:0] _zz_decode_SRC2_CTRL_2;
wire [1:0] _zz_decode_ALU_CTRL_2;
wire [1:0] _zz_decode_ALU_BITWISE_CTRL_2;
wire [1:0] _zz_decode_SHIFT_CTRL_2;
wire [1:0] _zz_decode_BRANCH_CTRL_2;
wire when_RegFilePlugin_l63;
wire [4:0] decode_RegFilePlugin_regFileReadAddress1;
wire [4:0] decode_RegFilePlugin_regFileReadAddress2;
wire [31:0] decode_RegFilePlugin_rs1Data;
wire [31:0] decode_RegFilePlugin_rs2Data;
reg lastStageRegFileWrite_valid /* verilator public */ ;
reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ;
reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ;
reg _zz_7;
reg [31:0] execute_IntAluPlugin_bitwise;
reg [31:0] _zz_execute_REGFILE_WRITE_DATA;
reg [31:0] _zz_decode_SRC1;
wire _zz_decode_SRC2;
reg [19:0] _zz_decode_SRC2_1;
wire _zz_decode_SRC2_2;
reg [19:0] _zz_decode_SRC2_3;
reg [31:0] _zz_decode_SRC2_4;
reg [31:0] execute_SrcPlugin_addSub;
wire execute_SrcPlugin_less;
wire [4:0] execute_FullBarrelShifterPlugin_amplitude;
reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed;
wire [31:0] execute_FullBarrelShifterPlugin_reversed;
reg [31:0] _zz_decode_RS2_3;
reg HazardSimplePlugin_src0Hazard;
reg HazardSimplePlugin_src1Hazard;
wire HazardSimplePlugin_writeBackWrites_valid;
wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address;
wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data;
reg HazardSimplePlugin_writeBackBuffer_valid;
reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address;
reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data;
wire HazardSimplePlugin_addr0Match;
wire HazardSimplePlugin_addr1Match;
wire when_HazardSimplePlugin_l47;
wire when_HazardSimplePlugin_l48;
wire when_HazardSimplePlugin_l51;
wire when_HazardSimplePlugin_l45;
wire when_HazardSimplePlugin_l57;
wire when_HazardSimplePlugin_l58;
wire when_HazardSimplePlugin_l48_1;
wire when_HazardSimplePlugin_l51_1;
wire when_HazardSimplePlugin_l45_1;
wire when_HazardSimplePlugin_l57_1;
wire when_HazardSimplePlugin_l58_1;
wire when_HazardSimplePlugin_l48_2;
wire when_HazardSimplePlugin_l51_2;
wire when_HazardSimplePlugin_l45_2;
wire when_HazardSimplePlugin_l57_2;
wire when_HazardSimplePlugin_l58_2;
wire when_HazardSimplePlugin_l105;
wire when_HazardSimplePlugin_l108;
wire when_HazardSimplePlugin_l113;
wire execute_BranchPlugin_eq;
wire [2:0] switch_Misc_l226_1;
reg _zz_execute_BRANCH_COND_RESULT;
reg _zz_execute_BRANCH_COND_RESULT_1;
wire _zz_execute_BranchPlugin_missAlignedTarget;
reg [19:0] _zz_execute_BranchPlugin_missAlignedTarget_1;
wire _zz_execute_BranchPlugin_missAlignedTarget_2;
reg [10:0] _zz_execute_BranchPlugin_missAlignedTarget_3;
wire _zz_execute_BranchPlugin_missAlignedTarget_4;
reg [18:0] _zz_execute_BranchPlugin_missAlignedTarget_5;
reg _zz_execute_BranchPlugin_missAlignedTarget_6;
wire execute_BranchPlugin_missAlignedTarget;
reg [31:0] execute_BranchPlugin_branch_src1;
reg [31:0] execute_BranchPlugin_branch_src2;
wire _zz_execute_BranchPlugin_branch_src2;
reg [19:0] _zz_execute_BranchPlugin_branch_src2_1;
wire _zz_execute_BranchPlugin_branch_src2_2;
reg [10:0] _zz_execute_BranchPlugin_branch_src2_3;
wire _zz_execute_BranchPlugin_branch_src2_4;
reg [18:0] _zz_execute_BranchPlugin_branch_src2_5;
wire [31:0] execute_BranchPlugin_branchAdder;
reg execute_MulPlugin_aSigned;
reg execute_MulPlugin_bSigned;
wire [31:0] execute_MulPlugin_a;
wire [31:0] execute_MulPlugin_b;
wire [1:0] switch_MulPlugin_l87;
wire [15:0] execute_MulPlugin_aULow;
wire [15:0] execute_MulPlugin_bULow;
wire [16:0] execute_MulPlugin_aSLow;
wire [16:0] execute_MulPlugin_bSLow;
wire [16:0] execute_MulPlugin_aHigh;
wire [16:0] execute_MulPlugin_bHigh;
wire [65:0] writeBack_MulPlugin_result;
wire when_MulPlugin_l147;
wire [1:0] switch_MulPlugin_l148;
wire when_Pipeline_l124;
reg [31:0] decode_to_execute_PC;
wire when_Pipeline_l124_1;
reg [31:0] execute_to_memory_PC;
wire when_Pipeline_l124_2;
reg [31:0] memory_to_writeBack_PC;
wire when_Pipeline_l124_3;
reg [31:0] decode_to_execute_INSTRUCTION;
wire when_Pipeline_l124_4;
reg [31:0] execute_to_memory_INSTRUCTION;
wire when_Pipeline_l124_5;
reg [31:0] memory_to_writeBack_INSTRUCTION;
wire when_Pipeline_l124_6;
reg [31:0] decode_to_execute_FORMAL_PC_NEXT;
wire when_Pipeline_l124_7;
reg [31:0] execute_to_memory_FORMAL_PC_NEXT;
wire when_Pipeline_l124_8;
reg decode_to_execute_SRC_USE_SUB_LESS;
wire when_Pipeline_l124_9;
reg decode_to_execute_MEMORY_ENABLE;
wire when_Pipeline_l124_10;
reg execute_to_memory_MEMORY_ENABLE;
wire when_Pipeline_l124_11;
reg memory_to_writeBack_MEMORY_ENABLE;
wire when_Pipeline_l124_12;
reg decode_to_execute_REGFILE_WRITE_VALID;
wire when_Pipeline_l124_13;
reg execute_to_memory_REGFILE_WRITE_VALID;
wire when_Pipeline_l124_14;
reg memory_to_writeBack_REGFILE_WRITE_VALID;
wire when_Pipeline_l124_15;
reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
wire when_Pipeline_l124_16;
reg decode_to_execute_BYPASSABLE_MEMORY_STAGE;
wire when_Pipeline_l124_17;
reg execute_to_memory_BYPASSABLE_MEMORY_STAGE;
wire when_Pipeline_l124_18;
reg decode_to_execute_MEMORY_STORE;
wire when_Pipeline_l124_19;
reg execute_to_memory_MEMORY_STORE;
wire when_Pipeline_l124_20;
reg [1:0] decode_to_execute_ALU_CTRL;
wire when_Pipeline_l124_21;
reg decode_to_execute_SRC_LESS_UNSIGNED;
wire when_Pipeline_l124_22;
reg [1:0] decode_to_execute_ALU_BITWISE_CTRL;
wire when_Pipeline_l124_23;
reg [1:0] decode_to_execute_SHIFT_CTRL;
wire when_Pipeline_l124_24;
reg [1:0] execute_to_memory_SHIFT_CTRL;
wire when_Pipeline_l124_25;
reg [1:0] decode_to_execute_BRANCH_CTRL;
wire when_Pipeline_l124_26;
reg decode_to_execute_IS_MUL;
wire when_Pipeline_l124_27;
reg execute_to_memory_IS_MUL;
wire when_Pipeline_l124_28;
reg memory_to_writeBack_IS_MUL;
wire when_Pipeline_l124_29;
reg [31:0] decode_to_execute_RS1;
wire when_Pipeline_l124_30;
reg [31:0] decode_to_execute_RS2;
wire when_Pipeline_l124_31;
reg decode_to_execute_SRC2_FORCE_ZERO;
wire when_Pipeline_l124_32;
reg [31:0] decode_to_execute_SRC1;
wire when_Pipeline_l124_33;
reg [31:0] decode_to_execute_SRC2;
wire when_Pipeline_l124_34;
reg decode_to_execute_PREDICTION_HAD_BRANCHED2;
wire when_Pipeline_l124_35;
reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW;
wire when_Pipeline_l124_36;
reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW;
wire when_Pipeline_l124_37;
reg [31:0] execute_to_memory_REGFILE_WRITE_DATA;
wire when_Pipeline_l124_38;
reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA;
wire when_Pipeline_l124_39;
reg [31:0] execute_to_memory_SHIFT_RIGHT;
wire when_Pipeline_l124_40;
reg execute_to_memory_BRANCH_DO;
wire when_Pipeline_l124_41;
reg [31:0] execute_to_memory_BRANCH_CALC;
wire when_Pipeline_l124_42;
reg [31:0] execute_to_memory_MUL_LL;
wire when_Pipeline_l124_43;
reg [33:0] execute_to_memory_MUL_LH;
wire when_Pipeline_l124_44;
reg [33:0] execute_to_memory_MUL_HL;
wire when_Pipeline_l124_45;
reg [33:0] execute_to_memory_MUL_HH;
wire when_Pipeline_l124_46;
reg [33:0] memory_to_writeBack_MUL_HH;
wire when_Pipeline_l124_47;
reg [31:0] memory_to_writeBack_MEMORY_READ_DATA;
wire when_Pipeline_l124_48;
reg [51:0] memory_to_writeBack_MUL_LOW;
wire when_Pipeline_l151;
wire when_Pipeline_l154;
wire when_Pipeline_l151_1;
wire when_Pipeline_l154_1;
wire when_Pipeline_l151_2;
wire when_Pipeline_l154_2;
`ifndef SYNTHESIS
reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string;
reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string;
reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string;
reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string;
reg [71:0] decode_SHIFT_CTRL_string;
reg [71:0] _zz_decode_SHIFT_CTRL_string;
reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string;
reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string;
reg [39:0] decode_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string;
reg [63:0] decode_ALU_CTRL_string;
reg [63:0] _zz_decode_ALU_CTRL_string;
reg [63:0] _zz_decode_to_execute_ALU_CTRL_string;
reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string;
reg [31:0] execute_BRANCH_CTRL_string;
reg [31:0] _zz_execute_BRANCH_CTRL_string;
reg [71:0] memory_SHIFT_CTRL_string;
reg [71:0] _zz_memory_SHIFT_CTRL_string;
reg [71:0] execute_SHIFT_CTRL_string;
reg [71:0] _zz_execute_SHIFT_CTRL_string;
reg [23:0] decode_SRC2_CTRL_string;
reg [23:0] _zz_decode_SRC2_CTRL_string;
reg [95:0] decode_SRC1_CTRL_string;
reg [95:0] _zz_decode_SRC1_CTRL_string;
reg [63:0] execute_ALU_CTRL_string;
reg [63:0] _zz_execute_ALU_CTRL_string;
reg [39:0] execute_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string;
reg [31:0] _zz_decode_BRANCH_CTRL_string;
reg [71:0] _zz_decode_SHIFT_CTRL_1_string;
reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string;
reg [63:0] _zz_decode_ALU_CTRL_1_string;
reg [23:0] _zz_decode_SRC2_CTRL_1_string;
reg [95:0] _zz_decode_SRC1_CTRL_1_string;
reg [31:0] decode_BRANCH_CTRL_string;
reg [31:0] _zz_decode_BRANCH_CTRL_1_string;
reg [95:0] _zz_decode_SRC1_CTRL_2_string;
reg [23:0] _zz_decode_SRC2_CTRL_2_string;
reg [63:0] _zz_decode_ALU_CTRL_2_string;
reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string;
reg [71:0] _zz_decode_SHIFT_CTRL_2_string;
reg [31:0] _zz_decode_BRANCH_CTRL_2_string;
reg [63:0] decode_to_execute_ALU_CTRL_string;
reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string;
reg [71:0] decode_to_execute_SHIFT_CTRL_string;
reg [71:0] execute_to_memory_SHIFT_CTRL_string;
reg [31:0] decode_to_execute_BRANCH_CTRL_string;
`endif
(* no_rw_check *)
reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ;
assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5));
assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3));
assign _zz_memory_MUL_LOW_2 = 52'h0;
assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL};
assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4};
assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16);
assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6};
assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16);
assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8};
assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude);
assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0];
assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == ShiftCtrlEnum_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed};
assign _zz_IBusSimplePlugin_jump_pcLoad_payload_1 = (_zz_IBusSimplePlugin_jump_pcLoad_payload & (~ _zz_IBusSimplePlugin_jump_pcLoad_payload_2));
assign _zz_IBusSimplePlugin_jump_pcLoad_payload_2 = (_zz_IBusSimplePlugin_jump_pcLoad_payload - 2'b01);
assign _zz_IBusSimplePlugin_fetchPc_pc_1 = {IBusSimplePlugin_fetchPc_inc,2'b00};
assign _zz_IBusSimplePlugin_fetchPc_pc = {29'd0, _zz_IBusSimplePlugin_fetchPc_pc_1};
assign _zz__zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
assign _zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch_2 = {{_zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch_1,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0};
assign _zz__zz_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]};
assign _zz__zz_4 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
assign _zz__zz_6 = {{_zz_3,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0};
assign _zz__zz_6_1 = {{_zz_5,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0};
assign _zz__zz_IBusSimplePlugin_predictionJumpInterface_payload = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]};
assign _zz__zz_IBusSimplePlugin_predictionJumpInterface_payload_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
assign _zz_IBusSimplePlugin_pending_next = (IBusSimplePlugin_pending_value + _zz_IBusSimplePlugin_pending_next_1);
assign _zz_IBusSimplePlugin_pending_next_2 = IBusSimplePlugin_pending_inc;
assign _zz_IBusSimplePlugin_pending_next_1 = {2'd0, _zz_IBusSimplePlugin_pending_next_2};
assign _zz_IBusSimplePlugin_pending_next_4 = IBusSimplePlugin_pending_dec;
assign _zz_IBusSimplePlugin_pending_next_3 = {2'd0, _zz_IBusSimplePlugin_pending_next_4};
assign _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_1 = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != 3'b000));
assign _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter = {2'd0, _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_1};
assign _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_3 = IBusSimplePlugin_pending_dec;
assign _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_2 = {2'd0, _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_3};
assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS;
assign _zz__zz_decode_SRC1 = 3'b100;
assign _zz__zz_decode_SRC1_1 = decode_INSTRUCTION[19 : 15];
assign _zz__zz_decode_SRC2_2 = {decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]};
assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4));
assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3));
assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1;
assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2);
assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6);
assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001;
assign _zz_execute_SrcPlugin_addSub_6 = 32'h0;
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6 = {_zz_execute_BranchPlugin_missAlignedTarget_1,execute_INSTRUCTION[31 : 20]};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1 = {{_zz_execute_BranchPlugin_missAlignedTarget_3,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2 = {{_zz_execute_BranchPlugin_missAlignedTarget_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0};
assign _zz__zz_execute_BranchPlugin_branch_src2_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
assign _zz_execute_BranchPlugin_branch_src2_9 = 3'b100;
assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW};
assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32);
assign _zz__zz_decode_RS2_2 = writeBack_MUL_LOW[31 : 0];
assign _zz__zz_decode_RS2_2_1 = writeBack_MulPlugin_result[63 : 32];
assign _zz_decode_RegFilePlugin_rs1Data = 1'b1;
assign _zz_decode_RegFilePlugin_rs2Data = 1'b1;
assign _zz_IBusSimplePlugin_predictionJumpInterface_payload_4 = decode_INSTRUCTION[31];
assign _zz_IBusSimplePlugin_predictionJumpInterface_payload_5 = decode_INSTRUCTION[31];
assign _zz_IBusSimplePlugin_predictionJumpInterface_payload_6 = decode_INSTRUCTION[7];
assign _zz__zz_decode_IS_MUL = (decode_INSTRUCTION & 32'h0000001c);
assign _zz__zz_decode_IS_MUL_1 = 32'h00000004;
assign _zz__zz_decode_IS_MUL_2 = (decode_INSTRUCTION & 32'h00000048);
assign _zz__zz_decode_IS_MUL_3 = 32'h00000040;
assign _zz__zz_decode_IS_MUL_4 = ((decode_INSTRUCTION & 32'h00007014) == 32'h00005010);
assign _zz__zz_decode_IS_MUL_5 = {((decode_INSTRUCTION & _zz__zz_decode_IS_MUL_6) == 32'h40001010),((decode_INSTRUCTION & _zz__zz_decode_IS_MUL_7) == 32'h00001010)};
assign _zz__zz_decode_IS_MUL_8 = (|((decode_INSTRUCTION & _zz__zz_decode_IS_MUL_9) == 32'h00000024));
assign _zz__zz_decode_IS_MUL_10 = (|(_zz__zz_decode_IS_MUL_11 == _zz__zz_decode_IS_MUL_12));
assign _zz__zz_decode_IS_MUL_13 = {(|_zz__zz_decode_IS_MUL_14),{(|_zz__zz_decode_IS_MUL_15),{_zz__zz_decode_IS_MUL_18,{_zz__zz_decode_IS_MUL_20,_zz__zz_decode_IS_MUL_23}}}};
assign _zz__zz_decode_IS_MUL_6 = 32'h40003014;
assign _zz__zz_decode_IS_MUL_7 = 32'h02007014;
assign _zz__zz_decode_IS_MUL_9 = 32'h00000064;
assign _zz__zz_decode_IS_MUL_11 = (decode_INSTRUCTION & 32'h00001000);
assign _zz__zz_decode_IS_MUL_12 = 32'h00001000;
assign _zz__zz_decode_IS_MUL_14 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000);
assign _zz__zz_decode_IS_MUL_15 = {((decode_INSTRUCTION & _zz__zz_decode_IS_MUL_16) == 32'h00002000),((decode_INSTRUCTION & _zz__zz_decode_IS_MUL_17) == 32'h00001000)};
assign _zz__zz_decode_IS_MUL_18 = (|((decode_INSTRUCTION & _zz__zz_decode_IS_MUL_19) == 32'h00004000));
assign _zz__zz_decode_IS_MUL_20 = (|(_zz__zz_decode_IS_MUL_21 == _zz__zz_decode_IS_MUL_22));
assign _zz__zz_decode_IS_MUL_23 = {(|_zz__zz_decode_IS_MUL_24),{(|_zz__zz_decode_IS_MUL_25),{_zz__zz_decode_IS_MUL_27,{_zz__zz_decode_IS_MUL_29,_zz__zz_decode_IS_MUL_34}}}};
assign _zz__zz_decode_IS_MUL_16 = 32'h00002010;
assign _zz__zz_decode_IS_MUL_17 = 32'h00005000;
assign _zz__zz_decode_IS_MUL_19 = 32'h00004004;
assign _zz__zz_decode_IS_MUL_21 = (decode_INSTRUCTION & 32'h00006004);
assign _zz__zz_decode_IS_MUL_22 = 32'h00002000;
assign _zz__zz_decode_IS_MUL_24 = ((decode_INSTRUCTION & 32'h00000024) == 32'h00000020);
assign _zz__zz_decode_IS_MUL_25 = {((decode_INSTRUCTION & _zz__zz_decode_IS_MUL_26) == 32'h00000040),_zz_decode_IS_MUL_1};
assign _zz__zz_decode_IS_MUL_27 = (|((decode_INSTRUCTION & _zz__zz_decode_IS_MUL_28) == 32'h00000020));
assign _zz__zz_decode_IS_MUL_29 = (|{_zz_decode_IS_MUL_2,{_zz__zz_decode_IS_MUL_30,_zz__zz_decode_IS_MUL_32}});
assign _zz__zz_decode_IS_MUL_34 = {(|{_zz__zz_decode_IS_MUL_35,_zz__zz_decode_IS_MUL_36}),{(|_zz__zz_decode_IS_MUL_47),{_zz__zz_decode_IS_MUL_56,{_zz__zz_decode_IS_MUL_59,_zz__zz_decode_IS_MUL_64}}}};
assign _zz__zz_decode_IS_MUL_26 = 32'h00000040;
assign _zz__zz_decode_IS_MUL_28 = 32'h00000020;
assign _zz__zz_decode_IS_MUL_30 = ((decode_INSTRUCTION & _zz__zz_decode_IS_MUL_31) == 32'h00000010);
assign _zz__zz_decode_IS_MUL_32 = ((decode_INSTRUCTION & _zz__zz_decode_IS_MUL_33) == 32'h00000020);
assign _zz__zz_decode_IS_MUL_35 = _zz_decode_IS_MUL_2;
assign _zz__zz_decode_IS_MUL_36 = {(_zz__zz_decode_IS_MUL_37 == _zz__zz_decode_IS_MUL_38),{_zz__zz_decode_IS_MUL_39,{_zz__zz_decode_IS_MUL_41,_zz__zz_decode_IS_MUL_44}}};
assign _zz__zz_decode_IS_MUL_47 = {(_zz__zz_decode_IS_MUL_48 == _zz__zz_decode_IS_MUL_49),{_zz_decode_IS_MUL_3,{_zz__zz_decode_IS_MUL_50,_zz__zz_decode_IS_MUL_53}}};
assign _zz__zz_decode_IS_MUL_56 = (|{_zz_decode_IS_MUL_2,_zz__zz_decode_IS_MUL_57});
assign _zz__zz_decode_IS_MUL_59 = (|{_zz__zz_decode_IS_MUL_60,_zz__zz_decode_IS_MUL_61});
assign _zz__zz_decode_IS_MUL_64 = {(|_zz__zz_decode_IS_MUL_65),{_zz__zz_decode_IS_MUL_67,{_zz__zz_decode_IS_MUL_69,_zz__zz_decode_IS_MUL_76}}};
assign _zz__zz_decode_IS_MUL_31 = 32'h00000030;
assign _zz__zz_decode_IS_MUL_33 = 32'h02000020;
assign _zz__zz_decode_IS_MUL_37 = (decode_INSTRUCTION & 32'h00002030);
assign _zz__zz_decode_IS_MUL_38 = 32'h00002010;
assign _zz__zz_decode_IS_MUL_39 = ((decode_INSTRUCTION & _zz__zz_decode_IS_MUL_40) == 32'h00002020);
assign _zz__zz_decode_IS_MUL_41 = (_zz__zz_decode_IS_MUL_42 == _zz__zz_decode_IS_MUL_43);
assign _zz__zz_decode_IS_MUL_44 = (_zz__zz_decode_IS_MUL_45 == _zz__zz_decode_IS_MUL_46);
assign _zz__zz_decode_IS_MUL_48 = (decode_INSTRUCTION & 32'h00000010);
assign _zz__zz_decode_IS_MUL_49 = 32'h00000010;
assign _zz__zz_decode_IS_MUL_50 = (_zz__zz_decode_IS_MUL_51 == _zz__zz_decode_IS_MUL_52);
assign _zz__zz_decode_IS_MUL_53 = (_zz__zz_decode_IS_MUL_54 == _zz__zz_decode_IS_MUL_55);
assign _zz__zz_decode_IS_MUL_57 = ((decode_INSTRUCTION & _zz__zz_decode_IS_MUL_58) == 32'h00000020);
assign _zz__zz_decode_IS_MUL_60 = _zz_decode_IS_MUL_2;
assign _zz__zz_decode_IS_MUL_61 = (_zz__zz_decode_IS_MUL_62 == _zz__zz_decode_IS_MUL_63);
assign _zz__zz_decode_IS_MUL_65 = {_zz__zz_decode_IS_MUL_66,_zz_decode_IS_MUL_1};
assign _zz__zz_decode_IS_MUL_67 = (|_zz__zz_decode_IS_MUL_68);
assign _zz__zz_decode_IS_MUL_69 = (|_zz__zz_decode_IS_MUL_70);
assign _zz__zz_decode_IS_MUL_76 = {_zz__zz_decode_IS_MUL_77,_zz__zz_decode_IS_MUL_79};
assign _zz__zz_decode_IS_MUL_40 = 32'h02002020;
assign _zz__zz_decode_IS_MUL_42 = (decode_INSTRUCTION & 32'h02001020);
assign _zz__zz_decode_IS_MUL_43 = 32'h00000020;
assign _zz__zz_decode_IS_MUL_45 = (decode_INSTRUCTION & 32'h00001030);
assign _zz__zz_decode_IS_MUL_46 = 32'h00000010;
assign _zz__zz_decode_IS_MUL_51 = (decode_INSTRUCTION & 32'h0000000c);
assign _zz__zz_decode_IS_MUL_52 = 32'h00000004;
assign _zz__zz_decode_IS_MUL_54 = (decode_INSTRUCTION & 32'h00000028);
assign _zz__zz_decode_IS_MUL_55 = 32'h0;
assign _zz__zz_decode_IS_MUL_58 = 32'h00000070;
assign _zz__zz_decode_IS_MUL_62 = (decode_INSTRUCTION & 32'h00000020);
assign _zz__zz_decode_IS_MUL_63 = 32'h0;
assign _zz__zz_decode_IS_MUL_66 = ((decode_INSTRUCTION & 32'h00000004) == 32'h0);
assign _zz__zz_decode_IS_MUL_68 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0);
assign _zz__zz_decode_IS_MUL_70 = {((decode_INSTRUCTION & _zz__zz_decode_IS_MUL_71) == 32'h00000040),{(_zz__zz_decode_IS_MUL_72 == _zz__zz_decode_IS_MUL_73),(_zz__zz_decode_IS_MUL_74 == _zz__zz_decode_IS_MUL_75)}};
assign _zz__zz_decode_IS_MUL_77 = (|((decode_INSTRUCTION & _zz__zz_decode_IS_MUL_78) == 32'h00000004));
assign _zz__zz_decode_IS_MUL_79 = (|((decode_INSTRUCTION & _zz__zz_decode_IS_MUL_80) == 32'h00000004));
assign _zz__zz_decode_IS_MUL_71 = 32'h00000044;
assign _zz__zz_decode_IS_MUL_72 = (decode_INSTRUCTION & 32'h00002014);
assign _zz__zz_decode_IS_MUL_73 = 32'h00002010;
assign _zz__zz_decode_IS_MUL_74 = (decode_INSTRUCTION & 32'h40000034);
assign _zz__zz_decode_IS_MUL_75 = 32'h40000030;
assign _zz__zz_decode_IS_MUL_78 = 32'h00000014;
assign _zz__zz_decode_IS_MUL_80 = 32'h00000044;
assign _zz_execute_BranchPlugin_branch_src2_6 = execute_INSTRUCTION[31];
assign _zz_execute_BranchPlugin_branch_src2_7 = execute_INSTRUCTION[31];
assign _zz_execute_BranchPlugin_branch_src2_8 = execute_INSTRUCTION[7];
always @(posedge clk) begin
if(_zz_decode_RegFilePlugin_rs1Data) begin
_zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1];
end
end
always @(posedge clk) begin
if(_zz_decode_RegFilePlugin_rs2Data) begin
_zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2];
end
end
always @(posedge clk) begin
if(_zz_1) begin
RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data;
end
end
StreamFifoLowLatency IBusSimplePlugin_rspJoin_rspBuffer_c (
.io_push_valid (iBus_rsp_toStream_valid ), //i
.io_push_ready (IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready ), //o
.io_push_payload_error (iBus_rsp_toStream_payload_error ), //i
.io_push_payload_inst (iBus_rsp_toStream_payload_inst[31:0] ), //i
.io_pop_valid (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid ), //o
.io_pop_ready (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_ready ), //i
.io_pop_payload_error (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error ), //o
.io_pop_payload_inst (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst[31:0]), //o
.io_flush (1'b0 ), //i
.io_occupancy (IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy ), //o
.clk (clk ), //i
.reset (reset ) //i
);
`ifndef SYNTHESIS
always @(*) begin
case(_zz_decode_to_execute_BRANCH_CTRL)
BranchCtrlEnum_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC ";
BranchCtrlEnum_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B ";
BranchCtrlEnum_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL ";
BranchCtrlEnum_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR";
default : _zz_decode_to_execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_BRANCH_CTRL_1)
BranchCtrlEnum_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC ";
BranchCtrlEnum_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B ";
BranchCtrlEnum_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL ";
BranchCtrlEnum_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR";
default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_SHIFT_CTRL)
ShiftCtrlEnum_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1";
ShiftCtrlEnum_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 ";
ShiftCtrlEnum_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 ";
ShiftCtrlEnum_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_SHIFT_CTRL_1)
ShiftCtrlEnum_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1";
ShiftCtrlEnum_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 ";
ShiftCtrlEnum_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 ";
ShiftCtrlEnum_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 ";
default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????";
endcase
end
always @(*) begin
case(decode_SHIFT_CTRL)
ShiftCtrlEnum_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1";
ShiftCtrlEnum_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 ";
ShiftCtrlEnum_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 ";
ShiftCtrlEnum_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 ";
default : decode_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_SHIFT_CTRL)
ShiftCtrlEnum_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1";
ShiftCtrlEnum_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 ";
ShiftCtrlEnum_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 ";
ShiftCtrlEnum_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_decode_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SHIFT_CTRL)
ShiftCtrlEnum_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1";
ShiftCtrlEnum_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 ";
ShiftCtrlEnum_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 ";
ShiftCtrlEnum_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SHIFT_CTRL_1)
ShiftCtrlEnum_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1";
ShiftCtrlEnum_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 ";
ShiftCtrlEnum_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 ";
ShiftCtrlEnum_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 ";
default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????";
endcase
end
always @(*) begin
case(decode_ALU_BITWISE_CTRL)
AluBitwiseCtrlEnum_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1";
AluBitwiseCtrlEnum_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 ";
AluBitwiseCtrlEnum_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1";
default : decode_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_BITWISE_CTRL)
AluBitwiseCtrlEnum_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1";
AluBitwiseCtrlEnum_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 ";
AluBitwiseCtrlEnum_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1";
default : _zz_decode_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_BITWISE_CTRL)
AluBitwiseCtrlEnum_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1";
AluBitwiseCtrlEnum_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
AluBitwiseCtrlEnum_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1";
default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1)
AluBitwiseCtrlEnum_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1";
AluBitwiseCtrlEnum_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 ";
AluBitwiseCtrlEnum_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1";
default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(decode_ALU_CTRL)
AluCtrlEnum_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB ";
AluCtrlEnum_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU";
AluCtrlEnum_BITWISE : decode_ALU_CTRL_string = "BITWISE ";
default : decode_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_CTRL)
AluCtrlEnum_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB ";
AluCtrlEnum_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU";
AluCtrlEnum_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE ";
default : _zz_decode_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_CTRL)
AluCtrlEnum_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB ";
AluCtrlEnum_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU";
AluCtrlEnum_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE ";
default : _zz_decode_to_execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_CTRL_1)
AluCtrlEnum_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB ";
AluCtrlEnum_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU";
AluCtrlEnum_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE ";
default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????";
endcase
end
always @(*) begin
case(execute_BRANCH_CTRL)
BranchCtrlEnum_INC : execute_BRANCH_CTRL_string = "INC ";
BranchCtrlEnum_B : execute_BRANCH_CTRL_string = "B ";
BranchCtrlEnum_JAL : execute_BRANCH_CTRL_string = "JAL ";
BranchCtrlEnum_JALR : execute_BRANCH_CTRL_string = "JALR";
default : execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_execute_BRANCH_CTRL)
BranchCtrlEnum_INC : _zz_execute_BRANCH_CTRL_string = "INC ";
BranchCtrlEnum_B : _zz_execute_BRANCH_CTRL_string = "B ";
BranchCtrlEnum_JAL : _zz_execute_BRANCH_CTRL_string = "JAL ";
BranchCtrlEnum_JALR : _zz_execute_BRANCH_CTRL_string = "JALR";
default : _zz_execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(memory_SHIFT_CTRL)
ShiftCtrlEnum_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1";
ShiftCtrlEnum_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 ";
ShiftCtrlEnum_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 ";
ShiftCtrlEnum_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 ";
default : memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_memory_SHIFT_CTRL)
ShiftCtrlEnum_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1";
ShiftCtrlEnum_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 ";
ShiftCtrlEnum_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 ";
ShiftCtrlEnum_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(execute_SHIFT_CTRL)
ShiftCtrlEnum_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1";
ShiftCtrlEnum_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 ";
ShiftCtrlEnum_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 ";
ShiftCtrlEnum_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 ";
default : execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_execute_SHIFT_CTRL)
ShiftCtrlEnum_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1";
ShiftCtrlEnum_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 ";
ShiftCtrlEnum_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 ";
ShiftCtrlEnum_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(decode_SRC2_CTRL)
Src2CtrlEnum_RS : decode_SRC2_CTRL_string = "RS ";
Src2CtrlEnum_IMI : decode_SRC2_CTRL_string = "IMI";
Src2CtrlEnum_IMS : decode_SRC2_CTRL_string = "IMS";
Src2CtrlEnum_PC : decode_SRC2_CTRL_string = "PC ";
default : decode_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_SRC2_CTRL)
Src2CtrlEnum_RS : _zz_decode_SRC2_CTRL_string = "RS ";
Src2CtrlEnum_IMI : _zz_decode_SRC2_CTRL_string = "IMI";
Src2CtrlEnum_IMS : _zz_decode_SRC2_CTRL_string = "IMS";
Src2CtrlEnum_PC : _zz_decode_SRC2_CTRL_string = "PC ";
default : _zz_decode_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(decode_SRC1_CTRL)
Src1CtrlEnum_RS : decode_SRC1_CTRL_string = "RS ";
Src1CtrlEnum_IMU : decode_SRC1_CTRL_string = "IMU ";
Src1CtrlEnum_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT";
Src1CtrlEnum_URS1 : decode_SRC1_CTRL_string = "URS1 ";
default : decode_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_SRC1_CTRL)
Src1CtrlEnum_RS : _zz_decode_SRC1_CTRL_string = "RS ";
Src1CtrlEnum_IMU : _zz_decode_SRC1_CTRL_string = "IMU ";
Src1CtrlEnum_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT";
Src1CtrlEnum_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 ";
default : _zz_decode_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(execute_ALU_CTRL)
AluCtrlEnum_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB ";
AluCtrlEnum_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU";
AluCtrlEnum_BITWISE : execute_ALU_CTRL_string = "BITWISE ";
default : execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_execute_ALU_CTRL)
AluCtrlEnum_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB ";
AluCtrlEnum_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU";
AluCtrlEnum_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE ";
default : _zz_execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(execute_ALU_BITWISE_CTRL)
AluBitwiseCtrlEnum_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1";
AluBitwiseCtrlEnum_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 ";
AluBitwiseCtrlEnum_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1";
default : execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_ALU_BITWISE_CTRL)
AluBitwiseCtrlEnum_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1";
AluBitwiseCtrlEnum_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
AluBitwiseCtrlEnum_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1";
default : _zz_execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_BRANCH_CTRL)
BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_string = "INC ";
BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_string = "B ";
BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_string = "JAL ";
BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_string = "JALR";
default : _zz_decode_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_SHIFT_CTRL_1)
ShiftCtrlEnum_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1";
ShiftCtrlEnum_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 ";
ShiftCtrlEnum_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 ";
ShiftCtrlEnum_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 ";
default : _zz_decode_SHIFT_CTRL_1_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_BITWISE_CTRL_1)
AluBitwiseCtrlEnum_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1";
AluBitwiseCtrlEnum_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 ";
AluBitwiseCtrlEnum_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1";
default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_CTRL_1)
AluCtrlEnum_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB ";
AluCtrlEnum_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU";
AluCtrlEnum_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE ";
default : _zz_decode_ALU_CTRL_1_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_SRC2_CTRL_1)
Src2CtrlEnum_RS : _zz_decode_SRC2_CTRL_1_string = "RS ";
Src2CtrlEnum_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI";
Src2CtrlEnum_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS";
Src2CtrlEnum_PC : _zz_decode_SRC2_CTRL_1_string = "PC ";
default : _zz_decode_SRC2_CTRL_1_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_SRC1_CTRL_1)
Src1CtrlEnum_RS : _zz_decode_SRC1_CTRL_1_string = "RS ";
Src1CtrlEnum_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU ";
Src1CtrlEnum_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT";
Src1CtrlEnum_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 ";
default : _zz_decode_SRC1_CTRL_1_string = "????????????";
endcase
end
always @(*) begin
case(decode_BRANCH_CTRL)
BranchCtrlEnum_INC : decode_BRANCH_CTRL_string = "INC ";
BranchCtrlEnum_B : decode_BRANCH_CTRL_string = "B ";
BranchCtrlEnum_JAL : decode_BRANCH_CTRL_string = "JAL ";
BranchCtrlEnum_JALR : decode_BRANCH_CTRL_string = "JALR";
default : decode_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_BRANCH_CTRL_1)
BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_1_string = "INC ";
BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_1_string = "B ";
BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL ";
BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR";
default : _zz_decode_BRANCH_CTRL_1_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_SRC1_CTRL_2)
Src1CtrlEnum_RS : _zz_decode_SRC1_CTRL_2_string = "RS ";
Src1CtrlEnum_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU ";
Src1CtrlEnum_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT";
Src1CtrlEnum_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 ";
default : _zz_decode_SRC1_CTRL_2_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_SRC2_CTRL_2)
Src2CtrlEnum_RS : _zz_decode_SRC2_CTRL_2_string = "RS ";
Src2CtrlEnum_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI";
Src2CtrlEnum_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS";
Src2CtrlEnum_PC : _zz_decode_SRC2_CTRL_2_string = "PC ";
default : _zz_decode_SRC2_CTRL_2_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_ALU_CTRL_2)
AluCtrlEnum_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB ";
AluCtrlEnum_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU";
AluCtrlEnum_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE ";
default : _zz_decode_ALU_CTRL_2_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_BITWISE_CTRL_2)
AluBitwiseCtrlEnum_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1";
AluBitwiseCtrlEnum_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 ";
AluBitwiseCtrlEnum_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1";
default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_SHIFT_CTRL_2)
ShiftCtrlEnum_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1";
ShiftCtrlEnum_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 ";
ShiftCtrlEnum_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 ";
ShiftCtrlEnum_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 ";
default : _zz_decode_SHIFT_CTRL_2_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_BRANCH_CTRL_2)
BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_2_string = "INC ";
BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_2_string = "B ";
BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_2_string = "JAL ";
BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_2_string = "JALR";
default : _zz_decode_BRANCH_CTRL_2_string = "????";
endcase
end
always @(*) begin
case(decode_to_execute_ALU_CTRL)
AluCtrlEnum_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB ";
AluCtrlEnum_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU";
AluCtrlEnum_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE ";
default : decode_to_execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(decode_to_execute_ALU_BITWISE_CTRL)
AluBitwiseCtrlEnum_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1";
AluBitwiseCtrlEnum_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
AluBitwiseCtrlEnum_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1";
default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(decode_to_execute_SHIFT_CTRL)
ShiftCtrlEnum_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1";
ShiftCtrlEnum_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 ";
ShiftCtrlEnum_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 ";
ShiftCtrlEnum_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 ";
default : decode_to_execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(execute_to_memory_SHIFT_CTRL)
ShiftCtrlEnum_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1";
ShiftCtrlEnum_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 ";
ShiftCtrlEnum_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 ";
ShiftCtrlEnum_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 ";
default : execute_to_memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(decode_to_execute_BRANCH_CTRL)
BranchCtrlEnum_INC : decode_to_execute_BRANCH_CTRL_string = "INC ";
BranchCtrlEnum_B : decode_to_execute_BRANCH_CTRL_string = "B ";
BranchCtrlEnum_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL ";
BranchCtrlEnum_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR";
default : decode_to_execute_BRANCH_CTRL_string = "????";
endcase
end
`endif
assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7)); // @[Stage.scala 30:13]
assign memory_MEMORY_READ_DATA = dBus_rsp_data; // @[Stage.scala 30:13]
assign memory_MUL_HH = execute_to_memory_MUL_HH; // @[Stage.scala 30:13]
assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); // @[Stage.scala 30:13]
assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); // @[Stage.scala 30:13]
assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); // @[Stage.scala 30:13]
assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); // @[Stage.scala 30:13]
assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; // @[Stage.scala 30:13]
assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); // @[Stage.scala 30:13]
assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT; // @[Stage.scala 30:13]
assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; // @[Stage.scala 30:13]
assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; // @[Stage.scala 30:13]
assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA; // @[Stage.scala 30:13]
assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; // @[Stage.scala 30:13]
assign execute_MEMORY_ADDRESS_LOW = dBus_cmd_payload_address[1 : 0]; // @[Stage.scala 30:13]
assign decode_PREDICTION_HAD_BRANCHED2 = IBusSimplePlugin_decodePrediction_cmd_hadBranch; // @[Stage.scala 30:13]
assign decode_SRC2 = _zz_decode_SRC2_4; // @[Stage.scala 30:13]
assign decode_SRC1 = _zz_decode_SRC1; // @[Stage.scala 30:13]
assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); // @[Stage.scala 30:13]
assign memory_IS_MUL = execute_to_memory_IS_MUL; // @[Stage.scala 30:13]
assign execute_IS_MUL = decode_to_execute_IS_MUL; // @[Stage.scala 30:13]
assign decode_IS_MUL = _zz_decode_IS_MUL[23]; // @[Stage.scala 30:13]
assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1; // @[Stage.scala 39:14]
assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1; // @[Stage.scala 39:14]
assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL; // @[Stage.scala 30:13]
assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1; // @[Stage.scala 39:14]
assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL; // @[Stage.scala 30:13]
assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1; // @[Stage.scala 39:14]
assign decode_SRC_LESS_UNSIGNED = _zz_decode_IS_MUL[15]; // @[Stage.scala 30:13]
assign decode_ALU_CTRL = _zz_decode_ALU_CTRL; // @[Stage.scala 30:13]
assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1; // @[Stage.scala 39:14]
assign decode_MEMORY_STORE = _zz_decode_IS_MUL[10]; // @[Stage.scala 30:13]
assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; // @[Stage.scala 30:13]
assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_IS_MUL[9]; // @[Stage.scala 30:13]
assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_IS_MUL[8]; // @[Stage.scala 30:13]
assign decode_MEMORY_ENABLE = _zz_decode_IS_MUL[3]; // @[Stage.scala 30:13]
assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; // @[Stage.scala 30:13]
assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; // @[Stage.scala 30:13]
assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); // @[Stage.scala 30:13]
assign memory_PC = execute_to_memory_PC; // @[Stage.scala 30:13]
assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL; // @[Stage.scala 30:13]
assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH; // @[Stage.scala 30:13]
assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW; // @[Stage.scala 30:13]
assign memory_MUL_HL = execute_to_memory_MUL_HL; // @[Stage.scala 30:13]
assign memory_MUL_LH = execute_to_memory_MUL_LH; // @[Stage.scala 30:13]
assign memory_MUL_LL = execute_to_memory_MUL_LL; // @[Stage.scala 30:13]
assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; // @[Stage.scala 30:13]
assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; // @[Stage.scala 30:13]
assign execute_PC = decode_to_execute_PC; // @[Stage.scala 30:13]
assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; // @[Stage.scala 30:13]
assign execute_RS1 = decode_to_execute_RS1; // @[Stage.scala 30:13]
assign execute_BRANCH_COND_RESULT = _zz_execute_BRANCH_COND_RESULT_1; // @[Stage.scala 30:13]
assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL; // @[Stage.scala 30:13]
assign decode_RS2_USE = _zz_decode_IS_MUL[12]; // @[Stage.scala 30:13]
assign decode_RS1_USE = _zz_decode_IS_MUL[4]; // @[Stage.scala 30:13]
assign _zz_decode_RS2 = execute_REGFILE_WRITE_DATA; // @[Stage.scala 39:14]
assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; // @[Stage.scala 30:13]
assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; // @[Stage.scala 30:13]
assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; // @[Stage.scala 30:13]
assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; // @[Stage.scala 30:13]
assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; // @[Stage.scala 30:13]
assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; // @[Stage.scala 30:13]
always @(*) begin
decode_RS2 = decode_RegFilePlugin_rs2Data; // @[Stage.scala 30:13]
if(HazardSimplePlugin_writeBackBuffer_valid) begin
if(HazardSimplePlugin_addr1Match) begin
decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; // @[HazardSimplePlugin.scala 87:34]
end
end
if(when_HazardSimplePlugin_l45) begin
if(when_HazardSimplePlugin_l47) begin
if(when_HazardSimplePlugin_l51) begin
decode_RS2 = _zz_decode_RS2_2; // @[HazardSimplePlugin.scala 52:38]
end
end
end
if(when_HazardSimplePlugin_l45_1) begin
if(memory_BYPASSABLE_MEMORY_STAGE) begin
if(when_HazardSimplePlugin_l51_1) begin
decode_RS2 = _zz_decode_RS2_1; // @[HazardSimplePlugin.scala 52:38]
end
end
end
if(when_HazardSimplePlugin_l45_2) begin
if(execute_BYPASSABLE_EXECUTE_STAGE) begin
if(when_HazardSimplePlugin_l51_2) begin
decode_RS2 = _zz_decode_RS2; // @[HazardSimplePlugin.scala 52:38]
end
end
end
end
always @(*) begin
decode_RS1 = decode_RegFilePlugin_rs1Data; // @[Stage.scala 30:13]
if(HazardSimplePlugin_writeBackBuffer_valid) begin
if(HazardSimplePlugin_addr0Match) begin
decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; // @[HazardSimplePlugin.scala 84:34]
end
end
if(when_HazardSimplePlugin_l45) begin
if(when_HazardSimplePlugin_l47) begin
if(when_HazardSimplePlugin_l48) begin
decode_RS1 = _zz_decode_RS2_2; // @[HazardSimplePlugin.scala 49:38]
end
end
end
if(when_HazardSimplePlugin_l45_1) begin
if(memory_BYPASSABLE_MEMORY_STAGE) begin
if(when_HazardSimplePlugin_l48_1) begin
decode_RS1 = _zz_decode_RS2_1; // @[HazardSimplePlugin.scala 49:38]
end
end
end
if(when_HazardSimplePlugin_l45_2) begin
if(execute_BYPASSABLE_EXECUTE_STAGE) begin
if(when_HazardSimplePlugin_l48_2) begin
decode_RS1 = _zz_decode_RS2; // @[HazardSimplePlugin.scala 49:38]
end
end
end
end
assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; // @[Stage.scala 30:13]
always @(*) begin
_zz_decode_RS2_1 = memory_REGFILE_WRITE_DATA; // @[Stage.scala 39:14]
if(memory_arbitration_isValid) begin
case(memory_SHIFT_CTRL)
ShiftCtrlEnum_SLL_1 : begin
_zz_decode_RS2_1 = _zz_decode_RS2_3; // @[ShiftPlugins.scala 75:40]
end
ShiftCtrlEnum_SRL_1, ShiftCtrlEnum_SRA_1 : begin
_zz_decode_RS2_1 = memory_SHIFT_RIGHT; // @[ShiftPlugins.scala 78:40]
end
default : begin
end
endcase
end
end
assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL; // @[Stage.scala 30:13]
assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL; // @[Stage.scala 30:13]
assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; // @[Stage.scala 30:13]
assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; // @[Stage.scala 30:13]
assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; // @[Stage.scala 30:13]
assign _zz_decode_to_execute_PC = decode_PC; // @[Stage.scala 39:14]
assign _zz_decode_to_execute_RS2 = decode_RS2; // @[Stage.scala 39:14]
assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL; // @[Stage.scala 30:13]
assign _zz_decode_to_execute_RS1 = decode_RS1; // @[Stage.scala 39:14]
assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL; // @[Stage.scala 30:13]
assign decode_SRC_USE_SUB_LESS = _zz_decode_IS_MUL[2]; // @[Stage.scala 30:13]
assign decode_SRC_ADD_ZERO = _zz_decode_IS_MUL[18]; // @[Stage.scala 30:13]
assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; // @[Stage.scala 30:13]
assign execute_SRC_LESS = execute_SrcPlugin_less; // @[Stage.scala 30:13]
assign execute_ALU_CTRL = _zz_execute_ALU_CTRL; // @[Stage.scala 30:13]
assign execute_SRC2 = decode_to_execute_SRC2; // @[Stage.scala 30:13]
assign execute_SRC1 = decode_to_execute_SRC1; // @[Stage.scala 30:13]
assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL; // @[Stage.scala 30:13]
assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION; // @[Stage.scala 39:14]
assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID; // @[Stage.scala 39:14]
always @(*) begin
_zz_1 = 1'b0; // @[when.scala 47:16]
if(lastStageRegFileWrite_valid) begin
_zz_1 = 1'b1; // @[when.scala 52:10]
end
end
assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusSimplePlugin_iBusRsp_output_payload_rsp_inst); // @[Stage.scala 30:13]
always @(*) begin
decode_REGFILE_WRITE_VALID = _zz_decode_IS_MUL[7]; // @[Stage.scala 30:13]
if(when_RegFilePlugin_l63) begin
decode_REGFILE_WRITE_VALID = 1'b0; // @[RegFilePlugin.scala 64:41]
end
end
always @(*) begin
_zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA; // @[Stage.scala 39:14]
if(when_DBusSimplePlugin_l558) begin
_zz_decode_RS2_2 = writeBack_DBusSimplePlugin_rspFormated; // @[DBusSimplePlugin.scala 559:36]
end
if(when_MulPlugin_l147) begin
case(switch_MulPlugin_l148)
2'b00 : begin
_zz_decode_RS2_2 = _zz__zz_decode_RS2_2; // @[MulPlugin.scala 150:40]
end
default : begin
_zz_decode_RS2_2 = _zz__zz_decode_RS2_2_1; // @[MulPlugin.scala 153:40]
end
endcase
end
end
assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; // @[Stage.scala 30:13]
assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; // @[Stage.scala 30:13]
assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA; // @[Stage.scala 30:13]
assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE; // @[Stage.scala 30:13]
assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; // @[Stage.scala 30:13]
assign execute_SRC_ADD = execute_SrcPlugin_addSub; // @[Stage.scala 30:13]
assign execute_RS2 = decode_to_execute_RS2; // @[Stage.scala 30:13]
assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; // @[Stage.scala 30:13]
assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; // @[Stage.scala 30:13]
assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; // @[Stage.scala 30:13]
assign execute_ALIGNEMENT_FAULT = 1'b0; // @[Stage.scala 30:13]
assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1; // @[Stage.scala 30:13]
always @(*) begin
_zz_decode_to_execute_FORMAL_PC_NEXT = decode_FORMAL_PC_NEXT; // @[Stage.scala 39:14]
if(IBusSimplePlugin_predictionJumpInterface_valid) begin
_zz_decode_to_execute_FORMAL_PC_NEXT = IBusSimplePlugin_predictionJumpInterface_payload; // @[Fetcher.scala 439:47]
end
end
assign decode_PC = IBusSimplePlugin_injector_decodeInput_payload_pc; // @[Stage.scala 30:13]
assign decode_INSTRUCTION = IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; // @[Stage.scala 30:13]
assign writeBack_PC = memory_to_writeBack_PC; // @[Stage.scala 30:13]
assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; // @[Stage.scala 30:13]
assign decode_arbitration_haltItself = 1'b0; // @[Stage.scala 49:23]
always @(*) begin
decode_arbitration_haltByOther = 1'b0; // @[Stage.scala 50:23]
if(when_HazardSimplePlugin_l113) begin
decode_arbitration_haltByOther = 1'b1; // @[HazardSimplePlugin.scala 114:43]
end
end
always @(*) begin
decode_arbitration_removeIt = 1'b0; // @[Stage.scala 51:23]
if(decode_arbitration_isFlushed) begin
decode_arbitration_removeIt = 1'b1; // @[Pipeline.scala 134:36]
end
end
assign decode_arbitration_flushIt = 1'b0; // @[Stage.scala 52:22]
always @(*) begin
decode_arbitration_flushNext = 1'b0; // @[Stage.scala 53:24]
if(IBusSimplePlugin_predictionJumpInterface_valid) begin
decode_arbitration_flushNext = 1'b1; // @[Fetcher.scala 522:38]
end
end
always @(*) begin
execute_arbitration_haltItself = 1'b0; // @[Stage.scala 49:23]
if(when_DBusSimplePlugin_l428) begin
execute_arbitration_haltItself = 1'b1; // @[DBusSimplePlugin.scala 429:32]
end
end
assign execute_arbitration_haltByOther = 1'b0; // @[Stage.scala 50:23]
always @(*) begin
execute_arbitration_removeIt = 1'b0; // @[Stage.scala 51:23]
if(execute_arbitration_isFlushed) begin
execute_arbitration_removeIt = 1'b1; // @[Pipeline.scala 134:36]
end
end
assign execute_arbitration_flushIt = 1'b0; // @[Stage.scala 52:22]
assign execute_arbitration_flushNext = 1'b0; // @[Stage.scala 53:24]
always @(*) begin
memory_arbitration_haltItself = 1'b0; // @[Stage.scala 49:23]
if(when_DBusSimplePlugin_l482) begin
memory_arbitration_haltItself = 1'b1; // @[DBusSimplePlugin.scala 482:30]
end
end
assign memory_arbitration_haltByOther = 1'b0; // @[Stage.scala 50:23]
always @(*) begin
memory_arbitration_removeIt = 1'b0; // @[Stage.scala 51:23]
if(memory_arbitration_isFlushed) begin
memory_arbitration_removeIt = 1'b1; // @[Pipeline.scala 134:36]
end
end
assign memory_arbitration_flushIt = 1'b0; // @[Stage.scala 52:22]
always @(*) begin
memory_arbitration_flushNext = 1'b0; // @[Stage.scala 53:24]
if(BranchPlugin_jumpInterface_valid) begin
memory_arbitration_flushNext = 1'b1; // @[BranchPlugin.scala 294:29]
end
end
assign writeBack_arbitration_haltItself = 1'b0; // @[Stage.scala 49:23]
assign writeBack_arbitration_haltByOther = 1'b0; // @[Stage.scala 50:23]
always @(*) begin
writeBack_arbitration_removeIt = 1'b0; // @[Stage.scala 51:23]
if(writeBack_arbitration_isFlushed) begin
writeBack_arbitration_removeIt = 1'b1; // @[Pipeline.scala 134:36]
end
end
assign writeBack_arbitration_flushIt = 1'b0; // @[Stage.scala 52:22]
assign writeBack_arbitration_flushNext = 1'b0; // @[Stage.scala 53:24]
assign lastStageInstruction = writeBack_INSTRUCTION; // @[Misc.scala 552:9]
assign lastStagePc = writeBack_PC; // @[Misc.scala 552:9]
assign lastStageIsValid = writeBack_arbitration_isValid; // @[Misc.scala 552:9]
assign lastStageIsFiring = writeBack_arbitration_isFiring; // @[Misc.scala 552:9]
assign IBusSimplePlugin_fetcherHalt = 1'b0; // @[Fetcher.scala 67:19]
assign IBusSimplePlugin_forceNoDecodeCond = 1'b0; // @[Fetcher.scala 68:25]
always @(*) begin
IBusSimplePlugin_incomingInstruction = 1'b0; // @[Fetcher.scala 69:27]
if(IBusSimplePlugin_iBusRsp_stages_1_input_valid) begin
IBusSimplePlugin_incomingInstruction = 1'b1; // @[Fetcher.scala 243:27]
end
if(IBusSimplePlugin_injector_decodeInput_valid) begin
IBusSimplePlugin_incomingInstruction = 1'b1; // @[Fetcher.scala 317:29]
end
end
assign BranchPlugin_inDebugNoFetchFlag = 1'b0; // @[BranchPlugin.scala 155:26]
assign IBusSimplePlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); // @[BaseType.scala 305:24]
assign IBusSimplePlugin_jump_pcLoad_valid = ({BranchPlugin_jumpInterface_valid,IBusSimplePlugin_predictionJumpInterface_valid} != 2'b00); // @[Fetcher.scala 116:20]
assign _zz_IBusSimplePlugin_jump_pcLoad_payload = {IBusSimplePlugin_predictionJumpInterface_valid,BranchPlugin_jumpInterface_valid}; // @[BaseType.scala 318:22]
assign IBusSimplePlugin_jump_pcLoad_payload = (_zz_IBusSimplePlugin_jump_pcLoad_payload_1[0] ? BranchPlugin_jumpInterface_payload : IBusSimplePlugin_predictionJumpInterface_payload); // @[Fetcher.scala 117:22]
always @(*) begin
IBusSimplePlugin_fetchPc_correction = 1'b0; // @[Fetcher.scala 129:24]
if(IBusSimplePlugin_jump_pcLoad_valid) begin
IBusSimplePlugin_fetchPc_correction = 1'b1; // @[Fetcher.scala 156:20]
end
end
assign IBusSimplePlugin_fetchPc_output_fire = (IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready); // @[BaseType.scala 305:24]
assign IBusSimplePlugin_fetchPc_corrected = (IBusSimplePlugin_fetchPc_correction || IBusSimplePlugin_fetchPc_correctionReg); // @[BaseType.scala 305:24]
always @(*) begin
IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b0; // @[Fetcher.scala 132:28]
if(IBusSimplePlugin_iBusRsp_stages_1_input_ready) begin
IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b1; // @[Fetcher.scala 235:34]
end
end
assign when_Fetcher_l134 = (IBusSimplePlugin_fetchPc_correction || IBusSimplePlugin_fetchPc_pcRegPropagate); // @[BaseType.scala 305:24]
assign IBusSimplePlugin_fetchPc_output_fire_1 = (IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready); // @[BaseType.scala 305:24]
assign when_Fetcher_l134_1 = ((! IBusSimplePlugin_fetchPc_output_valid) && IBusSimplePlugin_fetchPc_output_ready); // @[BaseType.scala 305:24]
always @(*) begin
IBusSimplePlugin_fetchPc_pc = (IBusSimplePlugin_fetchPc_pcReg + _zz_IBusSimplePlugin_fetchPc_pc); // @[BaseType.scala 299:24]
if(IBusSimplePlugin_jump_pcLoad_valid) begin
IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_jump_pcLoad_payload; // @[Fetcher.scala 157:12]
end
IBusSimplePlugin_fetchPc_pc[0] = 1'b0; // @[Fetcher.scala 165:13]
IBusSimplePlugin_fetchPc_pc[1] = 1'b0; // @[Fetcher.scala 166:32]
end
always @(*) begin
IBusSimplePlugin_fetchPc_flushed = 1'b0; // @[Fetcher.scala 138:21]
if(IBusSimplePlugin_jump_pcLoad_valid) begin
IBusSimplePlugin_fetchPc_flushed = 1'b1; // @[Fetcher.scala 158:17]
end
end
assign when_Fetcher_l161 = (IBusSimplePlugin_fetchPc_booted && ((IBusSimplePlugin_fetchPc_output_ready || IBusSimplePlugin_fetchPc_correction) || IBusSimplePlugin_fetchPc_pcRegPropagate)); // @[BaseType.scala 305:24]
assign IBusSimplePlugin_fetchPc_output_valid = ((! IBusSimplePlugin_fetcherHalt) && IBusSimplePlugin_fetchPc_booted); // @[Fetcher.scala 168:20]
assign IBusSimplePlugin_fetchPc_output_payload = IBusSimplePlugin_fetchPc_pc; // @[Fetcher.scala 169:22]
assign IBusSimplePlugin_iBusRsp_redoFetch = 1'b0; // @[Fetcher.scala 210:23]
assign IBusSimplePlugin_iBusRsp_stages_0_input_valid = IBusSimplePlugin_fetchPc_output_valid; // @[Stream.scala 294:16]
assign IBusSimplePlugin_fetchPc_output_ready = IBusSimplePlugin_iBusRsp_stages_0_input_ready; // @[Stream.scala 295:16]
assign IBusSimplePlugin_iBusRsp_stages_0_input_payload = IBusSimplePlugin_fetchPc_output_payload; // @[Stream.scala 296:18]
always @(*) begin
IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0; // @[Fetcher.scala 219:16]
if(when_IBusSimplePlugin_l305) begin
IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b1; // @[IBusSimplePlugin.scala 305:20]
end
end
assign _zz_IBusSimplePlugin_iBusRsp_stages_0_input_ready = (! IBusSimplePlugin_iBusRsp_stages_0_halt); // @[BaseType.scala 299:24]
assign IBusSimplePlugin_iBusRsp_stages_0_input_ready = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && _zz_IBusSimplePlugin_iBusRsp_stages_0_input_ready); // @[Stream.scala 427:16]
assign IBusSimplePlugin_iBusRsp_stages_0_output_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && _zz_IBusSimplePlugin_iBusRsp_stages_0_input_ready); // @[Stream.scala 294:16]
assign IBusSimplePlugin_iBusRsp_stages_0_output_payload = IBusSimplePlugin_iBusRsp_stages_0_input_payload; // @[Stream.scala 296:18]
assign IBusSimplePlugin_iBusRsp_stages_1_halt = 1'b0; // @[Fetcher.scala 219:16]
assign _zz_IBusSimplePlugin_iBusRsp_stages_1_input_ready = (! IBusSimplePlugin_iBusRsp_stages_1_halt); // @[BaseType.scala 299:24]
assign IBusSimplePlugin_iBusRsp_stages_1_input_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_ready && _zz_IBusSimplePlugin_iBusRsp_stages_1_input_ready); // @[Stream.scala 427:16]
assign IBusSimplePlugin_iBusRsp_stages_1_output_valid = (IBusSimplePlugin_iBusRsp_stages_1_input_valid && _zz_IBusSimplePlugin_iBusRsp_stages_1_input_ready); // @[Stream.scala 294:16]
assign IBusSimplePlugin_iBusRsp_stages_1_output_payload = IBusSimplePlugin_iBusRsp_stages_1_input_payload; // @[Stream.scala 296:18]
assign IBusSimplePlugin_iBusRsp_flush = (IBusSimplePlugin_externalFlush || IBusSimplePlugin_iBusRsp_redoFetch); // @[BaseType.scala 305:24]
assign IBusSimplePlugin_iBusRsp_stages_0_output_ready = _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready; // @[Stream.scala 304:16]
assign _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusSimplePlugin_iBusRsp_stages_1_input_valid)) || IBusSimplePlugin_iBusRsp_stages_1_input_ready); // @[Misc.scala 148:20]
assign _zz_IBusSimplePlugin_iBusRsp_stages_1_input_valid = _zz_IBusSimplePlugin_iBusRsp_stages_1_input_valid_1; // @[Misc.scala 158:17]
assign IBusSimplePlugin_iBusRsp_stages_1_input_valid = _zz_IBusSimplePlugin_iBusRsp_stages_1_input_valid; // @[Stream.scala 303:16]
assign IBusSimplePlugin_iBusRsp_stages_1_input_payload = IBusSimplePlugin_fetchPc_pcReg; // @[Fetcher.scala 234:31]
always @(*) begin
IBusSimplePlugin_iBusRsp_readyForError = 1'b1; // @[Fetcher.scala 241:27]
if(IBusSimplePlugin_injector_decodeInput_valid) begin
IBusSimplePlugin_iBusRsp_readyForError = 1'b0; // @[Fetcher.scala 316:40]
end
if(when_Fetcher_l323) begin
IBusSimplePlugin_iBusRsp_readyForError = 1'b0; // @[Fetcher.scala 323:55]
end
end
assign IBusSimplePlugin_iBusRsp_output_ready = ((1'b0 && (! IBusSimplePlugin_injector_decodeInput_valid)) || IBusSimplePlugin_injector_decodeInput_ready); // @[Misc.scala 148:20]
assign IBusSimplePlugin_injector_decodeInput_valid = _zz_IBusSimplePlugin_injector_decodeInput_valid; // @[Misc.scala 158:17]
assign IBusSimplePlugin_injector_decodeInput_payload_pc = _zz_IBusSimplePlugin_injector_decodeInput_payload_pc; // @[Misc.scala 159:19]
assign IBusSimplePlugin_injector_decodeInput_payload_rsp_error = _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_error; // @[Misc.scala 159:19]
assign IBusSimplePlugin_injector_decodeInput_payload_rsp_inst = _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; // @[Misc.scala 159:19]
assign IBusSimplePlugin_injector_decodeInput_payload_isRvc = _zz_IBusSimplePlugin_injector_decodeInput_payload_isRvc; // @[Misc.scala 159:19]
assign when_Fetcher_l323 = (! IBusSimplePlugin_pcValids_0); // @[BaseType.scala 299:24]
assign when_Fetcher_l332 = (! (! IBusSimplePlugin_iBusRsp_stages_1_input_ready)); // @[BaseType.scala 299:24]
assign when_Fetcher_l332_1 = (! (! IBusSimplePlugin_injector_decodeInput_ready)); // @[BaseType.scala 299:24]
assign when_Fetcher_l332_2 = (! execute_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Fetcher_l332_3 = (! memory_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Fetcher_l332_4 = (! writeBack_arbitration_isStuck); // @[BaseType.scala 299:24]
assign IBusSimplePlugin_pcValids_0 = IBusSimplePlugin_injector_nextPcCalc_valids_1; // @[Fetcher.scala 348:18]
assign IBusSimplePlugin_pcValids_1 = IBusSimplePlugin_injector_nextPcCalc_valids_2; // @[Fetcher.scala 348:18]
assign IBusSimplePlugin_pcValids_2 = IBusSimplePlugin_injector_nextPcCalc_valids_3; // @[Fetcher.scala 348:18]
assign IBusSimplePlugin_pcValids_3 = IBusSimplePlugin_injector_nextPcCalc_valids_4; // @[Fetcher.scala 348:18]
assign IBusSimplePlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck); // @[Fetcher.scala 351:25]
always @(*) begin
decode_arbitration_isValid = IBusSimplePlugin_injector_decodeInput_valid; // @[Fetcher.scala 352:34]
if(IBusSimplePlugin_forceNoDecodeCond) begin
decode_arbitration_isValid = 1'b0; // @[Fetcher.scala 415:36]
end
end
assign _zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch = _zz__zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch[11]; // @[BaseType.scala 305:24]
always @(*) begin
_zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch_1[18] = _zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch_1[17] = _zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch_1[16] = _zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch_1[15] = _zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch_1[14] = _zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch_1[13] = _zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch_1[12] = _zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch_1[11] = _zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch_1[10] = _zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch_1[9] = _zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch_1[8] = _zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch_1[7] = _zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch_1[6] = _zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch_1[5] = _zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch_1[4] = _zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch_1[3] = _zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch_1[2] = _zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch_1[1] = _zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch_1[0] = _zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch; // @[Literal.scala 87:17]
end
always @(*) begin
IBusSimplePlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == BranchCtrlEnum_JAL) || ((decode_BRANCH_CTRL == BranchCtrlEnum_B) && _zz_IBusSimplePlugin_decodePrediction_cmd_hadBranch_2[31])); // @[Fetcher.scala 509:40]
if(_zz_6) begin
IBusSimplePlugin_decodePrediction_cmd_hadBranch = 1'b0; // @[Fetcher.scala 516:42]
end
end
assign _zz_2 = _zz__zz_2[19]; // @[BaseType.scala 305:24]
always @(*) begin
_zz_3[10] = _zz_2; // @[Literal.scala 87:17]
_zz_3[9] = _zz_2; // @[Literal.scala 87:17]
_zz_3[8] = _zz_2; // @[Literal.scala 87:17]
_zz_3[7] = _zz_2; // @[Literal.scala 87:17]
_zz_3[6] = _zz_2; // @[Literal.scala 87:17]
_zz_3[5] = _zz_2; // @[Literal.scala 87:17]
_zz_3[4] = _zz_2; // @[Literal.scala 87:17]
_zz_3[3] = _zz_2; // @[Literal.scala 87:17]
_zz_3[2] = _zz_2; // @[Literal.scala 87:17]
_zz_3[1] = _zz_2; // @[Literal.scala 87:17]
_zz_3[0] = _zz_2; // @[Literal.scala 87:17]
end
assign _zz_4 = _zz__zz_4[11]; // @[BaseType.scala 305:24]
always @(*) begin
_zz_5[18] = _zz_4; // @[Literal.scala 87:17]
_zz_5[17] = _zz_4; // @[Literal.scala 87:17]
_zz_5[16] = _zz_4; // @[Literal.scala 87:17]
_zz_5[15] = _zz_4; // @[Literal.scala 87:17]
_zz_5[14] = _zz_4; // @[Literal.scala 87:17]
_zz_5[13] = _zz_4; // @[Literal.scala 87:17]
_zz_5[12] = _zz_4; // @[Literal.scala 87:17]
_zz_5[11] = _zz_4; // @[Literal.scala 87:17]
_zz_5[10] = _zz_4; // @[Literal.scala 87:17]
_zz_5[9] = _zz_4; // @[Literal.scala 87:17]
_zz_5[8] = _zz_4; // @[Literal.scala 87:17]
_zz_5[7] = _zz_4; // @[Literal.scala 87:17]
_zz_5[6] = _zz_4; // @[Literal.scala 87:17]
_zz_5[5] = _zz_4; // @[Literal.scala 87:17]
_zz_5[4] = _zz_4; // @[Literal.scala 87:17]
_zz_5[3] = _zz_4; // @[Literal.scala 87:17]
_zz_5[2] = _zz_4; // @[Literal.scala 87:17]
_zz_5[1] = _zz_4; // @[Literal.scala 87:17]
_zz_5[0] = _zz_4; // @[Literal.scala 87:17]
end
always @(*) begin
case(decode_BRANCH_CTRL)
BranchCtrlEnum_JAL : begin
_zz_6 = _zz__zz_6[1]; // @[Misc.scala 239:22]
end
default : begin
_zz_6 = _zz__zz_6_1[1]; // @[Misc.scala 235:22]
end
endcase
end
assign IBusSimplePlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusSimplePlugin_decodePrediction_cmd_hadBranch); // @[Fetcher.scala 520:39]
assign _zz_IBusSimplePlugin_predictionJumpInterface_payload = _zz__zz_IBusSimplePlugin_predictionJumpInterface_payload[19]; // @[BaseType.scala 305:24]
always @(*) begin
_zz_IBusSimplePlugin_predictionJumpInterface_payload_1[10] = _zz_IBusSimplePlugin_predictionJumpInterface_payload; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_predictionJumpInterface_payload_1[9] = _zz_IBusSimplePlugin_predictionJumpInterface_payload; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_predictionJumpInterface_payload_1[8] = _zz_IBusSimplePlugin_predictionJumpInterface_payload; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_predictionJumpInterface_payload_1[7] = _zz_IBusSimplePlugin_predictionJumpInterface_payload; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_predictionJumpInterface_payload_1[6] = _zz_IBusSimplePlugin_predictionJumpInterface_payload; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_predictionJumpInterface_payload_1[5] = _zz_IBusSimplePlugin_predictionJumpInterface_payload; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_predictionJumpInterface_payload_1[4] = _zz_IBusSimplePlugin_predictionJumpInterface_payload; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_predictionJumpInterface_payload_1[3] = _zz_IBusSimplePlugin_predictionJumpInterface_payload; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_predictionJumpInterface_payload_1[2] = _zz_IBusSimplePlugin_predictionJumpInterface_payload; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_predictionJumpInterface_payload_1[1] = _zz_IBusSimplePlugin_predictionJumpInterface_payload; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_predictionJumpInterface_payload_1[0] = _zz_IBusSimplePlugin_predictionJumpInterface_payload; // @[Literal.scala 87:17]
end
assign _zz_IBusSimplePlugin_predictionJumpInterface_payload_2 = _zz__zz_IBusSimplePlugin_predictionJumpInterface_payload_2[11]; // @[BaseType.scala 305:24]
always @(*) begin
_zz_IBusSimplePlugin_predictionJumpInterface_payload_3[18] = _zz_IBusSimplePlugin_predictionJumpInterface_payload_2; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_predictionJumpInterface_payload_3[17] = _zz_IBusSimplePlugin_predictionJumpInterface_payload_2; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_predictionJumpInterface_payload_3[16] = _zz_IBusSimplePlugin_predictionJumpInterface_payload_2; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_predictionJumpInterface_payload_3[15] = _zz_IBusSimplePlugin_predictionJumpInterface_payload_2; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_predictionJumpInterface_payload_3[14] = _zz_IBusSimplePlugin_predictionJumpInterface_payload_2; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_predictionJumpInterface_payload_3[13] = _zz_IBusSimplePlugin_predictionJumpInterface_payload_2; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_predictionJumpInterface_payload_3[12] = _zz_IBusSimplePlugin_predictionJumpInterface_payload_2; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_predictionJumpInterface_payload_3[11] = _zz_IBusSimplePlugin_predictionJumpInterface_payload_2; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_predictionJumpInterface_payload_3[10] = _zz_IBusSimplePlugin_predictionJumpInterface_payload_2; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_predictionJumpInterface_payload_3[9] = _zz_IBusSimplePlugin_predictionJumpInterface_payload_2; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_predictionJumpInterface_payload_3[8] = _zz_IBusSimplePlugin_predictionJumpInterface_payload_2; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_predictionJumpInterface_payload_3[7] = _zz_IBusSimplePlugin_predictionJumpInterface_payload_2; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_predictionJumpInterface_payload_3[6] = _zz_IBusSimplePlugin_predictionJumpInterface_payload_2; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_predictionJumpInterface_payload_3[5] = _zz_IBusSimplePlugin_predictionJumpInterface_payload_2; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_predictionJumpInterface_payload_3[4] = _zz_IBusSimplePlugin_predictionJumpInterface_payload_2; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_predictionJumpInterface_payload_3[3] = _zz_IBusSimplePlugin_predictionJumpInterface_payload_2; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_predictionJumpInterface_payload_3[2] = _zz_IBusSimplePlugin_predictionJumpInterface_payload_2; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_predictionJumpInterface_payload_3[1] = _zz_IBusSimplePlugin_predictionJumpInterface_payload_2; // @[Literal.scala 87:17]
_zz_IBusSimplePlugin_predictionJumpInterface_payload_3[0] = _zz_IBusSimplePlugin_predictionJumpInterface_payload_2; // @[Literal.scala 87:17]
end
assign IBusSimplePlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == BranchCtrlEnum_JAL) ? {{_zz_IBusSimplePlugin_predictionJumpInterface_payload_1,{{{_zz_IBusSimplePlugin_predictionJumpInterface_payload_4,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_IBusSimplePlugin_predictionJumpInterface_payload_3,{{{_zz_IBusSimplePlugin_predictionJumpInterface_payload_5,_zz_IBusSimplePlugin_predictionJumpInterface_payload_6},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); // @[Fetcher.scala 521:41]
assign iBus_cmd_valid = IBusSimplePlugin_cmd_valid; // @[Stream.scala 294:16]
assign IBusSimplePlugin_cmd_ready = iBus_cmd_ready; // @[Stream.scala 295:16]
assign iBus_cmd_payload_pc = IBusSimplePlugin_cmd_payload_pc; // @[Stream.scala 296:18]
assign IBusSimplePlugin_pending_next = (_zz_IBusSimplePlugin_pending_next - _zz_IBusSimplePlugin_pending_next_3); // @[BaseType.scala 299:24]
assign IBusSimplePlugin_cmdFork_canEmit = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && (IBusSimplePlugin_pending_value != 3'b111)); // @[BaseType.scala 305:24]
assign when_IBusSimplePlugin_l305 = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && ((! IBusSimplePlugin_cmdFork_canEmit) || (! IBusSimplePlugin_cmd_ready))); // @[BaseType.scala 305:24]
assign IBusSimplePlugin_cmd_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && IBusSimplePlugin_cmdFork_canEmit); // @[IBusSimplePlugin.scala 306:19]
assign IBusSimplePlugin_cmd_fire = (IBusSimplePlugin_cmd_valid && IBusSimplePlugin_cmd_ready); // @[BaseType.scala 305:24]
assign IBusSimplePlugin_pending_inc = IBusSimplePlugin_cmd_fire; // @[IBusSimplePlugin.scala 307:21]
assign IBusSimplePlugin_cmd_payload_pc = {IBusSimplePlugin_iBusRsp_stages_0_input_payload[31 : 2],2'b00}; // @[IBusSimplePlugin.scala 347:16]
assign iBus_rsp_toStream_valid = iBus_rsp_valid; // @[Flow.scala 72:15]
assign iBus_rsp_toStream_payload_error = iBus_rsp_payload_error; // @[Flow.scala 73:17]
assign iBus_rsp_toStream_payload_inst = iBus_rsp_payload_inst; // @[Flow.scala 73:17]
assign iBus_rsp_toStream_ready = IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready; // @[Stream.scala 295:16]
assign IBusSimplePlugin_rspJoin_rspBuffer_flush = ((IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != 3'b000) || IBusSimplePlugin_iBusRsp_flush); // @[BaseType.scala 305:24]
assign IBusSimplePlugin_rspJoin_rspBuffer_output_valid = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter == 3'b000)); // @[IBusSimplePlugin.scala 366:24]
assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; // @[IBusSimplePlugin.scala 367:26]
assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; // @[IBusSimplePlugin.scala 367:26]
assign IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_ready = (IBusSimplePlugin_rspJoin_rspBuffer_output_ready || IBusSimplePlugin_rspJoin_rspBuffer_flush); // @[IBusSimplePlugin.scala 368:26]
assign toplevel_IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_fire = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_ready); // @[BaseType.scala 305:24]
assign IBusSimplePlugin_pending_dec = toplevel_IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_fire; // @[IBusSimplePlugin.scala 370:23]
assign IBusSimplePlugin_rspJoin_fetchRsp_pc = IBusSimplePlugin_iBusRsp_stages_1_output_payload; // @[IBusSimplePlugin.scala 374:21]
always @(*) begin
IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error; // @[IBusSimplePlugin.scala 375:22]
if(when_IBusSimplePlugin_l376) begin
IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = 1'b0; // @[IBusSimplePlugin.scala 376:37]
end
end
assign IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst; // @[IBusSimplePlugin.scala 375:22]
assign when_IBusSimplePlugin_l376 = (! IBusSimplePlugin_rspJoin_rspBuffer_output_valid); // @[BaseType.scala 299:24]
assign IBusSimplePlugin_rspJoin_exceptionDetected = 1'b0; // @[IBusSimplePlugin.scala 384:33]
assign IBusSimplePlugin_rspJoin_join_valid = (IBusSimplePlugin_iBusRsp_stages_1_output_valid && IBusSimplePlugin_rspJoin_rspBuffer_output_valid); // @[IBusSimplePlugin.scala 385:20]
assign IBusSimplePlugin_rspJoin_join_payload_pc = IBusSimplePlugin_rspJoin_fetchRsp_pc; // @[IBusSimplePlugin.scala 386:22]
assign IBusSimplePlugin_rspJoin_join_payload_rsp_error = IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; // @[IBusSimplePlugin.scala 386:22]
assign IBusSimplePlugin_rspJoin_join_payload_rsp_inst = IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; // @[IBusSimplePlugin.scala 386:22]
assign IBusSimplePlugin_rspJoin_join_payload_isRvc = IBusSimplePlugin_rspJoin_fetchRsp_isRvc; // @[IBusSimplePlugin.scala 386:22]
assign IBusSimplePlugin_rspJoin_join_fire = (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready); // @[BaseType.scala 305:24]
assign IBusSimplePlugin_iBusRsp_stages_1_output_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_valid ? IBusSimplePlugin_rspJoin_join_fire : IBusSimplePlugin_rspJoin_join_ready); // @[IBusSimplePlugin.scala 387:34]
assign IBusSimplePlugin_rspJoin_join_fire_1 = (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready); // @[BaseType.scala 305:24]
assign IBusSimplePlugin_rspJoin_rspBuffer_output_ready = IBusSimplePlugin_rspJoin_join_fire_1; // @[IBusSimplePlugin.scala 388:32]
assign _zz_IBusSimplePlugin_iBusRsp_output_valid = (! IBusSimplePlugin_rspJoin_exceptionDetected); // @[BaseType.scala 299:24]
assign IBusSimplePlugin_rspJoin_join_ready = (IBusSimplePlugin_iBusRsp_output_ready && _zz_IBusSimplePlugin_iBusRsp_output_valid); // @[Stream.scala 427:16]
assign IBusSimplePlugin_iBusRsp_output_valid = (IBusSimplePlugin_rspJoin_join_valid && _zz_IBusSimplePlugin_iBusRsp_output_valid); // @[Stream.scala 294:16]
assign IBusSimplePlugin_iBusRsp_output_payload_pc = IBusSimplePlugin_rspJoin_join_payload_pc; // @[Stream.scala 296:18]
assign IBusSimplePlugin_iBusRsp_output_payload_rsp_error = IBusSimplePlugin_rspJoin_join_payload_rsp_error; // @[Stream.scala 296:18]
assign IBusSimplePlugin_iBusRsp_output_payload_rsp_inst = IBusSimplePlugin_rspJoin_join_payload_rsp_inst; // @[Stream.scala 296:18]
assign IBusSimplePlugin_iBusRsp_output_payload_isRvc = IBusSimplePlugin_rspJoin_join_payload_isRvc; // @[Stream.scala 296:18]
assign _zz_dBus_cmd_valid = 1'b0; // @[DBusSimplePlugin.scala 404:127]
always @(*) begin
execute_DBusSimplePlugin_skipCmd = 1'b0; // @[DBusSimplePlugin.scala 417:21]
if(execute_ALIGNEMENT_FAULT) begin
execute_DBusSimplePlugin_skipCmd = 1'b1; // @[DBusSimplePlugin.scala 418:15]
end
end
assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_dBus_cmd_valid)); // @[DBusSimplePlugin.scala 420:22]
assign dBus_cmd_payload_wr = execute_MEMORY_STORE; // @[DBusSimplePlugin.scala 421:19]
assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; // @[DBusSimplePlugin.scala 422:21]
always @(*) begin
case(dBus_cmd_payload_size)
2'b00 : begin
_zz_dBus_cmd_payload_data = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; // @[Misc.scala 239:22]
end
2'b01 : begin
_zz_dBus_cmd_payload_data = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; // @[Misc.scala 239:22]
end
default : begin
_zz_dBus_cmd_payload_data = execute_RS2[31 : 0]; // @[Misc.scala 235:22]
end
endcase
end
assign dBus_cmd_payload_data = _zz_dBus_cmd_payload_data; // @[DBusSimplePlugin.scala 423:29]
assign when_DBusSimplePlugin_l428 = ((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_dBus_cmd_valid)); // @[BaseType.scala 305:24]
always @(*) begin
case(dBus_cmd_payload_size)
2'b00 : begin
_zz_execute_DBusSimplePlugin_formalMask = 4'b0001; // @[Misc.scala 239:22]
end
2'b01 : begin
_zz_execute_DBusSimplePlugin_formalMask = 4'b0011; // @[Misc.scala 239:22]
end
default : begin
_zz_execute_DBusSimplePlugin_formalMask = 4'b1111; // @[Misc.scala 235:22]
end
endcase
end
assign execute_DBusSimplePlugin_formalMask = (_zz_execute_DBusSimplePlugin_formalMask <<< dBus_cmd_payload_address[1 : 0]); // @[BaseType.scala 299:24]
assign dBus_cmd_payload_address = execute_SRC_ADD; // @[DBusSimplePlugin.scala 458:26]
assign when_DBusSimplePlugin_l482 = (((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)); // @[BaseType.scala 305:24]
always @(*) begin
writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA; // @[DBusSimplePlugin.scala 530:18]
case(writeBack_MEMORY_ADDRESS_LOW)
2'b01 : begin
writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[15 : 8]; // @[DBusSimplePlugin.scala 539:40]
end
2'b10 : begin
writeBack_DBusSimplePlugin_rspShifted[15 : 0] = writeBack_MEMORY_READ_DATA[31 : 16]; // @[DBusSimplePlugin.scala 540:41]
end
2'b11 : begin
writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[31 : 24]; // @[DBusSimplePlugin.scala 541:40]
end
default : begin
end
endcase
end
assign switch_Misc_l226 = writeBack_INSTRUCTION[13 : 12]; // @[BaseType.scala 299:24]
assign _zz_writeBack_DBusSimplePlugin_rspFormated = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); // @[BaseType.scala 305:24]
always @(*) begin
_zz_writeBack_DBusSimplePlugin_rspFormated_1[31] = _zz_writeBack_DBusSimplePlugin_rspFormated; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_1[30] = _zz_writeBack_DBusSimplePlugin_rspFormated; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_1[29] = _zz_writeBack_DBusSimplePlugin_rspFormated; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_1[28] = _zz_writeBack_DBusSimplePlugin_rspFormated; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_1[27] = _zz_writeBack_DBusSimplePlugin_rspFormated; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_1[26] = _zz_writeBack_DBusSimplePlugin_rspFormated; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_1[25] = _zz_writeBack_DBusSimplePlugin_rspFormated; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_1[24] = _zz_writeBack_DBusSimplePlugin_rspFormated; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_1[23] = _zz_writeBack_DBusSimplePlugin_rspFormated; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_1[22] = _zz_writeBack_DBusSimplePlugin_rspFormated; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_1[21] = _zz_writeBack_DBusSimplePlugin_rspFormated; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_1[20] = _zz_writeBack_DBusSimplePlugin_rspFormated; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_1[19] = _zz_writeBack_DBusSimplePlugin_rspFormated; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_1[18] = _zz_writeBack_DBusSimplePlugin_rspFormated; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_1[17] = _zz_writeBack_DBusSimplePlugin_rspFormated; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_1[16] = _zz_writeBack_DBusSimplePlugin_rspFormated; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_1[15] = _zz_writeBack_DBusSimplePlugin_rspFormated; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_1[14] = _zz_writeBack_DBusSimplePlugin_rspFormated; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_1[13] = _zz_writeBack_DBusSimplePlugin_rspFormated; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_1[12] = _zz_writeBack_DBusSimplePlugin_rspFormated; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_1[11] = _zz_writeBack_DBusSimplePlugin_rspFormated; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_1[10] = _zz_writeBack_DBusSimplePlugin_rspFormated; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_1[9] = _zz_writeBack_DBusSimplePlugin_rspFormated; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_1[8] = _zz_writeBack_DBusSimplePlugin_rspFormated; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_1[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; // @[Literal.scala 99:91]
end
assign _zz_writeBack_DBusSimplePlugin_rspFormated_2 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); // @[BaseType.scala 305:24]
always @(*) begin
_zz_writeBack_DBusSimplePlugin_rspFormated_3[31] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_3[30] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_3[29] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_3[28] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_3[27] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_3[26] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_3[25] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_3[24] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_3[23] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_3[22] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_3[21] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_3[20] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_3[19] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_3[18] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_3[17] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_3[16] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; // @[Literal.scala 87:17]
_zz_writeBack_DBusSimplePlugin_rspFormated_3[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; // @[Literal.scala 99:91]
end
always @(*) begin
case(switch_Misc_l226)
2'b00 : begin
writeBack_DBusSimplePlugin_rspFormated = _zz_writeBack_DBusSimplePlugin_rspFormated_1; // @[Misc.scala 239:22]
end
2'b01 : begin
writeBack_DBusSimplePlugin_rspFormated = _zz_writeBack_DBusSimplePlugin_rspFormated_3; // @[Misc.scala 239:22]
end
default : begin
writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted; // @[Misc.scala 235:22]
end
endcase
end
assign when_DBusSimplePlugin_l558 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); // @[BaseType.scala 305:24]
assign _zz_decode_IS_MUL_1 = ((decode_INSTRUCTION & 32'h00000018) == 32'h0); // @[BaseType.scala 305:24]
assign _zz_decode_IS_MUL_2 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); // @[BaseType.scala 305:24]
assign _zz_decode_IS_MUL_3 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); // @[BaseType.scala 305:24]
assign _zz_decode_IS_MUL = {(|((decode_INSTRUCTION & 32'h02000034) == 32'h02000030)),{(|{_zz_decode_IS_MUL_3,(_zz__zz_decode_IS_MUL == _zz__zz_decode_IS_MUL_1)}),{(|(_zz__zz_decode_IS_MUL_2 == _zz__zz_decode_IS_MUL_3)),{(|_zz__zz_decode_IS_MUL_4),{(|_zz__zz_decode_IS_MUL_5),{_zz__zz_decode_IS_MUL_8,{_zz__zz_decode_IS_MUL_10,_zz__zz_decode_IS_MUL_13}}}}}}}; // @[DecoderSimplePlugin.scala 161:19]
assign _zz_decode_SRC1_CTRL_2 = _zz_decode_IS_MUL[1 : 0]; // @[Enum.scala 186:17]
assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2; // @[Enum.scala 188:10]
assign _zz_decode_SRC2_CTRL_2 = _zz_decode_IS_MUL[6 : 5]; // @[Enum.scala 186:17]
assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2; // @[Enum.scala 188:10]
assign _zz_decode_ALU_CTRL_2 = _zz_decode_IS_MUL[14 : 13]; // @[Enum.scala 186:17]
assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2; // @[Enum.scala 188:10]
assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_IS_MUL[17 : 16]; // @[Enum.scala 186:17]
assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2; // @[Enum.scala 188:10]
assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_IS_MUL[20 : 19]; // @[Enum.scala 186:17]
assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2; // @[Enum.scala 188:10]
assign _zz_decode_BRANCH_CTRL_2 = _zz_decode_IS_MUL[22 : 21]; // @[Enum.scala 186:17]
assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_2; // @[Enum.scala 188:10]
assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0); // @[BaseType.scala 305:24]
assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; // @[BaseType.scala 318:22]
assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; // @[BaseType.scala 318:22]
assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0; // @[Bits.scala 133:56]
assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1; // @[Bits.scala 133:56]
always @(*) begin
lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); // @[RegFilePlugin.scala 102:26]
if(_zz_7) begin
lastStageRegFileWrite_valid = 1'b1; // @[RegFilePlugin.scala 114:28]
end
end
always @(*) begin
lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; // @[RegFilePlugin.scala 103:28]
if(_zz_7) begin
lastStageRegFileWrite_payload_address = 5'h0; // @[RegFilePlugin.scala 116:32]
end
end
always @(*) begin
lastStageRegFileWrite_payload_data = _zz_decode_RS2_2; // @[RegFilePlugin.scala 104:25]
if(_zz_7) begin
lastStageRegFileWrite_payload_data = 32'h0; // @[RegFilePlugin.scala 117:29]
end
end
always @(*) begin
case(execute_ALU_BITWISE_CTRL)
AluBitwiseCtrlEnum_AND_1 : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); // @[Misc.scala 239:22]
end
AluBitwiseCtrlEnum_OR_1 : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); // @[Misc.scala 239:22]
end
default : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); // @[Misc.scala 239:22]
end
endcase
end
always @(*) begin
case(execute_ALU_CTRL)
AluCtrlEnum_BITWISE : begin
_zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise; // @[Misc.scala 239:22]
end
AluCtrlEnum_SLT_SLTU : begin
_zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA}; // @[Misc.scala 239:22]
end
default : begin
_zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB; // @[Misc.scala 239:22]
end
endcase
end
always @(*) begin
case(decode_SRC1_CTRL)
Src1CtrlEnum_RS : begin
_zz_decode_SRC1 = _zz_decode_to_execute_RS1; // @[Misc.scala 239:22]
end
Src1CtrlEnum_PC_INCREMENT : begin
_zz_decode_SRC1 = {29'd0, _zz__zz_decode_SRC1}; // @[Misc.scala 239:22]
end
Src1CtrlEnum_IMU : begin
_zz_decode_SRC1 = {decode_INSTRUCTION[31 : 12],12'h0}; // @[Misc.scala 239:22]
end
default : begin
_zz_decode_SRC1 = {27'd0, _zz__zz_decode_SRC1_1}; // @[Misc.scala 239:22]
end
endcase
end
assign _zz_decode_SRC2 = decode_INSTRUCTION[31]; // @[BaseType.scala 305:24]
always @(*) begin
_zz_decode_SRC2_1[19] = _zz_decode_SRC2; // @[Literal.scala 87:17]
_zz_decode_SRC2_1[18] = _zz_decode_SRC2; // @[Literal.scala 87:17]
_zz_decode_SRC2_1[17] = _zz_decode_SRC2; // @[Literal.scala 87:17]
_zz_decode_SRC2_1[16] = _zz_decode_SRC2; // @[Literal.scala 87:17]
_zz_decode_SRC2_1[15] = _zz_decode_SRC2; // @[Literal.scala 87:17]
_zz_decode_SRC2_1[14] = _zz_decode_SRC2; // @[Literal.scala 87:17]
_zz_decode_SRC2_1[13] = _zz_decode_SRC2; // @[Literal.scala 87:17]
_zz_decode_SRC2_1[12] = _zz_decode_SRC2; // @[Literal.scala 87:17]
_zz_decode_SRC2_1[11] = _zz_decode_SRC2; // @[Literal.scala 87:17]
_zz_decode_SRC2_1[10] = _zz_decode_SRC2; // @[Literal.scala 87:17]
_zz_decode_SRC2_1[9] = _zz_decode_SRC2; // @[Literal.scala 87:17]
_zz_decode_SRC2_1[8] = _zz_decode_SRC2; // @[Literal.scala 87:17]
_zz_decode_SRC2_1[7] = _zz_decode_SRC2; // @[Literal.scala 87:17]
_zz_decode_SRC2_1[6] = _zz_decode_SRC2; // @[Literal.scala 87:17]
_zz_decode_SRC2_1[5] = _zz_decode_SRC2; // @[Literal.scala 87:17]
_zz_decode_SRC2_1[4] = _zz_decode_SRC2; // @[Literal.scala 87:17]
_zz_decode_SRC2_1[3] = _zz_decode_SRC2; // @[Literal.scala 87:17]
_zz_decode_SRC2_1[2] = _zz_decode_SRC2; // @[Literal.scala 87:17]
_zz_decode_SRC2_1[1] = _zz_decode_SRC2; // @[Literal.scala 87:17]
_zz_decode_SRC2_1[0] = _zz_decode_SRC2; // @[Literal.scala 87:17]
end
assign _zz_decode_SRC2_2 = _zz__zz_decode_SRC2_2[11]; // @[BaseType.scala 305:24]
always @(*) begin
_zz_decode_SRC2_3[19] = _zz_decode_SRC2_2; // @[Literal.scala 87:17]
_zz_decode_SRC2_3[18] = _zz_decode_SRC2_2; // @[Literal.scala 87:17]
_zz_decode_SRC2_3[17] = _zz_decode_SRC2_2; // @[Literal.scala 87:17]
_zz_decode_SRC2_3[16] = _zz_decode_SRC2_2; // @[Literal.scala 87:17]
_zz_decode_SRC2_3[15] = _zz_decode_SRC2_2; // @[Literal.scala 87:17]
_zz_decode_SRC2_3[14] = _zz_decode_SRC2_2; // @[Literal.scala 87:17]
_zz_decode_SRC2_3[13] = _zz_decode_SRC2_2; // @[Literal.scala 87:17]
_zz_decode_SRC2_3[12] = _zz_decode_SRC2_2; // @[Literal.scala 87:17]
_zz_decode_SRC2_3[11] = _zz_decode_SRC2_2; // @[Literal.scala 87:17]
_zz_decode_SRC2_3[10] = _zz_decode_SRC2_2; // @[Literal.scala 87:17]
_zz_decode_SRC2_3[9] = _zz_decode_SRC2_2; // @[Literal.scala 87:17]
_zz_decode_SRC2_3[8] = _zz_decode_SRC2_2; // @[Literal.scala 87:17]
_zz_decode_SRC2_3[7] = _zz_decode_SRC2_2; // @[Literal.scala 87:17]
_zz_decode_SRC2_3[6] = _zz_decode_SRC2_2; // @[Literal.scala 87:17]
_zz_decode_SRC2_3[5] = _zz_decode_SRC2_2; // @[Literal.scala 87:17]
_zz_decode_SRC2_3[4] = _zz_decode_SRC2_2; // @[Literal.scala 87:17]
_zz_decode_SRC2_3[3] = _zz_decode_SRC2_2; // @[Literal.scala 87:17]
_zz_decode_SRC2_3[2] = _zz_decode_SRC2_2; // @[Literal.scala 87:17]
_zz_decode_SRC2_3[1] = _zz_decode_SRC2_2; // @[Literal.scala 87:17]
_zz_decode_SRC2_3[0] = _zz_decode_SRC2_2; // @[Literal.scala 87:17]
end
always @(*) begin
case(decode_SRC2_CTRL)
Src2CtrlEnum_RS : begin
_zz_decode_SRC2_4 = _zz_decode_to_execute_RS2; // @[Misc.scala 239:22]
end
Src2CtrlEnum_IMI : begin
_zz_decode_SRC2_4 = {_zz_decode_SRC2_1,decode_INSTRUCTION[31 : 20]}; // @[Misc.scala 239:22]
end
Src2CtrlEnum_IMS : begin
_zz_decode_SRC2_4 = {_zz_decode_SRC2_3,{decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}}; // @[Misc.scala 239:22]
end
default : begin
_zz_decode_SRC2_4 = _zz_decode_to_execute_PC; // @[Misc.scala 239:22]
end
endcase
end
always @(*) begin
execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub; // @[BaseType.scala 318:22]
if(execute_SRC2_FORCE_ZERO) begin
execute_SrcPlugin_addSub = execute_SRC1; // @[SrcPlugin.scala 69:46]
end
end
assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); // @[Expression.scala 1420:25]
assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; // @[BaseType.scala 318:22]
always @(*) begin
_zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31]; // @[Utils.scala 432:14]
_zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30]; // @[Utils.scala 432:14]
_zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29]; // @[Utils.scala 432:14]
_zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28]; // @[Utils.scala 432:14]
_zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27]; // @[Utils.scala 432:14]
_zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26]; // @[Utils.scala 432:14]
_zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25]; // @[Utils.scala 432:14]
_zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24]; // @[Utils.scala 432:14]
_zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23]; // @[Utils.scala 432:14]
_zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22]; // @[Utils.scala 432:14]
_zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21]; // @[Utils.scala 432:14]
_zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20]; // @[Utils.scala 432:14]
_zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19]; // @[Utils.scala 432:14]
_zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18]; // @[Utils.scala 432:14]
_zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17]; // @[Utils.scala 432:14]
_zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16]; // @[Utils.scala 432:14]
_zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15]; // @[Utils.scala 432:14]
_zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14]; // @[Utils.scala 432:14]
_zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13]; // @[Utils.scala 432:14]
_zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12]; // @[Utils.scala 432:14]
_zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11]; // @[Utils.scala 432:14]
_zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10]; // @[Utils.scala 432:14]
_zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9]; // @[Utils.scala 432:14]
_zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8]; // @[Utils.scala 432:14]
_zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7]; // @[Utils.scala 432:14]
_zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6]; // @[Utils.scala 432:14]
_zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5]; // @[Utils.scala 432:14]
_zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4]; // @[Utils.scala 432:14]
_zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3]; // @[Utils.scala 432:14]
_zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2]; // @[Utils.scala 432:14]
_zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1]; // @[Utils.scala 432:14]
_zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0]; // @[Utils.scala 432:14]
end
assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == ShiftCtrlEnum_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1); // @[Expression.scala 1420:25]
always @(*) begin
_zz_decode_RS2_3[0] = memory_SHIFT_RIGHT[31]; // @[Utils.scala 432:14]
_zz_decode_RS2_3[1] = memory_SHIFT_RIGHT[30]; // @[Utils.scala 432:14]
_zz_decode_RS2_3[2] = memory_SHIFT_RIGHT[29]; // @[Utils.scala 432:14]
_zz_decode_RS2_3[3] = memory_SHIFT_RIGHT[28]; // @[Utils.scala 432:14]
_zz_decode_RS2_3[4] = memory_SHIFT_RIGHT[27]; // @[Utils.scala 432:14]
_zz_decode_RS2_3[5] = memory_SHIFT_RIGHT[26]; // @[Utils.scala 432:14]
_zz_decode_RS2_3[6] = memory_SHIFT_RIGHT[25]; // @[Utils.scala 432:14]
_zz_decode_RS2_3[7] = memory_SHIFT_RIGHT[24]; // @[Utils.scala 432:14]
_zz_decode_RS2_3[8] = memory_SHIFT_RIGHT[23]; // @[Utils.scala 432:14]
_zz_decode_RS2_3[9] = memory_SHIFT_RIGHT[22]; // @[Utils.scala 432:14]
_zz_decode_RS2_3[10] = memory_SHIFT_RIGHT[21]; // @[Utils.scala 432:14]
_zz_decode_RS2_3[11] = memory_SHIFT_RIGHT[20]; // @[Utils.scala 432:14]
_zz_decode_RS2_3[12] = memory_SHIFT_RIGHT[19]; // @[Utils.scala 432:14]
_zz_decode_RS2_3[13] = memory_SHIFT_RIGHT[18]; // @[Utils.scala 432:14]
_zz_decode_RS2_3[14] = memory_SHIFT_RIGHT[17]; // @[Utils.scala 432:14]
_zz_decode_RS2_3[15] = memory_SHIFT_RIGHT[16]; // @[Utils.scala 432:14]
_zz_decode_RS2_3[16] = memory_SHIFT_RIGHT[15]; // @[Utils.scala 432:14]
_zz_decode_RS2_3[17] = memory_SHIFT_RIGHT[14]; // @[Utils.scala 432:14]
_zz_decode_RS2_3[18] = memory_SHIFT_RIGHT[13]; // @[Utils.scala 432:14]
_zz_decode_RS2_3[19] = memory_SHIFT_RIGHT[12]; // @[Utils.scala 432:14]
_zz_decode_RS2_3[20] = memory_SHIFT_RIGHT[11]; // @[Utils.scala 432:14]
_zz_decode_RS2_3[21] = memory_SHIFT_RIGHT[10]; // @[Utils.scala 432:14]
_zz_decode_RS2_3[22] = memory_SHIFT_RIGHT[9]; // @[Utils.scala 432:14]
_zz_decode_RS2_3[23] = memory_SHIFT_RIGHT[8]; // @[Utils.scala 432:14]
_zz_decode_RS2_3[24] = memory_SHIFT_RIGHT[7]; // @[Utils.scala 432:14]
_zz_decode_RS2_3[25] = memory_SHIFT_RIGHT[6]; // @[Utils.scala 432:14]
_zz_decode_RS2_3[26] = memory_SHIFT_RIGHT[5]; // @[Utils.scala 432:14]
_zz_decode_RS2_3[27] = memory_SHIFT_RIGHT[4]; // @[Utils.scala 432:14]
_zz_decode_RS2_3[28] = memory_SHIFT_RIGHT[3]; // @[Utils.scala 432:14]
_zz_decode_RS2_3[29] = memory_SHIFT_RIGHT[2]; // @[Utils.scala 432:14]
_zz_decode_RS2_3[30] = memory_SHIFT_RIGHT[1]; // @[Utils.scala 432:14]
_zz_decode_RS2_3[31] = memory_SHIFT_RIGHT[0]; // @[Utils.scala 432:14]
end
always @(*) begin
HazardSimplePlugin_src0Hazard = 1'b0; // @[HazardSimplePlugin.scala 36:24]
if(when_HazardSimplePlugin_l57) begin
if(when_HazardSimplePlugin_l58) begin
if(when_HazardSimplePlugin_l48) begin
HazardSimplePlugin_src0Hazard = 1'b1; // @[HazardSimplePlugin.scala 60:26]
end
end
end
if(when_HazardSimplePlugin_l57_1) begin
if(when_HazardSimplePlugin_l58_1) begin
if(when_HazardSimplePlugin_l48_1) begin
HazardSimplePlugin_src0Hazard = 1'b1; // @[HazardSimplePlugin.scala 60:26]
end
end
end
if(when_HazardSimplePlugin_l57_2) begin
if(when_HazardSimplePlugin_l58_2) begin
if(when_HazardSimplePlugin_l48_2) begin
HazardSimplePlugin_src0Hazard = 1'b1; // @[HazardSimplePlugin.scala 60:26]
end
end
end
if(when_HazardSimplePlugin_l105) begin
HazardSimplePlugin_src0Hazard = 1'b0; // @[HazardSimplePlugin.scala 106:22]
end
end
always @(*) begin
HazardSimplePlugin_src1Hazard = 1'b0; // @[HazardSimplePlugin.scala 37:24]
if(when_HazardSimplePlugin_l57) begin
if(when_HazardSimplePlugin_l58) begin
if(when_HazardSimplePlugin_l51) begin
HazardSimplePlugin_src1Hazard = 1'b1; // @[HazardSimplePlugin.scala 63:26]
end
end
end
if(when_HazardSimplePlugin_l57_1) begin
if(when_HazardSimplePlugin_l58_1) begin
if(when_HazardSimplePlugin_l51_1) begin
HazardSimplePlugin_src1Hazard = 1'b1; // @[HazardSimplePlugin.scala 63:26]
end
end
end
if(when_HazardSimplePlugin_l57_2) begin
if(when_HazardSimplePlugin_l58_2) begin
if(when_HazardSimplePlugin_l51_2) begin
HazardSimplePlugin_src1Hazard = 1'b1; // @[HazardSimplePlugin.scala 63:26]
end
end
end
if(when_HazardSimplePlugin_l108) begin
HazardSimplePlugin_src1Hazard = 1'b0; // @[HazardSimplePlugin.scala 109:22]
end
end
assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); // @[HazardSimplePlugin.scala 74:29]
assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; // @[HazardSimplePlugin.scala 75:31]
assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2; // @[HazardSimplePlugin.scala 76:28]
assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); // @[BaseType.scala 305:24]
assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); // @[BaseType.scala 305:24]
assign when_HazardSimplePlugin_l47 = 1'b1; // @[HazardSimplePlugin.scala 42:105]
assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); // @[BaseType.scala 305:24]
assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); // @[BaseType.scala 305:24]
assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); // @[BaseType.scala 305:24]
assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); // @[BaseType.scala 305:24]
assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47)); // @[BaseType.scala 305:24]
assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); // @[BaseType.scala 305:24]
assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); // @[BaseType.scala 305:24]
assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); // @[BaseType.scala 305:24]
assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); // @[BaseType.scala 305:24]
assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); // @[BaseType.scala 305:24]
assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); // @[BaseType.scala 305:24]
assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); // @[BaseType.scala 305:24]
assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); // @[BaseType.scala 305:24]
assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); // @[BaseType.scala 305:24]
assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); // @[BaseType.scala 305:24]
assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE); // @[BaseType.scala 299:24]
assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE); // @[BaseType.scala 299:24]
assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)); // @[BaseType.scala 305:24]
assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); // @[BaseType.scala 305:24]
assign switch_Misc_l226_1 = execute_INSTRUCTION[14 : 12]; // @[BaseType.scala 299:24]
always @(*) begin
casez(switch_Misc_l226_1)
3'b000 : begin
_zz_execute_BRANCH_COND_RESULT = execute_BranchPlugin_eq; // @[Misc.scala 239:22]
end
3'b001 : begin
_zz_execute_BRANCH_COND_RESULT = (! execute_BranchPlugin_eq); // @[Misc.scala 239:22]
end
3'b1?1 : begin
_zz_execute_BRANCH_COND_RESULT = (! execute_SRC_LESS); // @[Misc.scala 239:22]
end
default : begin
_zz_execute_BRANCH_COND_RESULT = execute_SRC_LESS; // @[Misc.scala 235:22]
end
endcase
end
always @(*) begin
case(execute_BRANCH_CTRL)
BranchCtrlEnum_INC : begin
_zz_execute_BRANCH_COND_RESULT_1 = 1'b0; // @[Misc.scala 239:22]
end
BranchCtrlEnum_JAL : begin
_zz_execute_BRANCH_COND_RESULT_1 = 1'b1; // @[Misc.scala 239:22]
end
BranchCtrlEnum_JALR : begin
_zz_execute_BRANCH_COND_RESULT_1 = 1'b1; // @[Misc.scala 239:22]
end
default : begin
_zz_execute_BRANCH_COND_RESULT_1 = _zz_execute_BRANCH_COND_RESULT; // @[Misc.scala 239:22]
end
endcase
end
assign _zz_execute_BranchPlugin_missAlignedTarget = execute_INSTRUCTION[31]; // @[BaseType.scala 305:24]
always @(*) begin
_zz_execute_BranchPlugin_missAlignedTarget_1[19] = _zz_execute_BranchPlugin_missAlignedTarget; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_1[18] = _zz_execute_BranchPlugin_missAlignedTarget; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_1[17] = _zz_execute_BranchPlugin_missAlignedTarget; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_1[16] = _zz_execute_BranchPlugin_missAlignedTarget; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_1[15] = _zz_execute_BranchPlugin_missAlignedTarget; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_1[14] = _zz_execute_BranchPlugin_missAlignedTarget; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_1[13] = _zz_execute_BranchPlugin_missAlignedTarget; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_1[12] = _zz_execute_BranchPlugin_missAlignedTarget; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_1[11] = _zz_execute_BranchPlugin_missAlignedTarget; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_1[10] = _zz_execute_BranchPlugin_missAlignedTarget; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_1[9] = _zz_execute_BranchPlugin_missAlignedTarget; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_1[8] = _zz_execute_BranchPlugin_missAlignedTarget; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_1[7] = _zz_execute_BranchPlugin_missAlignedTarget; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_1[6] = _zz_execute_BranchPlugin_missAlignedTarget; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_1[5] = _zz_execute_BranchPlugin_missAlignedTarget; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_1[4] = _zz_execute_BranchPlugin_missAlignedTarget; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_1[3] = _zz_execute_BranchPlugin_missAlignedTarget; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_1[2] = _zz_execute_BranchPlugin_missAlignedTarget; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_1[1] = _zz_execute_BranchPlugin_missAlignedTarget; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_1[0] = _zz_execute_BranchPlugin_missAlignedTarget; // @[Literal.scala 87:17]
end
assign _zz_execute_BranchPlugin_missAlignedTarget_2 = _zz__zz_execute_BranchPlugin_missAlignedTarget_2[19]; // @[BaseType.scala 305:24]
always @(*) begin
_zz_execute_BranchPlugin_missAlignedTarget_3[10] = _zz_execute_BranchPlugin_missAlignedTarget_2; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_3[9] = _zz_execute_BranchPlugin_missAlignedTarget_2; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_3[8] = _zz_execute_BranchPlugin_missAlignedTarget_2; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_3[7] = _zz_execute_BranchPlugin_missAlignedTarget_2; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_3[6] = _zz_execute_BranchPlugin_missAlignedTarget_2; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_3[5] = _zz_execute_BranchPlugin_missAlignedTarget_2; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_3[4] = _zz_execute_BranchPlugin_missAlignedTarget_2; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_3[3] = _zz_execute_BranchPlugin_missAlignedTarget_2; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_3[2] = _zz_execute_BranchPlugin_missAlignedTarget_2; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_3[1] = _zz_execute_BranchPlugin_missAlignedTarget_2; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_3[0] = _zz_execute_BranchPlugin_missAlignedTarget_2; // @[Literal.scala 87:17]
end
assign _zz_execute_BranchPlugin_missAlignedTarget_4 = _zz__zz_execute_BranchPlugin_missAlignedTarget_4[11]; // @[BaseType.scala 305:24]
always @(*) begin
_zz_execute_BranchPlugin_missAlignedTarget_5[18] = _zz_execute_BranchPlugin_missAlignedTarget_4; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_5[17] = _zz_execute_BranchPlugin_missAlignedTarget_4; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_5[16] = _zz_execute_BranchPlugin_missAlignedTarget_4; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_5[15] = _zz_execute_BranchPlugin_missAlignedTarget_4; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_5[14] = _zz_execute_BranchPlugin_missAlignedTarget_4; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_5[13] = _zz_execute_BranchPlugin_missAlignedTarget_4; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_5[12] = _zz_execute_BranchPlugin_missAlignedTarget_4; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_5[11] = _zz_execute_BranchPlugin_missAlignedTarget_4; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_5[10] = _zz_execute_BranchPlugin_missAlignedTarget_4; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_5[9] = _zz_execute_BranchPlugin_missAlignedTarget_4; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_5[8] = _zz_execute_BranchPlugin_missAlignedTarget_4; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_5[7] = _zz_execute_BranchPlugin_missAlignedTarget_4; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_5[6] = _zz_execute_BranchPlugin_missAlignedTarget_4; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_5[5] = _zz_execute_BranchPlugin_missAlignedTarget_4; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_5[4] = _zz_execute_BranchPlugin_missAlignedTarget_4; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_5[3] = _zz_execute_BranchPlugin_missAlignedTarget_4; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_5[2] = _zz_execute_BranchPlugin_missAlignedTarget_4; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_5[1] = _zz_execute_BranchPlugin_missAlignedTarget_4; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_missAlignedTarget_5[0] = _zz_execute_BranchPlugin_missAlignedTarget_4; // @[Literal.scala 87:17]
end
always @(*) begin
case(execute_BRANCH_CTRL)
BranchCtrlEnum_JALR : begin
_zz_execute_BranchPlugin_missAlignedTarget_6 = (_zz__zz_execute_BranchPlugin_missAlignedTarget_6[1] ^ execute_RS1[1]); // @[Misc.scala 239:22]
end
BranchCtrlEnum_JAL : begin
_zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1[1]; // @[Misc.scala 239:22]
end
default : begin
_zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2[1]; // @[Misc.scala 235:22]
end
endcase
end
assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_execute_BranchPlugin_missAlignedTarget_6); // @[BaseType.scala 305:24]
always @(*) begin
case(execute_BRANCH_CTRL)
BranchCtrlEnum_JALR : begin
execute_BranchPlugin_branch_src1 = execute_RS1; // @[BranchPlugin.scala 272:23]
end
default : begin
execute_BranchPlugin_branch_src1 = execute_PC; // @[BranchPlugin.scala 276:23]
end
endcase
end
assign _zz_execute_BranchPlugin_branch_src2 = execute_INSTRUCTION[31]; // @[BaseType.scala 305:24]
always @(*) begin
_zz_execute_BranchPlugin_branch_src2_1[19] = _zz_execute_BranchPlugin_branch_src2; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_1[18] = _zz_execute_BranchPlugin_branch_src2; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_1[17] = _zz_execute_BranchPlugin_branch_src2; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_1[16] = _zz_execute_BranchPlugin_branch_src2; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_1[15] = _zz_execute_BranchPlugin_branch_src2; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_1[14] = _zz_execute_BranchPlugin_branch_src2; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_1[13] = _zz_execute_BranchPlugin_branch_src2; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_1[12] = _zz_execute_BranchPlugin_branch_src2; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_1[11] = _zz_execute_BranchPlugin_branch_src2; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2; // @[Literal.scala 87:17]
end
always @(*) begin
case(execute_BRANCH_CTRL)
BranchCtrlEnum_JALR : begin
execute_BranchPlugin_branch_src2 = {_zz_execute_BranchPlugin_branch_src2_1,execute_INSTRUCTION[31 : 20]}; // @[BranchPlugin.scala 273:23]
end
default : begin
execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == BranchCtrlEnum_JAL) ? {{_zz_execute_BranchPlugin_branch_src2_3,{{{_zz_execute_BranchPlugin_branch_src2_6,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_execute_BranchPlugin_branch_src2_5,{{{_zz_execute_BranchPlugin_branch_src2_7,_zz_execute_BranchPlugin_branch_src2_8},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); // @[BranchPlugin.scala 277:23]
if(execute_PREDICTION_HAD_BRANCHED2) begin
execute_BranchPlugin_branch_src2 = {29'd0, _zz_execute_BranchPlugin_branch_src2_9}; // @[BranchPlugin.scala 279:25]
end
end
endcase
end
assign _zz_execute_BranchPlugin_branch_src2_2 = _zz__zz_execute_BranchPlugin_branch_src2_2[19]; // @[BaseType.scala 305:24]
always @(*) begin
_zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2; // @[Literal.scala 87:17]
end
assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11]; // @[BaseType.scala 305:24]
always @(*) begin
_zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4; // @[Literal.scala 87:17]
_zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4; // @[Literal.scala 87:17]
end
assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); // @[BaseType.scala 299:24]
assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); // @[BranchPlugin.scala 292:27]
assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; // @[BranchPlugin.scala 293:29]
assign IBusSimplePlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; // @[BranchPlugin.scala 306:35]
assign execute_MulPlugin_a = execute_RS1; // @[MulPlugin.scala 83:11]
assign execute_MulPlugin_b = execute_RS2; // @[MulPlugin.scala 84:11]
assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12]; // @[BaseType.scala 299:24]
always @(*) begin
case(switch_MulPlugin_l87)
2'b01 : begin
execute_MulPlugin_aSigned = 1'b1; // @[MulPlugin.scala 89:19]
end
2'b10 : begin
execute_MulPlugin_aSigned = 1'b1; // @[MulPlugin.scala 93:19]
end
default : begin
execute_MulPlugin_aSigned = 1'b0; // @[MulPlugin.scala 97:19]
end
endcase
end
always @(*) begin
case(switch_MulPlugin_l87)
2'b01 : begin
execute_MulPlugin_bSigned = 1'b1; // @[MulPlugin.scala 90:19]
end
2'b10 : begin
execute_MulPlugin_bSigned = 1'b0; // @[MulPlugin.scala 94:19]
end
default : begin
execute_MulPlugin_bSigned = 1'b0; // @[MulPlugin.scala 98:19]
end
endcase
end
assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0]; // @[BaseType.scala 318:22]
assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0]; // @[BaseType.scala 318:22]
assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]}; // @[BaseType.scala 318:22]
assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; // @[BaseType.scala 318:22]
assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; // @[BaseType.scala 318:22]
assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; // @[BaseType.scala 318:22]
assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1)); // @[BaseType.scala 299:24]
assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL); // @[BaseType.scala 305:24]
assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12]; // @[BaseType.scala 299:24]
assign when_Pipeline_l124 = (! execute_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Pipeline_l124_2 = (! writeBack_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck); // @[BaseType.scala 299:24]
assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1; // @[Pipeline.scala 121:26]
assign when_Pipeline_l124_8 = (! execute_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Pipeline_l124_10 = (! memory_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Pipeline_l124_11 = (! writeBack_arbitration_isStuck); // @[BaseType.scala 299:24]
assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1; // @[Pipeline.scala 121:26]
assign when_Pipeline_l124_12 = (! execute_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Pipeline_l124_13 = (! memory_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Pipeline_l124_14 = (! writeBack_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Pipeline_l124_16 = (! execute_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Pipeline_l124_17 = (! memory_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Pipeline_l124_18 = (! execute_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Pipeline_l124_19 = (! memory_arbitration_isStuck); // @[BaseType.scala 299:24]
assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL; // @[Pipeline.scala 110:25]
assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1; // @[Pipeline.scala 121:26]
assign when_Pipeline_l124_20 = (! execute_arbitration_isStuck); // @[BaseType.scala 299:24]
assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL; // @[Pipeline.scala 124:26]
assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck); // @[BaseType.scala 299:24]
assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL; // @[Pipeline.scala 110:25]
assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1; // @[Pipeline.scala 121:26]
assign when_Pipeline_l124_22 = (! execute_arbitration_isStuck); // @[BaseType.scala 299:24]
assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL; // @[Pipeline.scala 124:26]
assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL; // @[Pipeline.scala 110:25]
assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL; // @[Pipeline.scala 110:25]
assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1; // @[Pipeline.scala 121:26]
assign when_Pipeline_l124_23 = (! execute_arbitration_isStuck); // @[BaseType.scala 299:24]
assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL; // @[Pipeline.scala 124:26]
assign when_Pipeline_l124_24 = (! memory_arbitration_isStuck); // @[BaseType.scala 299:24]
assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL; // @[Pipeline.scala 124:26]
assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL; // @[Pipeline.scala 110:25]
assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL; // @[Pipeline.scala 121:26]
assign when_Pipeline_l124_25 = (! execute_arbitration_isStuck); // @[BaseType.scala 299:24]
assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL; // @[Pipeline.scala 124:26]
assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Pipeline_l124_27 = (! memory_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Pipeline_l124_28 = (! writeBack_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Pipeline_l124_30 = (! execute_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Pipeline_l124_31 = (! execute_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Pipeline_l124_32 = (! execute_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Pipeline_l124_33 = (! execute_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Pipeline_l124_34 = (! execute_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Pipeline_l124_35 = (! memory_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Pipeline_l124_36 = (! writeBack_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Pipeline_l124_37 = (! memory_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Pipeline_l124_38 = (! writeBack_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Pipeline_l124_39 = (! memory_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Pipeline_l124_40 = (! memory_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Pipeline_l124_41 = (! memory_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Pipeline_l124_42 = (! memory_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Pipeline_l124_43 = (! memory_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Pipeline_l124_44 = (! memory_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Pipeline_l124_45 = (! memory_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Pipeline_l124_46 = (! writeBack_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Pipeline_l124_47 = (! writeBack_arbitration_isStuck); // @[BaseType.scala 299:24]
assign when_Pipeline_l124_48 = (! writeBack_arbitration_isStuck); // @[BaseType.scala 299:24]
assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); // @[Pipeline.scala 132:35]
assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); // @[Pipeline.scala 132:35]
assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); // @[Pipeline.scala 132:35]
assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); // @[Pipeline.scala 132:35]
assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); // @[Pipeline.scala 141:41]
assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); // @[Pipeline.scala 142:33]
assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); // @[Pipeline.scala 143:34]
assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); // @[Pipeline.scala 144:34]
assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); // @[Pipeline.scala 141:41]
assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); // @[Pipeline.scala 142:33]
assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); // @[Pipeline.scala 143:34]
assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); // @[Pipeline.scala 144:34]
assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); // @[Pipeline.scala 141:41]
assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); // @[Pipeline.scala 142:33]
assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); // @[Pipeline.scala 143:34]
assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); // @[Pipeline.scala 144:34]
assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); // @[Pipeline.scala 141:41]
assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); // @[Pipeline.scala 142:33]
assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); // @[Pipeline.scala 143:34]
assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); // @[Pipeline.scala 144:34]
assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); // @[BaseType.scala 305:24]
assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); // @[BaseType.scala 305:24]
assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); // @[BaseType.scala 305:24]
assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); // @[BaseType.scala 305:24]
assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt); // @[BaseType.scala 305:24]
assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); // @[BaseType.scala 305:24]
always @(posedge clk or posedge reset) begin
if(reset) begin
IBusSimplePlugin_fetchPc_pcReg <= 32'h0; // @[Data.scala 400:33]
IBusSimplePlugin_fetchPc_correctionReg <= 1'b0; // @[Data.scala 400:33]
IBusSimplePlugin_fetchPc_booted <= 1'b0; // @[Data.scala 400:33]
IBusSimplePlugin_fetchPc_inc <= 1'b0; // @[Data.scala 400:33]
_zz_IBusSimplePlugin_iBusRsp_stages_1_input_valid_1 <= 1'b0; // @[Data.scala 400:33]
_zz_IBusSimplePlugin_injector_decodeInput_valid <= 1'b0; // @[Data.scala 400:33]
IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; // @[Data.scala 400:33]
IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; // @[Data.scala 400:33]
IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; // @[Data.scala 400:33]
IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; // @[Data.scala 400:33]
IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; // @[Data.scala 400:33]
IBusSimplePlugin_pending_value <= 3'b000; // @[Data.scala 400:33]
IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= 3'b000; // @[Data.scala 400:33]
_zz_7 <= 1'b1; // @[Data.scala 400:33]
HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; // @[Data.scala 400:33]
execute_arbitration_isValid <= 1'b0; // @[Data.scala 400:33]
memory_arbitration_isValid <= 1'b0; // @[Data.scala 400:33]
writeBack_arbitration_isValid <= 1'b0; // @[Data.scala 400:33]
end else begin
if(IBusSimplePlugin_fetchPc_correction) begin
IBusSimplePlugin_fetchPc_correctionReg <= 1'b1; // @[Fetcher.scala 130:42]
end
if(IBusSimplePlugin_fetchPc_output_fire) begin
IBusSimplePlugin_fetchPc_correctionReg <= 1'b0; // @[Fetcher.scala 130:62]
end
IBusSimplePlugin_fetchPc_booted <= 1'b1; // @[Reg.scala 39:30]
if(when_Fetcher_l134) begin
IBusSimplePlugin_fetchPc_inc <= 1'b0; // @[Fetcher.scala 134:32]
end
if(IBusSimplePlugin_fetchPc_output_fire_1) begin
IBusSimplePlugin_fetchPc_inc <= 1'b1; // @[Fetcher.scala 134:72]
end
if(when_Fetcher_l134_1) begin
IBusSimplePlugin_fetchPc_inc <= 1'b0; // @[Fetcher.scala 134:93]
end
if(when_Fetcher_l161) begin
IBusSimplePlugin_fetchPc_pcReg <= IBusSimplePlugin_fetchPc_pc; // @[Fetcher.scala 162:15]
end
if(IBusSimplePlugin_iBusRsp_flush) begin
_zz_IBusSimplePlugin_iBusRsp_stages_1_input_valid_1 <= 1'b0; // @[Misc.scala 146:41]
end
if(_zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready) begin
_zz_IBusSimplePlugin_iBusRsp_stages_1_input_valid_1 <= (IBusSimplePlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); // @[Misc.scala 154:18]
end
if(decode_arbitration_removeIt) begin
_zz_IBusSimplePlugin_injector_decodeInput_valid <= 1'b0; // @[Misc.scala 146:41]
end
if(IBusSimplePlugin_iBusRsp_output_ready) begin
_zz_IBusSimplePlugin_injector_decodeInput_valid <= (IBusSimplePlugin_iBusRsp_output_valid && (! IBusSimplePlugin_externalFlush)); // @[Misc.scala 154:18]
end
if(IBusSimplePlugin_fetchPc_flushed) begin
IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; // @[Fetcher.scala 330:17]
end
if(when_Fetcher_l332) begin
IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b1; // @[Fetcher.scala 333:17]
end
if(IBusSimplePlugin_fetchPc_flushed) begin
IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; // @[Fetcher.scala 330:17]
end
if(when_Fetcher_l332_1) begin
IBusSimplePlugin_injector_nextPcCalc_valids_1 <= IBusSimplePlugin_injector_nextPcCalc_valids_0; // @[Fetcher.scala 333:17]
end
if(IBusSimplePlugin_fetchPc_flushed) begin
IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; // @[Fetcher.scala 336:17]
end
if(IBusSimplePlugin_fetchPc_flushed) begin
IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; // @[Fetcher.scala 330:17]
end
if(when_Fetcher_l332_2) begin
IBusSimplePlugin_injector_nextPcCalc_valids_2 <= IBusSimplePlugin_injector_nextPcCalc_valids_1; // @[Fetcher.scala 333:17]
end
if(IBusSimplePlugin_fetchPc_flushed) begin
IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; // @[Fetcher.scala 336:17]
end
if(IBusSimplePlugin_fetchPc_flushed) begin
IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; // @[Fetcher.scala 330:17]
end
if(when_Fetcher_l332_3) begin
IBusSimplePlugin_injector_nextPcCalc_valids_3 <= IBusSimplePlugin_injector_nextPcCalc_valids_2; // @[Fetcher.scala 333:17]
end
if(IBusSimplePlugin_fetchPc_flushed) begin
IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; // @[Fetcher.scala 336:17]
end
if(IBusSimplePlugin_fetchPc_flushed) begin
IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; // @[Fetcher.scala 330:17]
end
if(when_Fetcher_l332_4) begin
IBusSimplePlugin_injector_nextPcCalc_valids_4 <= IBusSimplePlugin_injector_nextPcCalc_valids_3; // @[Fetcher.scala 333:17]
end
if(IBusSimplePlugin_fetchPc_flushed) begin
IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; // @[Fetcher.scala 336:17]
end
IBusSimplePlugin_pending_value <= IBusSimplePlugin_pending_next; // @[IBusSimplePlugin.scala 295:15]
IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter - _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter); // @[IBusSimplePlugin.scala 357:26]
if(IBusSimplePlugin_iBusRsp_flush) begin
IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_pending_value - _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_2); // @[IBusSimplePlugin.scala 359:28]
end
_zz_7 <= 1'b0; // @[Reg.scala 39:30]
HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; // @[Reg.scala 39:30]
if(when_Pipeline_l151) begin
execute_arbitration_isValid <= 1'b0; // @[Pipeline.scala 152:35]
end
if(when_Pipeline_l154) begin
execute_arbitration_isValid <= decode_arbitration_isValid; // @[Pipeline.scala 155:35]
end
if(when_Pipeline_l151_1) begin
memory_arbitration_isValid <= 1'b0; // @[Pipeline.scala 152:35]
end
if(when_Pipeline_l154_1) begin
memory_arbitration_isValid <= execute_arbitration_isValid; // @[Pipeline.scala 155:35]
end
if(when_Pipeline_l151_2) begin
writeBack_arbitration_isValid <= 1'b0; // @[Pipeline.scala 152:35]
end
if(when_Pipeline_l154_2) begin
writeBack_arbitration_isValid <= memory_arbitration_isValid; // @[Pipeline.scala 155:35]
end
end
end
always @(posedge clk) begin
if(IBusSimplePlugin_iBusRsp_output_ready) begin
_zz_IBusSimplePlugin_injector_decodeInput_payload_pc <= IBusSimplePlugin_iBusRsp_output_payload_pc; // @[Misc.scala 155:15]
_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_error <= IBusSimplePlugin_iBusRsp_output_payload_rsp_error; // @[Misc.scala 155:15]
_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst <= IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; // @[Misc.scala 155:15]
_zz_IBusSimplePlugin_injector_decodeInput_payload_isRvc <= IBusSimplePlugin_iBusRsp_output_payload_isRvc; // @[Misc.scala 155:15]
end
if(IBusSimplePlugin_injector_decodeInput_ready) begin
IBusSimplePlugin_injector_formal_rawInDecode <= IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; // @[Utils.scala 1084:26]
end
HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; // @[Reg.scala 39:30]
HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; // @[Reg.scala 39:30]
if(when_Pipeline_l124) begin
decode_to_execute_PC <= _zz_decode_to_execute_PC; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_1) begin
execute_to_memory_PC <= execute_PC; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_2) begin
memory_to_writeBack_PC <= memory_PC; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_3) begin
decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_4) begin
execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_5) begin
memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_6) begin
decode_to_execute_FORMAL_PC_NEXT <= _zz_decode_to_execute_FORMAL_PC_NEXT; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_7) begin
execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_8) begin
decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_9) begin
decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_10) begin
execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_11) begin
memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_12) begin
decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_13) begin
execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_14) begin
memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_15) begin
decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_16) begin
decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_17) begin
execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_18) begin
decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_19) begin
execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_20) begin
decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_21) begin
decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_22) begin
decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_23) begin
decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_24) begin
execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_25) begin
decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_26) begin
decode_to_execute_IS_MUL <= decode_IS_MUL; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_27) begin
execute_to_memory_IS_MUL <= execute_IS_MUL; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_28) begin
memory_to_writeBack_IS_MUL <= memory_IS_MUL; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_29) begin
decode_to_execute_RS1 <= _zz_decode_to_execute_RS1; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_30) begin
decode_to_execute_RS2 <= _zz_decode_to_execute_RS2; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_31) begin
decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_32) begin
decode_to_execute_SRC1 <= decode_SRC1; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_33) begin
decode_to_execute_SRC2 <= decode_SRC2; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_34) begin
decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_35) begin
execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_36) begin
memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_37) begin
execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_38) begin
memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2_1; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_39) begin
execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_40) begin
execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_41) begin
execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_42) begin
execute_to_memory_MUL_LL <= execute_MUL_LL; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_43) begin
execute_to_memory_MUL_LH <= execute_MUL_LH; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_44) begin
execute_to_memory_MUL_HL <= execute_MUL_HL; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_45) begin
execute_to_memory_MUL_HH <= execute_MUL_HH; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_46) begin
memory_to_writeBack_MUL_HH <= memory_MUL_HH; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_47) begin
memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; // @[Pipeline.scala 124:40]
end
if(when_Pipeline_l124_48) begin
memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; // @[Pipeline.scala 124:40]
end
end
endmodule
module StreamFifoLowLatency (
input io_push_valid,
output io_push_ready,
input io_push_payload_error,
input [31:0] io_push_payload_inst,
output reg io_pop_valid,
input io_pop_ready,
output reg io_pop_payload_error,
output reg [31:0] io_pop_payload_inst,
input io_flush,
output [0:0] io_occupancy,
input clk,
input reset
);
reg when_Phase_l648;
reg pushPtr_willIncrement;
reg pushPtr_willClear;
wire pushPtr_willOverflowIfInc;
wire pushPtr_willOverflow;
reg popPtr_willIncrement;
reg popPtr_willClear;
wire popPtr_willOverflowIfInc;
wire popPtr_willOverflow;
wire ptrMatch;
reg risingOccupancy;
wire empty;
wire full;
wire pushing;
wire popping;
wire readed_error;
wire [31:0] readed_inst;
wire [32:0] _zz_readed_error;
wire when_Stream_l1196;
wire when_Stream_l1209;
wire [32:0] _zz_readed_error_1;
reg [32:0] _zz_readed_error_2;
always @(*) begin
when_Phase_l648 = 1'b0; // @[when.scala 47:16]
if(pushing) begin
when_Phase_l648 = 1'b1; // @[when.scala 52:10]
end
end
always @(*) begin
pushPtr_willIncrement = 1'b0; // @[Utils.scala 536:23]
if(pushing) begin
pushPtr_willIncrement = 1'b1; // @[Utils.scala 540:41]
end
end
always @(*) begin
pushPtr_willClear = 1'b0; // @[Utils.scala 537:19]
if(io_flush) begin
pushPtr_willClear = 1'b1; // @[Utils.scala 539:33]
end
end
assign pushPtr_willOverflowIfInc = 1'b1; // @[BaseType.scala 305:24]
assign pushPtr_willOverflow = (pushPtr_willOverflowIfInc && pushPtr_willIncrement); // @[BaseType.scala 305:24]
always @(*) begin
popPtr_willIncrement = 1'b0; // @[Utils.scala 536:23]
if(popping) begin
popPtr_willIncrement = 1'b1; // @[Utils.scala 540:41]
end
end
always @(*) begin
popPtr_willClear = 1'b0; // @[Utils.scala 537:19]
if(io_flush) begin
popPtr_willClear = 1'b1; // @[Utils.scala 539:33]
end
end
assign popPtr_willOverflowIfInc = 1'b1; // @[BaseType.scala 305:24]
assign popPtr_willOverflow = (popPtr_willOverflowIfInc && popPtr_willIncrement); // @[BaseType.scala 305:24]
assign ptrMatch = 1'b1; // @[BaseType.scala 305:24]
assign empty = (ptrMatch && (! risingOccupancy)); // @[BaseType.scala 305:24]
assign full = (ptrMatch && risingOccupancy); // @[BaseType.scala 305:24]
assign pushing = (io_push_valid && io_push_ready); // @[BaseType.scala 305:24]
assign popping = (io_pop_valid && io_pop_ready); // @[BaseType.scala 305:24]
assign io_push_ready = (! full); // @[Stream.scala 1190:17]
assign _zz_readed_error = _zz_readed_error_1; // @[Mem.scala 285:24]
assign readed_error = _zz_readed_error[0]; // @[Bool.scala 189:10]
assign readed_inst = _zz_readed_error[32 : 1]; // @[Bits.scala 133:56]
assign when_Stream_l1196 = (! empty); // @[BaseType.scala 299:24]
always @(*) begin
if(when_Stream_l1196) begin
io_pop_valid = 1'b1; // @[Stream.scala 1197:22]
end else begin
io_pop_valid = io_push_valid; // @[Stream.scala 1200:22]
end
end
always @(*) begin
if(when_Stream_l1196) begin
io_pop_payload_error = readed_error; // @[Stream.scala 1198:24]
end else begin
io_pop_payload_error = io_push_payload_error; // @[Stream.scala 1201:24]
end
end
always @(*) begin
if(when_Stream_l1196) begin
io_pop_payload_inst = readed_inst; // @[Stream.scala 1198:24]
end else begin
io_pop_payload_inst = io_push_payload_inst; // @[Stream.scala 1201:24]
end
end
assign when_Stream_l1209 = (pushing != popping); // @[BaseType.scala 305:24]
assign io_occupancy = (risingOccupancy && ptrMatch); // @[Stream.scala 1225:18]
assign _zz_readed_error_1 = _zz_readed_error_2; // @[Phase.scala 647:23]
always @(posedge clk or posedge reset) begin
if(reset) begin
risingOccupancy <= 1'b0; // @[Data.scala 400:33]
end else begin
if(when_Stream_l1209) begin
risingOccupancy <= pushing; // @[Stream.scala 1210:21]
end
if(io_flush) begin
risingOccupancy <= 1'b0; // @[Stream.scala 1237:21]
end
end
end
always @(posedge clk) begin
if(when_Phase_l648) begin
_zz_readed_error_2 <= {io_push_payload_inst,io_push_payload_error}; // @[Phase.scala 650:27]
end
end
endmodule
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