40 lines
700 B
Verilog
40 lines
700 B
Verilog
/*
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* xclk_pulse.v
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*
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* vim: ts=4 sw=4
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*
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* Helper to cross a pulse from one clock domain to another
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*
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* Copyright (C) 2023 Sylvain Munaut <tnt@246tNt.com>
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* SPDX-License-Identifier: CERN-OHL-P-2.0
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*/
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`default_nettype none
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module xclk_pulse (
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input wire i_stb,
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input wire i_clk,
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output wire o_stb,
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input wire o_clk,
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input wire rst
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);
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reg i_toggle;
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reg [2:0] o_sync;
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always @(posedge i_clk or posedge rst)
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if (rst)
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i_toggle <= 1'b0;
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else
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i_toggle <= i_toggle ^ i_stb;
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always @(posedge o_clk or posedge rst)
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if (rst)
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o_sync <= 3'b000;
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else
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o_sync <= { o_sync[1] ^ o_sync[0], o_sync[0], i_toggle };
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assign o_stb = o_sync[2];
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endmodule // xclk_pulse
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