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gateware: Switch clk_sys to 12 MHz 

This actually helps save a bit of power (at least for sysmgr_3) since
the "always-on" clk_base is slower.

The SoC needs more time to compute frames, but the same number of
cycles so that doesn't change the power on clk_sys itself really.

This will also be helpful for upcoming commits where we switch to
a Vex that has better IPC but doesn't easily meet 24 MHz constraint.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
This commit is contained in:
Sylvain Munaut 2023-03-22 21:54:35 +01:00
parent 119bc9fa1f
commit 2188b231be
4 changed files with 13 additions and 13 deletions
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2
gateware/data/clocks.py
View File

@ -1,4 +1,4 @@
ctx.addClock("clk_led", 6)
ctx.addClock("clk_sys", 24)
ctx.addClock("clk_sys", 12)
ctx.addClock("clk_usb", 48)
ctx.addClock("pmu_I.btn_clk", 20) # Just to avoid screwing the histogram

4
gateware/rtl/sysmgr_1.v
View File

@ -114,9 +114,9 @@ module sysmgr (
always @(posedge clk_base)
clk_usb_i <= clk_div[0] & ~usb_off;
// SYS is div-by-4 + gated
// SYS is div-by-8 + gated
always @(posedge clk_base)
clk_sys_i <= clk_div[1] & ~sys_off;
clk_sys_i <= clk_div[2] & ~sys_off;
// LED is div-by-16
assign clk_led_i = clk_div[3];

8
gateware/rtl/sysmgr_2.v
View File

@ -38,7 +38,7 @@ module sysmgr (
wire pll_lock;
reg [2:0] clk_div;
reg [1:0] clk_div;
reg clk_sys_i;
wire clk_led_i;
@ -84,7 +84,7 @@ module sysmgr (
.DELAY_ADJUSTMENT_MODE_FEEDBACK ("FIXED"),
.FDA_FEEDBACK (4'b0000),
.SHIFTREG_DIV_MODE (2'b00),
.PLLOUT_SELECT_PORTA ("GENCLK"),
.PLLOUT_SELECT_PORTA ("GENCLK_HALF"),
.PLLOUT_SELECT_PORTB ("GENCLK"),
.ENABLE_ICEGATE_PORTA (1'b0),
.ENABLE_ICEGATE_PORTB (1'b1),
@ -117,8 +117,8 @@ module sysmgr (
always @(posedge clk_base)
clk_sys_i <= clk_div[0] & ~sys_off;
// LED is div-by-8
assign clk_led_i = clk_div[2];
// LED is div-by-4
assign clk_led_i = clk_div[1];
// Global buffers
SB_GB clk_sys_gbuf_I (

12
gateware/rtl/sysmgr_3.v
View File

@ -37,7 +37,7 @@ module sysmgr (
wire pll_lock;
reg [2:0] clk_div;
reg [1:0] clk_div;
reg clk_sys_i;
wire clk_led_i;
@ -60,11 +60,11 @@ module sysmgr (
// SB_HFOSC
// -------
// Generates 48 MHz
// Generates 24 MHz
(* ROUTE_THROUGH_FABRIC = 1 *)
SB_HFOSC #(
.CLKHF_DIV("0b00")
.CLKHF_DIV("0b01")
) osc_I (
.CLKHFPU(1'b1),
.CLKHFEN(1'b1),
@ -87,7 +87,7 @@ module sysmgr (
.PLLOUT_SELECT ("GENCLK"),
.ENABLE_ICEGATE (1'b0)
) pll_I (
.REFERENCECLK (clk_div[1]),
.REFERENCECLK (clk_div[0]),
.PLLOUTCORE (),
.PLLOUTGLOBAL (clk_usb),
.EXTFEEDBACK (1'b0),
@ -113,8 +113,8 @@ module sysmgr (
always @(posedge clk_base)
clk_sys_i <= clk_div[0] & ~sys_off;
// LED is div-by-8
assign clk_led_i = clk_div[2];
// LED is div-by-4
assign clk_led_i = clk_div[1];
// Global buffers
SB_GB clk_sys_gbuf_I (