This was broken when moving the design to non-hacked multi channel
E1.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Change-Id: I5e7ce22935609bc64333e2d5c310eb7493555a93
This was never used and doesn't really belong here, this was just
an example descriptor in the original firmware this is based on.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Change-Id: Ic72c991eb7a566b227484c7cde2c305d58202219
This is a remanence of old firmware of the icepick on which that
design is based on.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Change-Id: I0bc27da4faa91de983cd5f355553ecaa13754266
Tests with prototypes have shown that above the RJ45 jack, there is a
0.95mm gap, and towards both sides there's a total of 0.7mm. Let's
reduce that to 0.15mm on top and 0.10mm on either side.
Change-Id: I13b097a76cd9ce96a64ed6fec956d7c918c613f9
Without theses there are too many control-sets generated by yosys and
nextpnr can't find any valid placement.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
By default build full bitstream, but from env or cli, allow to only
enable RX/TX units in channel 0 to speedup dev / testing.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
The hard IP kind of sucks ... but we don't need i2c much (or at
all really) and using the hard IP is nearly free (LC-wise).
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
We have a bunch of Multiply Add units that are un-used, we can
make use of the "accumulate" part to implement the few wide
counters we have to win some LCs.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Theses syntax error are ignored by yosys but trying synopsys, it is more
strict, so fix them. Right thing to do anyway ...
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Also default build to it since very few people would want to build
firmware targetted to the prototypes ...
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Current version has second E1 channel disabled to allow the
build to works. Works is in progress to optimize the gateware and
the fpga toolchain to allow full featured build.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
The documentation always had the rRX tick in the LSB which
is consistent with having the RX units before TX.
They can be read as 16 bit value anyway so there isn't any
performance impact.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Some more code could probably be unified with the "normal" usb E1 adapter
to both reduce code duplication but also offer 'sniff' function to the
E1 adapter.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Currently only the icE1usb-proto is supported. Adaptation for the
final production hardware is yet to be done.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
This is the project specific to the e1-tracer board that was
initially based on the iCEpick with a couple dev boards attached
but eventually consolidated to a proper board, which still retaining
100% electrical compatibility (and thus same gateware and firmware)
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
This is the project specific to the PMOD based early prototype.
It was used either with the icebreaker or the icebreaker-bitsy
board as host. Set BOARD variable appropriately during build.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Harald Welte
Sylvain Munaut
Joachim Steiger
Martin Schramm