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osmo-e1-hardware
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gateware: Minor syntax fixes 

Theses syntax error are ignored by yosys but trying synopsys, it is more
strict, so fix them. Right thing to do anyway ...

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
This commit is contained in:
Sylvain Munaut 2020-09-22 20:00:13 +02:00
parent 5e86047024
commit 7b228843ae
5 changed files with 9 additions and 9 deletions
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2
gateware/common/rtl/soc_base.v
View File

@ -261,7 +261,7 @@ module soc_base #(
// Boot memory - 1k
soc_bram #(
.AW(8),
.INIT_FILE("boot.hex"),
.INIT_FILE("boot.hex")
) bram_I (
.addr (bram_addr),
.rdata(bram_rdata),

2
gateware/e1-tracer/rtl/sysmgr.v
View File

@ -37,7 +37,7 @@ module sysmgr (
.PIN_TYPE(6'b000001)
) gb_in (
.PACKAGE_PIN(clk_in),
.GLOBAL_BUFFER_OUTPUT(clk_12m_i),
.GLOBAL_BUFFER_OUTPUT(clk_12m_i)
);
// PLL instance

6
gateware/icE1usb-proto/rtl/sysmgr.v
View File

@ -33,10 +33,10 @@ module sysmgr (
// Global input buffer for 30.72 MHz clock
SB_GB_IO #(
.PIN_TYPE(6'b000001),
.PIN_TYPE(6'b000001)
) gb_in (
.PACKAGE_PIN(clk_in),
.GLOBAL_BUFFER_OUTPUT(clk_30m72_i),
.GLOBAL_BUFFER_OUTPUT(clk_30m72_i)
);
// PLL instance
@ -50,7 +50,7 @@ module sysmgr (
.FDA_FEEDBACK(4'b0000),
.SHIFTREG_DIV_MODE(2'b00),
.PLLOUT_SELECT("GENCLK"),
.ENABLE_ICEGATE(1'b0),
.ENABLE_ICEGATE(1'b0)
) pll_I (
.REFERENCECLK(clk_30m72_i),
.PLLOUTCORE(),

2
gateware/icE1usb/rtl/led_blinker.v
View File

@ -75,7 +75,7 @@ module led_blinker (
// Per-led
always @(*)
begin : led_state
begin : led_state_proc
integer i;
for (i=0; i<4; i=i+1)
led[i] = led_state[2*i+1] ? (led_state[2*i] ? blink_fast : blink_slow) : led_state[2*i];

6
gateware/icE1usb/rtl/sysmgr.v
View File

@ -33,10 +33,10 @@ module sysmgr (
// Global input buffer for 30.72 MHz clock
SB_GB_IO #(
.PIN_TYPE(6'b000001),
.PIN_TYPE(6'b000001)
) gb_in (
.PACKAGE_PIN(clk_in),
.GLOBAL_BUFFER_OUTPUT(clk_30m72_i),
.GLOBAL_BUFFER_OUTPUT(clk_30m72_i)
);
// PLL instance
@ -50,7 +50,7 @@ module sysmgr (
.FDA_FEEDBACK(4'b0000),
.SHIFTREG_DIV_MODE(2'b00),
.PLLOUT_SELECT("GENCLK"),
.ENABLE_ICEGATE(1'b0),
.ENABLE_ICEGATE(1'b0)
) pll_I (
.REFERENCECLK(clk_30m72_i),
.PLLOUTCORE(),