E1 related hardware projects (osmo-e1-tap, osmo-e1-xcvr, osmo-e1-tracer)
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Sylvain Munaut c756644205 gateware: no_rw_check fixes to cope with new yosys BRAM inferrence 1 day ago
contrib jenkins.sh: Fix upload of tagged releases 9 months ago
doc Doc Update - Build process for DAHDI on Debian 11 5 months ago
firmware/ice40-riscv icE1usb fw: Limit dfuprog to proper USB IDs 1 day ago
flashing add flash scripts to flash e1_tracer via https://github.com/dword1511/stm32-vserprog.git and dfu-util 2 years ago
gateware gateware: no_rw_check fixes to cope with new yosys BRAM inferrence 1 day ago
hardware hardware/icE1usb-rs422: Add missing gitignore 3 weeks ago
mechanical mechanical/icE1usb-case: Update ECN with 1st production run infos 2 years ago
software osmo_e1f: Allow to transmit AIS 2 years ago
.checkpatch.conf checkpatch.conf: new file 9 months ago
.gitattributes Add .gitattribute to make sure pdf are treated as binary 2 years ago
.gitignore gitignore: add files from generating manuals 2 years ago
.gitmodules gateware: Initial import of all common parts 2 years ago
README Change name of repository in README 2 years ago

README

osmo-e1-hardware - Collection of various E1/TDM hardware projects
======================================================================

This repository hosts three different sub-projects:

* osmo-e1-xcvr (E1 LIU + magnetics)
https://osmocom.org/projects/e1-t1-adapter/wiki/Osmo-e1-xcvr
* osmo-e1-tracer (fully integrated passive raw bitstream tracer)
https://osmocom.org/projects/e1-t1-adapter/wiki/E1_tracer
* osmo-e1-tap (passive high-impedance tap)

== osmo-e1-xcvr ==

This is a simple hardware project that aims to generate a reusable module
for interfacing E1/T1/J1 lines from various custom FPGA/CPLD/microcontroller
projects.

The board contains tranformers, the analog circuitry, the LIU (line interface
unit), an oscillator as well as an integrated transceiver chip.

It exposes the control interface (SPI) as well as the decoded synchronous
Rx/Tx bitstreams each on a 2x5pin header.

Framer, Multiplexe,r HDLC decoder or anything like that is out-of-scope for
now. The idea relaly is to provide an interface as low-level as possible.

One of the ideas is to create a "soft E1" interface, where the Rx/Tx bitstreams
are interfaced with the SSC of an AT91SAM3S and subsequently passed into a PC
via USB. The 2Mbps signal is very low-bandwidth, so that a pure software
implementation should be absolutely no problem for todays computing power.

See https://osmocom.org/projects/e1-t1-adapter/wiki/Osmo-e1-xcvr for more details


== osmo-e1-tap ==

This is a small passive board that allows you to perform high-impedance tracing on an E1
or T1 line.


== osmo-e1-tracer ==

This is a fully integrated design that allows you to obtainm bi-directional high-impedance
bitstream E1 traces. It features an iCE40 FPGA with USB + E1 cores from Sylvain Munaut,
as well as two E1 LIUs.

See https://osmocom.org/projects/e1-t1-adapter/wiki/E1_tracer for more details.