It's not used anywhere, and if this sort of api becomes needed, it can be
designed cleanly and finished.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
This is more in line with the actual hardware (u32 registers), and will still
work if PRIMASK or FAULTMASK ever have more than 1 bit defined.
The functions cm_is_masked_interrupts() and cm_is_masked_faults() are
unchanged, since returning 'bool' fits with the function naming.
Fixes most of github issue #475. What remains "unfixed" is the absence
of functions to simply 'get' the u32 value of PRIMASK and FAULTMASK registers.
The MPU RASR AP table has a duplicate entries for Privileged ReadOnly
and Usermode ReadOnly, in the source ARM document (Cortex M3 TRM)
Remove the duplicate here.
The MPU RASR Shareable, Bufferable and Cacheable bits are all individual
bits, and none of the existing defines appear to even match the ARM
documentation. Remove them, but leave the definitions of the bit
positions.
Reported by MightyPork on IRC
Original commits, while appearing clean and tidy, hadn't even been
compile tested. Trust no-one. Not even Scully.
Fixes: 770878e7b4
Fixes: 86d20ef00c
Fixes: 05ff0df322
This adds the "volatile" keyword to all the inline assembly. gcc docs say "You can prevent an asm instruction from being deleted by writing the keyword volatile after the asm.". Testing (see comments of github issue #475) shows that indeed gcc can remove some inline asm, in at least this situation:
-multiple calls to cm_is_masked_interrupts() in the same scope/context
- -Os or -O2 optimization
This is problem because the value of PRIMASK could change between two calls to cm_is_masked_interrupts().
Adding the volatile keyword fixes this, and probably costs less than adding a full barrier (like adding "memory" to the clobber list).
As done by esden for the F4, remove typedefs and add prefixes to clock enums
This extends this to all stm32 families.
Let's not hide the fact that these variables are structs/enums.
We are filling up the namespace badly enough, we should be prefixing as
much as we can with the module names at least. As users we already run
often enough in namespace colisions we don't have to make it worse.
* CLOCK_3V3_xxx enums renamed to RCC_CLOCK_3V3_xxx
* clock enums (PLL, HSI, HSE ...) prefixed with RCC_
* scale enum of pwr module prefixed with PWR_
Let's not hide the fact that these variables are structs/enums.
We are filling up the namespace badly enough, we should be prefixing as
much as we can with the module names at least. As users we already run
often enough in namespace colisions we don't have to make it worse.
* CLOCK_3V3_xxx enums renamed to RCC_CLOCK_3V3_xxx
* clock enums (PLL, HSI, HSE ...) prefixed with RCC_
* scale enum of pwr module prefixed with PWR_
These prototypes affect functions defined by application code. Only
the implementations in libopencm3 are supposed to be weak; the
functions in application code should definitely not be. Otherwise,
you'll end up with two weak symbols being linked together, and
it's luck as to which one the linker picks.
Just the basic core common functionality gained for free by being a common
peripheral. Enough for a miniblink.
Fixes some errors in the GPIO memory map. ST's naming of AHB2 vs AHB3 is
confusing.
Values from RM0351rev1, with the correction of the duplicate TIM1_CC entry.
Only stub support so far, but this opens up the beginning of build testing.
Many stm32 families have multiple ADC and DAC peripherals. F0 (so far) only
has one. To make it easier to use the same code on many stm32 families,
provide an alias for ADC1 to ADC.
After adding support to the f3, add missing doxygen support to the f0
equivalent. This improves things and keeps them consistent until/if they are
pulled out as common code.
Based on the f0 support, which has identical functionality, but with doxygen
added. Bits renamed as they are only HSE prediv on some targets, and makes
things more consistent with the f0.
Fixes part of github issue #560
This function was badly copied and pasted from the f4 library, where there are
two functions, rcc_set_main_pll_hsi and rcc_set_main_pll_hse which combine
source, multipliers, dividers and other pll factors.
On F3, (not all of them, but the ones we support now), the function as
implemented has nothing to do with hsi / hse, and instead is simply selecting
the PLL multiplier.
Copypasta from f4 rcc code was only modified to shift the result, but not clear
the existing settings properly. Add mask/shift definitions and use them
properly.
TSC_IOGxCR is actually a 32 bit register, of which 13 bits are used
(rest are reserved).
Also, added x-1 since G0 is not a valid group, TSC_IOGCSR_GxE(1) is supposed
to be at 0x34, not 0x38.
Was only in the (obviously out of date) documented example and as a
declaration. No implementations. Dropping immediately, but documentation
still needs further work.
Most changes are noise from doxygen.
Readme udpated to explain newer FP_FLAGS for m7
stm32f7 library is skipped if the toolchain doesn't support it yet.
GUSBCFG TRDT fields have very particular meanings, and the field should be set
depending on your bus speed. There's no 8/16bit meaning in any current
reference manual for this field.
Fixes github issue #530
All the macro arguments that are user supplied, or potentially, wrap properly
in () as good practice.
Probably missed one or two, and a lot of them are possibly unnecessary, but
it's straightforward to just do it always.
Fixes github issue #321
More could probably be found, but this makes some of the basic RCC defines for
the L0 much more inline with other platforms, and much less verbose. This
helps us have more identical code for library users across different targets.
Based on previous work, add a new driver for the v2 usb peripheral found on
stm32f0 and l0 devices.
Correspondingly, add a usb gadget zero test suite for the f0. L0 device level
code isn't yet ready, but will add the test case when it moves in.
Work by Frantisek Burian, Kuldeep
Singh Dhaka, Robin Kreis, fenugrec and zyp on irc, and all those forgotten.
The breaking changes here changes in header location, and changes in driver
name passed down to the usb stack.
Changes affect: stm32f102/f103, stm32l1, and some f3 parts
* instead of the confusingly generic "usb" use the name "st_usbfs" for the USB
Full speed peripheral ST provides in a variety of their stm32 products.
Include directives should change as:
#include <libopencm3/stm32/usb.h> => <libopencm3/stm32/st_usbfs.h>
* instead of the confusingly specific "f103" name for the driver, use
"st_usbfs_v1" [BREAKING_CHANGE]
Instead of:
usbd_init(&stm32f103_usb_driver, .....) ==>
usbd_init(&st_usbfs_v1_usb_driver, .....) ==>
The purpose of these changes is to reduce some confusion around naming, but
primarily to prepare for the "v2" peripheral available on stm32f0/l0 and some
f3 devices.
Work by Frantisek Burian, Kuldeep Singh Dhaka, Robin Kreis, fenugrec and zyp
on irc, and all those forgotten.
* USB host register definitions added.
* Extracted common register and bitfield definitions
from 'otg_fs.h' and 'otg_hs.h'
into new file 'otg_common.h'.
Modified usb low-level drivers to adopt to new style of bitfields.
* Fixed typo OTG_GOTGIN -> OTG_GOTGINT (according to the datasheet)
Signed-off-by: Amir Hammad <amir.hammad@hotmail.com>
The MPU is an implementation option available for both ARMv6-M and ARMv7-M.
Remove poorly merged code that attempted to include this only for cortex m0+.
Added doxygen, updated the definitions of the RBAR register, (though if you're
really using this periperhal, you should be looking at the ref man for further
information)
Reported-by: forrestv on irc.
All STM32 family pwr.h must use LIBOPENCM3_PWR_H as include guard so that
pwr_common.h can detect that it has been referenced by pwr.h for
each family. F2 and F3 had the wrong include guard.
Fixes Github issue #513
This removes the shift from the defines, and includes them in the helper
function, making the code match the documentation, and following how the
rest of the library commonly operates.
Code using the existing defines will continue to work.
Basic helpers to at least support common configurations for the f401.
Original submission specified 5 wait states, but the reference manual and other
reviewers all believe that 2ws is sufficient for these modes.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
This makes it easier to read for most people, and makes it substantially
easier to review changes in the function signatures themselves at a
later date.
The f3 adc has separate bits for end of conversion and end of sequence.
Support those fully, with the regular enable/disable irq methods, and
the flag checking methods.
Discovered in github bug: #493
This code was copied from the f4, and blindly modified to make it seem
to work. The f3 has separate flags for EOC and EOS, it doesn't use a
second bit to configure what the EOC bit does.
Consequently, update the documentation to correctly indicate that the
EOC bits are only set per conversion.
Discovered in github bug: #493
While there might be other places that are missing this include, this
particular file is clearly missing them, and has resulted in a few separate bug
reports. Fix it right now, in the name of continuous improvement.
Fixes#310 and #427
This adds MCO source selection to some targets, and removes and standardizes
the mask/shift usage for all targets. For devices that support MCO2, this
supports only MCO1. No attempt has been made to extract MCO prescaler, which
is not available on all F1 and F3.
This commit implements the support for one interface to have multiple
altsettings. It also adds hook that user can use to perform actions
when the alsetting switch is performed by host.
Changes:
* For backward compatibility, placed a pointer instead of allocating memory for whole interface struct.
* Always execute callback (even if the current interface alternate-settings matches).
* Multiple configuration support.
Signed-off-by: Kuldeep Singh Dhaka <kuldeepdhaka9@gmail.com>
Anatol Pomozov