[sam3] add basic pmc support
some peripheral ID definitions already added in periph.h were removed
This commit is contained in:
Felix Held
Karl Palsson
parent
6d69cbf98f
commit
8a24685d0c
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Gareth McMullin <gareth@blacksphere.co.nz>
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* Copyright (C) 2015 Felix Held <felix-libopencm3@felixheld.de>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_PMC_H
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#define LIBOPENCM3_PMC_H
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#include <libopencm3/sam/memorymap.h>
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#include <libopencm3/sam/common/pmc_common_all.h>
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#include <libopencm3/sam/common/pmc_common_3a3s3x.h>
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#include <libopencm3/sam/common/pmc_common_3a3u3x.h>
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/* --- Power Management Controller (PMC) registers ------------------------- */
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/* Peripheral Control Register */
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#define PMC_PCR MMIO32(PMC_BASE + 0x010C)
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/* --- Register contents --------------------------------------------------- */
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/* --- PMC Master Clock Register (PMC_MCKR) -------------------------------- */
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/* PLLA Divide by 2 */
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#define PMC_MCKR_PLLADIV2 (0x01 << 12)
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/* --- PMC Peripheral Control Register (PMC_PCR) --------------------------- */
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/* Enable */
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#define PMC_PCR_EN (0x01 << 28)
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/* Divisor Value */
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#define PMC_PCR_DIV_SHIFT 16
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#define PMC_PCR_DIV_MASK (0x03 << PMC_PCR_DIV_SHIFT)
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#define PMC_PCR_DIV_PERIPH_DIV_MCK (0x00 << PMC_PCR_DIV_SHIFT)
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#define PMC_PCR_DIV_PERIPH_DIV2_MCK (0x01 << PMC_PCR_DIV_SHIFT)
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#define PMC_PCR_DIV_PERIPH_DIV4_MCK (0x02 << PMC_PCR_DIV_SHIFT)
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/* Command */
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#define PMC_PCR_CMD (0x01 << 12)
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/* Peripheral ID */
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#define PMC_PCR_PID_SHIFT 0
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#define PMC_PCR_PID_MASK (0x3F << PMC_PCR_PID_SHIFT)
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#endif
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@ -0,0 +1,139 @@
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2015 Felix Held <felix-libopencm3@felixheld.de>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
|
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_PMC_H
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#define LIBOPENCM3_PMC_H
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#include <libopencm3/sam/memorymap.h>
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#include <libopencm3/sam/common/pmc_common_all.h>
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#include <libopencm3/sam/common/pmc_common_3n3u.h>
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/* --- Power Management Controller (PMC) registers ----------------------- */
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/* PMC Clock Generator PLL Register */
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#define CKGR_PLLR CKGR_PLLAR
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/* Oscillator Calibration Register */
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#define PMC_OCR MMIO32(PMC_BASE + 0x0110)
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/* --- Register contents --------------------------------------------------- */
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/* --- PMC Clock Generator Main Oscillator Register (CKGR_MOR) ------------- */
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/* Wait Mode Command */
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#define CKGR_MOR_WAITMODE (0x01 << 2)
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/* --- PMC Clock Generator PLL Register (CKGR_PLLR) ---------------------- */
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/* CKGR_PLLAR on all other device subfamilies */
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/* must be set to program CKGR_PLLR */
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#define CKGR_PLLR_ONE CKGR_PLLAR_ONE
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/* PLLA Multiplier */
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#define CKGR_PLLR_MUL_SHIFT CKGR_PLLAR_MULA_SHIFT
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#define CKGR_PLLR_MUL_MASK CKGR_PLLAR_MULA_MASK
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/* PLLA Counter */
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#define CKGR_PLLR_PLLCOUNT_SHIFT CKGR_PLLAR_PLLACOUNT_SHIFT
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#define CKGR_PLLR_PLLCOUNT_MASK CKGR_PLLAR_PLLACOUNT_MASK
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/* Divider */
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#define CKGR_PLLR_DIV_SHIFT CKGR_PLLAR_DIVA_SHIFT
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#define CKGR_PLLR_DIV_MASK CKGR_PLLAR_DIVA_MASK
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/* --- PMC Master Clock Register (PMC_MCKR) -------------------------------- */
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/* PLL Divide by 2 */
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#define PMC_MCKR_PLLDIV2 (0x01 << 12)
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/* Master Clock Source Selection */
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#define PMC_MCKR_CSS_PLL_CLK (2 << PMC_MCKR_CSS_SHIFT)
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/* --- PMC Programmable Clock Register 0 (PMC_PCK0) ------------------------ */
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/* Master Clock Source Selection */
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#define PMC_PCK0_CSS_PLL_CLK (2 << PMC_PCK0_CSS_SHIFT)
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/* --- PMC Programmable Clock Register 1 (PMC_PCK1) ------------------------ */
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/* Master Clock Source Selection */
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#define PMC_PCK1_CSS_PLL_CLK (2 << PMC_PCK1_CSS_SHIFT)
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/* --- PMC Programmable Clock Register 2 (PMC_PCK2) ------------------------ */
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/* Master Clock Source Selection */
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#define PMC_PCK2_CSS_PLL_CLK (2 << PMC_PCK2_CSS_SHIFT)
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/* --- PMC Interrupt Enable Register (PMC_IER) ----------------------------- */
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/* PLL Lock Interrupt Enable */
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#define PMC_IER_LOCK PMC_IER_LOCKA
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/* --- PMC Interrupt Disable Register (PMC_IDR) ----------------------------- */
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/* PLL Lock Interrupt Disable */
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#define PMC_IDR_LOCK PMC_IDR_LOCKA
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/* --- PMC Status Register (PMC_SR) ---------------------------------------- */
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/* PLL Lock Status */
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#define PMC_SR_LOCK PMC_SR_LOCKA
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/* --- PMC Interrupt Mask Register (PMC_IMR) ----------------------------- */
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/* PLL Lock Interrupt Mask */
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#define PMC_IMR_LOCK PMC_IMR_LOCKA
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/* --- PMC Oscillator Calibration Register (PMC_OCR) ----------------------- */
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/* Selection of RC Oscillator Calibration bits for 12 Mhz */
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#define PMC_OCR_SEL12 (0x01 << 23)
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/* RC Oscillator Calibration bits for 12 Mhz */
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#define PMC_OCR_CAL12_SHIFT 16
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#define PMC_OCR_CAL12_MASK (0x7F << PMC_OCR_CAL12_SHIFT)
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/* Selection of RC Oscillator Calibration bits for 8 Mhz */
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#define PMC_OCR_SEL8 (0x01 << 15)
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/* RC Oscillator Calibration bits for 8 Mhz */
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#define PMC_OCR_CAL8_SHIFT 8
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#define PMC_OCR_CAL8_MASK (0x7F << PMC_OCR_CAL8_SHIFT)
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/* Selection of RC Oscillator Calibration bits for 4 Mhz */
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#define PMC_OCR_SEL4 (0x01 << 7)
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/* RC Oscillator Calibration bits for 4 Mhz */
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#define PMC_OCR_CAL4_SHIFT 0
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#define PMC_OCR_CAL4_MASK (0x7F << PMC_OCR_CAL12_SHIFT)
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#endif
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@ -0,0 +1,138 @@
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2015 Felix Held <felix-libopencm3@felixheld.de>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
|
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* the Free Software Foundation, either version 3 of the License, or
|
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_PMC_H
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#define LIBOPENCM3_PMC_H
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#include <libopencm3/sam/memorymap.h>
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#include <libopencm3/sam/common/pmc_common_all.h>
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#include <libopencm3/sam/common/pmc_common_3a3s3x.h>
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/* --- Power Management Controller (PMC) registers ----------------------- */
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/* PLLB Register */
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#define CKGR_PLLBR MMIO32(PMC_BASE + 0x002C)
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/* Oscillator Calibration Register */
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#define PMC_OCR MMIO32(PMC_BASE + 0x0110)
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/* --- Register contents --------------------------------------------------- */
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/* --- PMC Clock Generator Main Clock Frequency Register (CKGR_MCFR) ------- */
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/* RC Oscillator Frequency Measure (write-only, only on atsam3s8) */
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#define CKGR_MCFR_RCMEAS (0x01 << 20)
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/* --- PMC Clock Generator PLLB Register (CKGR_PLLBR) ---------------------- */
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/* PLLB Multiplier */
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#define CKGR_PLLBR_MULB_SHIFT 16
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#define CKGR_PLLBR_MULB_MASK (0x7FF << CKGR_PLLBR_MULB_SHIFT)
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/* PLLA Counter */
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#define CKGR_PLLBR_PLLBCOUNT_SHIFT 8
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#define CKGR_PLLBR_PLLBCOUNT_MASK (0x3F << CKGR_PLLBR_PLLBCOUNT_SHIFT)
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/* Divider */
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#define CKGR_PLLBR_DIVB_SHIFT 0
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#define CKGR_PLLBR_DIVB_MASK (0xFF << CKGR_PLLBR_DIVB_SHIFT)
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/* --- PMC Master Clock Register (PMC_MCKR) -------------------------------- */
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/* PLLB Divide by 2 */
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#define PMC_MCKR_PLLBDIV2 (0x01 << 13)
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/* PLLA Divide by 2 */
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#define PMC_MCKR_PLLADIV2 (0x01 << 12)
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/* Master Clock Source Selection */
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#define PMC_MCKR_CSS_PLLB_CLK (3 << PMC_MCKR_CSS_SHIFT)
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/* --- PMC Programmable Clock Register 0 (PMC_PCK0) ------------------------ */
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/* Master Clock Source Selection */
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#define PMC_PCK0_CSS_PLLB_CLK (3 << PMC_PCK0_CSS_SHIFT)
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/* --- PMC Programmable Clock Register 1 (PMC_PCK1) ------------------------ */
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/* Master Clock Source Selection */
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#define PMC_PCK1_CSS_PLLB_CLK (3 << PMC_PCK1_CSS_SHIFT)
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/* --- PMC Programmable Clock Register 2 (PMC_PCK2) ------------------------ */
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/* Master Clock Source Selection */
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#define PMC_PCK2_CSS_PLLB_CLK (3 << PMC_PCK2_CSS_SHIFT)
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/* --- PMC Interrupt Enable Register (PMC_IER) ----------------------------- */
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/* PLLB Lock Interrupt Enable */
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#define PMC_IER_LOCKB (0x01 << 2)
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/* --- PMC Interrupt Disable Register (PMC_IDR) ---------------------------- */
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/* PLLB Lock Interrupt Disable */
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#define PMC_IDR_LOCKB (0x01 << 2)
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/* --- PMC Status Register (PMC_SR) ---------------------------------------- */
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/* PLLB Lock Status */
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#define PMC_SR_LOCKB (0x01 << 2)
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/* --- PMC Interrupt Mask Register (PMC_IDR) ------------------------------- */
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/* PLLB Lock Interrupt Mask */
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#define PMC_IMR_LOCKB (0x01 << 2)
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/* --- PMC Oscillator Calibration Register (PMC_OCR) ----------------------- */
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/* Selection of RC Oscillator Calibration bits for 12 Mhz */
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#define PMC_OCR_SEL12 (0x01 << 23)
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/* RC Oscillator Calibration bits for 12 Mhz */
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#define PMC_OCR_CAL12_SHIFT 16
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#define PMC_OCR_CAL12_MASK (0x7F << PMC_OCR_CAL12_SHIFT)
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/* Selection of RC Oscillator Calibration bits for 8 Mhz */
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#define PMC_OCR_SEL8 (0x01 << 15)
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/* RC Oscillator Calibration bits for 8 Mhz */
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#define PMC_OCR_CAL8_SHIFT 8
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#define PMC_OCR_CAL8_MASK (0x7F << PMC_OCR_CAL8_SHIFT)
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/* Selection of RC Oscillator Calibration bits for 4 Mhz */
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#define PMC_OCR_SEL4 (0x01 << 7)
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/* RC Oscillator Calibration bits for 4 Mhz */
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#define PMC_OCR_CAL4_SHIFT 0
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#define PMC_OCR_CAL4_MASK (0x7F << PMC_OCR_CAL12_SHIFT)
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#endif
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@ -0,0 +1,38 @@
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Gareth McMullin <gareth@blacksphere.co.nz>
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* Copyright (C) 2015 Felix Held <felix-libopencm3@felixheld.de>
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*
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* This library is free software: you can redistribute it and/or modify
|
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* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
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* (at your option) any later version.
|
||||
*
|
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* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU Lesser General Public License for more details.
|
||||
*
|
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* You should have received a copy of the GNU Lesser General Public License
|
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_PMC_H
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#define LIBOPENCM3_PMC_H
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#include <libopencm3/sam/memorymap.h>
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#include <libopencm3/sam/common/pmc_common_all.h>
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#include <libopencm3/sam/common/pmc_common_3n3u.h>
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#include <libopencm3/sam/common/pmc_common_3a3u3x.h>
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/* --- Register contents --------------------------------------------------- */
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/* --- PMC Clock Generator Main Oscillator Register (CKGR_MOR) ------------- */
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/* Wait Mode Command */
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#define CKGR_MOR_WAITMODE (0x01 << 2)
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#endif
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@ -0,0 +1,64 @@
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Gareth McMullin <gareth@blacksphere.co.nz>
|
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* Copyright (C) 2015 Felix Held <felix-libopencm3@felixheld.de>
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*
|
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* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
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*/
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#ifndef LIBOPENCM3_PMC_H
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#define LIBOPENCM3_PMC_H
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#include <libopencm3/sam/memorymap.h>
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#include <libopencm3/sam/common/pmc_common_all.h>
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#include <libopencm3/sam/common/pmc_common_3a3s3x.h>
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#include <libopencm3/sam/common/pmc_common_3a3u3x.h>
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/* --- Power Management Controller (PMC) registers ----------------------- */
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/* Peripheral Control Register */
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#define PMC_PCR MMIO32(PMC_BASE + 0x010C)
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/* --- Register contents --------------------------------------------------- */
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/* --- PMC Master Clock Register (PMC_MCKR) -------------------------------- */
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/* PLLA Divide by 2 */
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#define PMC_MCKR_PLLADIV2 (0x01 << 12)
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/* --- PMC Peripheral Control Register (PMC_PCR) --------------------------- */
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/* Enable */
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#define PMC_PCR_EN (0x01 << 28)
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/* Divisor Value */
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#define PMC_PCR_DIV_SHIFT 16
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#define PMC_PCR_DIV_MASK (0x03 << PMC_PCR_DIV_SHIFT)
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#define PMC_PCR_DIV_PERIPH_DIV_MCK (0x00 << PMC_PCR_DIV_SHIFT)
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#define PMC_PCR_DIV_PERIPH_DIV2_MCK (0x01 << PMC_PCR_DIV_SHIFT)
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#define PMC_PCR_DIV_PERIPH_DIV4_MCK (0x02 << PMC_PCR_DIV_SHIFT)
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/* Command */
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#define PMC_PCR_CMD (0x01 << 12)
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/* Peripheral ID */
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#define PMC_PCR_PID_SHIFT 0
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#define PMC_PCR_PID_MASK (0x3F << PMC_PCR_PID_SHIFT)
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#endif
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@ -0,0 +1,68 @@
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Gareth McMullin <gareth@blacksphere.co.nz>
|
||||
* Copyright (C) 2015 Felix Held <felix-libopencm3@felixheld.de>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#if defined(LIBOPENCM3_PMC_H)
|
||||
|
||||
#ifndef LIBOPENCM3_PMC_COMMON_3A3S3X_H
|
||||
#define LIBOPENCM3_PMC_COMMON_3A3S3X_H
|
||||
|
||||
|
||||
/* --- Power Management Controller (PMC) registers ----------------------- */
|
||||
|
||||
/* Peripheral Clock Enable Register 0 */
|
||||
#define PMC_PCER0 MMIO32(PMC_BASE + 0x0010)
|
||||
|
||||
/* Peripheral Clock Disable Register 0 */
|
||||
#define PMC_PCDR0 MMIO32(PMC_BASE + 0x0014)
|
||||
|
||||
/* Peripheral Clock Status Register 0 */
|
||||
#define PMC_PCSR0 MMIO32(PMC_BASE + 0x0018)
|
||||
|
||||
/* USB Clock Register */
|
||||
#define PMC_USB MMIO32(PMC_BASE + 0x0038)
|
||||
|
||||
/* Peripheral Clock Enable Register 1 */
|
||||
#define PMC_PCER1 MMIO32(PMC_BASE + 0x0100)
|
||||
|
||||
/* Peripheral Clock Disable Register 1 */
|
||||
#define PMC_PCDR1 MMIO32(PMC_BASE + 0x0104)
|
||||
|
||||
/* Peripheral Clock Status Register 1 */
|
||||
#define PMC_PCSR1 MMIO32(PMC_BASE + 0x0108)
|
||||
|
||||
|
||||
/* --- Register contents --------------------------------------------------- */
|
||||
|
||||
|
||||
/* --- PMC USB Clock Register (PMC_USB) ------------------------------------ */
|
||||
|
||||
/* Divider for USB Clock */
|
||||
#define PMC_USB_USBDIV_SHIFT 8
|
||||
#define PMC_USB_USBDIV_MASK (0x0F << PMC_USB_USBDIV_SHIFT)
|
||||
|
||||
/* USB Input Clock Selection */
|
||||
#define PMC_USB_USBS (0x01 << 0)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
#else
|
||||
#warning "pmc_common_3a3s3x.h should not be included explicitly, only via pmc.h"
|
||||
#endif
|
||||
|
|
@ -0,0 +1,100 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Gareth McMullin <gareth@blacksphere.co.nz>
|
||||
* Copyright (C) 2015 Felix Held <felix-libopencm3@felixheld.de>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#if defined(LIBOPENCM3_PMC_H)
|
||||
|
||||
#ifndef LIBOPENCM3_PMC_COMMON_3A3U3X_H
|
||||
#define LIBOPENCM3_PMC_COMMON_3A3U3X_H
|
||||
|
||||
|
||||
/* --- Power Management Controller (PMC) registers ----------------------- */
|
||||
|
||||
/* UTMI Clock Register */
|
||||
#define CKGR_UCKR MMIO32(PMC_BASE + 0x001C)
|
||||
|
||||
|
||||
/* --- Register contents --------------------------------------------------- */
|
||||
|
||||
|
||||
/* --- PMC UTMI Clock Configuration Register (CKGR_UCKR) ------------------- */
|
||||
|
||||
/* UTMI PLL Start-up Time */
|
||||
#define CKGR_UCKR_UPLLCOUNT_SHIFT 20
|
||||
#define CKGR_UCKR_UPLLCOUNT_MASK (0x0F << CKGR_UCKR_UPLLCOUNT_SHIFT)
|
||||
|
||||
/* UTMI PLL Enable */
|
||||
#define CKGR_UCKR_UPLLEN (0x01 << 16)
|
||||
|
||||
/* --- PMC Master Clock Register (PMC_MCKR) -------------------------------- */
|
||||
|
||||
/* UPLL Divide by 2 */
|
||||
#define PMC_MCKR_UPLLDIV2 (0x01 << 13)
|
||||
|
||||
/* Master Clock Source Selection */
|
||||
#define PMC_MCKR_CSS_UPLL_CLK (3 << PMC_MCKR_CSS_SHIFT)
|
||||
|
||||
|
||||
/* --- PMC Programmable Clock Register 0 (PMC_PCK0) ------------------------ */
|
||||
|
||||
/* Master Clock Source Selection */
|
||||
#define PMC_PCK0_CSS_UPLL_CLK (3 << PMC_PCK0_CSS_SHIFT)
|
||||
|
||||
|
||||
/* --- PMC Programmable Clock Register 1 (PMC_PCK1) ------------------------ */
|
||||
|
||||
/* Master Clock Source Selection */
|
||||
#define PMC_PCK1_CSS_UPLL_CLK (3 << PMC_PCK1_CSS_SHIFT)
|
||||
|
||||
|
||||
/* --- PMC Programmable Clock Register 2 (PMC_PCK2) ------------------------ */
|
||||
|
||||
/* Master Clock Source Selection */
|
||||
#define PMC_PCK2_CSS_UPLL_CLK (3 << PMC_PCK2_CSS_SHIFT)
|
||||
|
||||
|
||||
/* --- PMC Interrupt Enable Register (PMC_IER) ----------------------------- */
|
||||
|
||||
/* UTMI PLL Lock Interrupt Enable */
|
||||
#define PMC_IER_LOCKU (0x01 << 6)
|
||||
|
||||
|
||||
/* --- PMC Interrupt Disable Register (PMC_IDR) ----------------------------- */
|
||||
|
||||
/* UTMI PLL Lock Interrupt Disable */
|
||||
#define PMC_IDR_LOCKU (0x01 << 6)
|
||||
|
||||
|
||||
/* --- PMC Status Register (PMC_SR) ---------------------------------------- */
|
||||
|
||||
/* UTMI PLL Lock Status */
|
||||
#define PMC_SR_LOCKU (0x01 << 6)
|
||||
|
||||
|
||||
/* --- PMC Interrupt Mask Register (PMC_IMR) ----------------------------- */
|
||||
|
||||
/* UTMI PLL Lock Interrupt Mask */
|
||||
#define PMC_IMR_LOCKU (0x01 << 6)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
#else
|
||||
#warning "pmc_common_3a3u3x.h should not be included explicitly, only via pmc.h"
|
||||
#endif
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2015 Felix Held <felix-libopencm3@felixheld.de>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#if defined(LIBOPENCM3_PMC_H)
|
||||
|
||||
#ifndef LIBOPENCM3_PMC_COMMON_3N3U_H
|
||||
#define LIBOPENCM3_PMC_COMMON_3N3U_H
|
||||
|
||||
/* Peripheral Clock Enable Register */
|
||||
#define PMC_PCER MMIO32(PMC_BASE + 0x0010)
|
||||
|
||||
/* Peripheral Clock Disable Register */
|
||||
#define PMC_PCDR MMIO32(PMC_BASE + 0x0014)
|
||||
|
||||
/* Peripheral Clock Status Register */
|
||||
#define PMC_PCSR MMIO32(PMC_BASE + 0x0018)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
#else
|
||||
#warning "pmc_common_3n3u.h should not be included explicitly, only via pmc.h"
|
||||
#endif
|
||||
|
|
@ -0,0 +1,501 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Gareth McMullin <gareth@blacksphere.co.nz>
|
||||
* Copyright (C) 2015 Felix Held <felix-libopencm3@felixheld.de>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#if defined(LIBOPENCM3_PMC_H)
|
||||
|
||||
#ifndef LIBOPENCM3_PMC_COMMON_ALL_H
|
||||
#define LIBOPENCM3_PMC_COMMON_ALL_H
|
||||
|
||||
#include <libopencm3/cm3/common.h>
|
||||
|
||||
/* --- Power Management Controller (PMC) registers ----------------------- */
|
||||
|
||||
/* System Clock Enable Register */
|
||||
#define PMC_SCER MMIO32(PMC_BASE + 0x0000)
|
||||
|
||||
/* System Clock Disable Register */
|
||||
#define PMC_SCDR MMIO32(PMC_BASE + 0x0004)
|
||||
|
||||
/* System Clock Status Register */
|
||||
#define PMC_SCSR MMIO32(PMC_BASE + 0x0008)
|
||||
|
||||
/* Main Oscillator Register */
|
||||
#define CKGR_MOR MMIO32(PMC_BASE + 0x0020)
|
||||
|
||||
/* Main Clock Frequency Register */
|
||||
#define CKGR_MCFR MMIO32(PMC_BASE + 0x0024)
|
||||
|
||||
/* PLLA Register */
|
||||
#define CKGR_PLLAR MMIO32(PMC_BASE + 0x0028)
|
||||
|
||||
/* Master Clock Register */
|
||||
#define PMC_MCKR MMIO32(PMC_BASE + 0x0030)
|
||||
|
||||
/* Programmable Clock 0 Register */
|
||||
#define PMC_PCK0 MMIO32(PMC_BASE + 0x0040)
|
||||
|
||||
/* Programmable Clock 1 Register */
|
||||
#define PMC_PCK1 MMIO32(PMC_BASE + 0x0044)
|
||||
|
||||
/* Programmable Clock 2 Register */
|
||||
#define PMC_PCK2 MMIO32(PMC_BASE + 0x0048)
|
||||
|
||||
/* Interrupt Enable Register */
|
||||
#define PMC_IER MMIO32(PMC_BASE + 0x0060)
|
||||
|
||||
/* Interrupt Disable Register */
|
||||
#define PMC_IDR MMIO32(PMC_BASE + 0x0064)
|
||||
|
||||
/* Status Register */
|
||||
#define PMC_SR MMIO32(PMC_BASE + 0x0068)
|
||||
|
||||
/* Interrupt Mask Register */
|
||||
#define PMC_IMR MMIO32(PMC_BASE + 0x006C)
|
||||
|
||||
/* Fast Startup Mode Register */
|
||||
#define PMC_FSMR MMIO32(PMC_BASE + 0x0070)
|
||||
|
||||
/* Fast Startup Polarity Register */
|
||||
#define PMC_FSPR MMIO32(PMC_BASE + 0x0074)
|
||||
|
||||
/* Fault Output Clear Register */
|
||||
#define PMC_FOCR MMIO32(PMC_BASE + 0x0078)
|
||||
|
||||
/* Write Protect Mode Register */
|
||||
#define PMC_WPMR MMIO32(PMC_BASE + 0x00E4)
|
||||
|
||||
/* Write Protect Status Register */
|
||||
#define PMC_WPSR MMIO32(PMC_BASE + 0x00E8)
|
||||
|
||||
|
||||
/* --- Register contents --------------------------------------------------- */
|
||||
|
||||
|
||||
/* --- PMC System Clock Enable Register (PMC_SCER) ------------------------- */
|
||||
|
||||
/* Programmable Clock Output Enable */
|
||||
#define PMC_SCER_PCK0 (0x01 << 8)
|
||||
#define PMC_SCER_PCK1 (0x01 << 9)
|
||||
#define PMC_SCER_PCK2 (0x01 << 10)
|
||||
|
||||
|
||||
/* --- PMC System Clock Disable Register (PMC_SCDR) ------------------------ */
|
||||
|
||||
/* Programmable Clock Output Disable */
|
||||
#define PMC_SCDR_PCK0 (0x01 << 8)
|
||||
#define PMC_SCDR_PCK1 (0x01 << 9)
|
||||
#define PMC_SCDR_PCK2 (0x01 << 10)
|
||||
|
||||
|
||||
/* --- PMC System Clock Status Register (PMC_SCSR) ------------------------- */
|
||||
|
||||
/* Programmable Clock Output Status */
|
||||
#define PMC_SCSR_PCK0 (0x01 << 8)
|
||||
#define PMC_SCSR_PCK1 (0x01 << 9)
|
||||
#define PMC_SCSR_PCK2 (0x01 << 10)
|
||||
|
||||
|
||||
/* for bit definitions for PMC System Clock Enable/Disable/Status Register see
|
||||
* periph.h */
|
||||
|
||||
|
||||
/* --- PMC Clock Generator Main Oscillator Register (CKGR_MOR) ------------- */
|
||||
|
||||
/* Clock Failure Detector Enable */
|
||||
#define CKGR_MOR_CFDEN (0x01 << 25)
|
||||
|
||||
/* Main Oscillator Selection */
|
||||
#define CKGR_MOR_MOSCSEL (0x01 << 24)
|
||||
|
||||
/* Password for changing settings */
|
||||
#define CKGR_MOR_KEY (0x37 << 16)
|
||||
|
||||
/* Main Crystal Oscillator Start-up Time */
|
||||
#define CKGR_MOR_MOSCXTST_SHIFT 8
|
||||
#define CKGR_MOR_MOSCXTST_MASK (0xFF << 8)
|
||||
|
||||
/* Main On-Chip RC Oscillator Frequency Selection */
|
||||
#define CKGR_MOR_MOSCRCF_SHIFT 4
|
||||
#define CKGR_MOR_MOSCRCF_MASK (0x07 << CKGR_MOR_MOSCRCF_SHIFT)
|
||||
|
||||
/* Main On-Chip RC Oscillator selectable frequencies */
|
||||
#define CKGR_MOR_MOSCRCF_4MHZ (0 << CKGR_MOR_MOSCRCF_SHIFT)
|
||||
#define CKGR_MOR_MOSCRCF_8MHZ (1 << CKGR_MOR_MOSCRCF_SHIFT)
|
||||
#define CKGR_MOR_MOSCRCF_12MHZ (2 << CKGR_MOR_MOSCRCF_SHIFT)
|
||||
|
||||
/* Main On-Chip RC Oscillator Enable */
|
||||
#define CKGR_MOR_MOSCRCEN (0x01 << 3)
|
||||
|
||||
/* Main Crystal Oscillator Bypass */
|
||||
#define CKGR_MOR_MOSCXTBY (0x01 << 1)
|
||||
|
||||
/* Main Crystal Oscillator Enable */
|
||||
#define CKGR_MOR_MOSCXTEN (0x01 << 0)
|
||||
|
||||
|
||||
/* --- PMC Clock Generator Main Clock Frequency Register (CKGR_MCFR) ------- */
|
||||
|
||||
/* Main Clock Ready */
|
||||
#define CKGR_MCFR_MAINFRDY (0x01 << 16)
|
||||
|
||||
/* Main Clock Frequency */
|
||||
#define CKGR_MCFR_MAINF_SHIFT 0
|
||||
#define CKGR_MCFR_MAINF_MASK (0xFFFF << CKGR_MCFR_MAINF_SHIFT)
|
||||
|
||||
|
||||
/* --- PMC Clock Generator PLLA Register (CKGR_PLLAR) ---------------------- */
|
||||
|
||||
/* must be set to program CKGR_PLLAR */
|
||||
#define CKGR_PLLAR_ONE (0x01 << 29)
|
||||
|
||||
/* PLLA Multiplier */
|
||||
#define CKGR_PLLAR_MULA_SHIFT 16
|
||||
#define CKGR_PLLAR_MULA_MASK (0x7FF << CKGR_PLLAR_MULA_SHIFT)
|
||||
|
||||
/* PLLA Counter */
|
||||
#define CKGR_PLLAR_PLLACOUNT_SHIFT 8
|
||||
#define CKGR_PLLAR_PLLACOUNT_MASK (0x3F << CKGR_PLLAR_PLLACOUNT_SHIFT)
|
||||
|
||||
/* Divider */
|
||||
#define CKGR_PLLAR_DIVA_SHIFT 0
|
||||
#define CKGR_PLLAR_DIVA_MASK (0xFF << CKGR_PLLAR_DIVA_SHIFT)
|
||||
|
||||
|
||||
/* --- PMC Master Clock Register (PMC_MCKR) -------------------------------- */
|
||||
|
||||
/* Processor Clock Prescaler */
|
||||
#define PMC_MCKR_PRES_SHIFT 4
|
||||
#define PMC_MCKR_PRES_MASK (0x07 << PMC_MCKR_PRES_SHIFT)
|
||||
#define PMC_MCKR_PRES_CLK_1 (0 << PMC_MCKR_PRES_SHIFT)
|
||||
#define PMC_MCKR_PRES_CLK_2 (1 << PMC_MCKR_PRES_SHIFT)
|
||||
#define PMC_MCKR_PRES_CLK_4 (2 << PMC_MCKR_PRES_SHIFT)
|
||||
#define PMC_MCKR_PRES_CLK_8 (3 << PMC_MCKR_PRES_SHIFT)
|
||||
#define PMC_MCKR_PRES_CLK_16 (4 << PMC_MCKR_PRES_SHIFT)
|
||||
#define PMC_MCKR_PRES_CLK_32 (5 << PMC_MCKR_PRES_SHIFT)
|
||||
#define PMC_MCKR_PRES_CLK_64 (6 << PMC_MCKR_PRES_SHIFT)
|
||||
#define PMC_MCKR_PRES_CLK_3 (7 << PMC_MCKR_PRES_SHIFT)
|
||||
|
||||
/* Master Clock Source Selection */
|
||||
#define PMC_MCKR_CSS_SHIFT 0
|
||||
#define PMC_MCKR_CSS_MASK (0x03 << PMC_MCKR_CSS_SHIFT)
|
||||
#define PMC_MCKR_CSS_SLOW_CLK (0 << PMC_MCKR_CSS_SHIFT)
|
||||
#define PMC_MCKR_CSS_MAIN_CLK (1 << PMC_MCKR_CSS_SHIFT)
|
||||
#define PMC_MCKR_CSS_PLLA_CLK (2 << PMC_MCKR_CSS_SHIFT)
|
||||
|
||||
|
||||
/* --- PMC Programmable Clock Register 0 (PMC_PCK0) ------------------------ */
|
||||
|
||||
/* Programmable Clock Prescaler */
|
||||
#define PMC_PCK0_PRES_SHIFT 4
|
||||
#define PMC_PCK0_PRES_MASK (0x07 << PMC_PCK0_PRES_SHIFT)
|
||||
#define PMC_PCK0_PRES_CLK_1 (0 << PMC_PCK0_PRES_SHIFT)
|
||||
#define PMC_PCK0_PRES_CLK_2 (1 << PMC_PCK0_PRES_SHIFT)
|
||||
#define PMC_PCK0_PRES_CLK_4 (2 << PMC_PCK0_PRES_SHIFT)
|
||||
#define PMC_PCK0_PRES_CLK_8 (3 << PMC_PCK0_PRES_SHIFT)
|
||||
#define PMC_PCK0_PRES_CLK_16 (4 << PMC_PCK0_PRES_SHIFT)
|
||||
#define PMC_PCK0_PRES_CLK_32 (5 << PMC_PCK0_PRES_SHIFT)
|
||||
#define PMC_PCK0_PRES_CLK_64 (6 << PMC_PCK0_PRES_SHIFT)
|
||||
|
||||
/* Master Clock Source Selection */
|
||||
#define PMC_PCK0_CSS_SHIFT 0
|
||||
#define PMC_PCK0_CSS_MASK (0x07 << PMC_PCK0_CSS_SHIFT)
|
||||
#define PMC_PCK0_CSS_SLOW_CLK (0 << PMC_PCK0_CSS_SHIFT)
|
||||
#define PMC_PCK0_CSS_MAIN_CLK (1 << PMC_PCK0_CSS_SHIFT)
|
||||
#define PMC_PCK0_CSS_PLLA_CLK (2 << PMC_PCK0_CSS_SHIFT)
|
||||
#define PMC_PCK0_CSS_MCK (4 << PMC_PCK0_CSS_SHIFT)
|
||||
|
||||
|
||||
/* --- PMC Programmable Clock Register 1 (PMC_PCK1) ------------------------ */
|
||||
|
||||
/* Programmable Clock Prescaler */
|
||||
#define PMC_PCK1_PRES_SHIFT 4
|
||||
#define PMC_PCK1_PRES_MASK (0x07 << PMC_PCK1_PRES_SHIFT)
|
||||
#define PMC_PCK1_PRES_CLK_1 (0 << PMC_PCK1_PRES_SHIFT)
|
||||
#define PMC_PCK1_PRES_CLK_2 (1 << PMC_PCK1_PRES_SHIFT)
|
||||
#define PMC_PCK1_PRES_CLK_4 (2 << PMC_PCK1_PRES_SHIFT)
|
||||
#define PMC_PCK1_PRES_CLK_8 (3 << PMC_PCK1_PRES_SHIFT)
|
||||
#define PMC_PCK1_PRES_CLK_16 (4 << PMC_PCK1_PRES_SHIFT)
|
||||
#define PMC_PCK1_PRES_CLK_32 (5 << PMC_PCK1_PRES_SHIFT)
|
||||
#define PMC_PCK1_PRES_CLK_64 (6 << PMC_PCK1_PRES_SHIFT)
|
||||
|
||||
/* Master Clock Source Selection */
|
||||
#define PMC_PCK1_CSS_SHIFT 0
|
||||
#define PMC_PCK1_CSS_MASK (0x07 << PMC_PCK1_CSS_SHIFT)
|
||||
#define PMC_PCK1_CSS_SLOW_CLK (0 << PMC_PCK1_CSS_SHIFT)
|
||||
#define PMC_PCK1_CSS_MAIN_CLK (1 << PMC_PCK1_CSS_SHIFT)
|
||||
#define PMC_PCK1_CSS_PLLA_CLK (2 << PMC_PCK1_CSS_SHIFT)
|
||||
#define PMC_PCK1_CSS_MCK (4 << PMC_PCK1_CSS_SHIFT)
|
||||
|
||||
|
||||
/* --- PMC Programmable Clock Register 2 (PMC_PCK2) ------------------------ */
|
||||
|
||||
/* Programmable Clock Prescaler */
|
||||
#define PMC_PCK2_PRES_SHIFT 4
|
||||
#define PMC_PCK2_PRES_MASK (0x07 << PMC_PCK2_PRES_SHIFT)
|
||||
#define PMC_PCK2_PRES_CLK_1 (0 << PMC_PCK2_PRES_SHIFT)
|
||||
#define PMC_PCK2_PRES_CLK_2 (1 << PMC_PCK2_PRES_SHIFT)
|
||||
#define PMC_PCK2_PRES_CLK_4 (2 << PMC_PCK2_PRES_SHIFT)
|
||||
#define PMC_PCK2_PRES_CLK_8 (3 << PMC_PCK2_PRES_SHIFT)
|
||||
#define PMC_PCK2_PRES_CLK_16 (4 << PMC_PCK2_PRES_SHIFT)
|
||||
#define PMC_PCK2_PRES_CLK_32 (5 << PMC_PCK2_PRES_SHIFT)
|
||||
#define PMC_PCK2_PRES_CLK_64 (6 << PMC_PCK2_PRES_SHIFT)
|
||||
|
||||
/* Master Clock Source Selection */
|
||||
#define PMC_PCK2_CSS_SHIFT 0
|
||||
#define PMC_PCK2_CSS_MASK (0x07 << PMC_PCK2_CSS_SHIFT)
|
||||
#define PMC_PCK2_CSS_SLOW_CLK (0 << PMC_PCK2_CSS_SHIFT)
|
||||
#define PMC_PCK2_CSS_MAIN_CLK (1 << PMC_PCK2_CSS_SHIFT)
|
||||
#define PMC_PCK2_CSS_PLLA_CLK (2 << PMC_PCK2_CSS_SHIFT)
|
||||
#define PMC_PCK2_CSS_MCK (4 << PMC_PCK2_CSS_SHIFT)
|
||||
|
||||
|
||||
/* --- PMC Interrupt Enable Register (PMC_IER) ----------------------------- */
|
||||
|
||||
/* Clock Failure Detector Event Interrupt Enable */
|
||||
#define PMC_IER_CFDEV (0x01 << 18)
|
||||
|
||||
/* Main On-Chip RC Status Interrupt Enable */
|
||||
#define PMC_IER_MOSCRCS (0x01 << 17)
|
||||
|
||||
/* Main Oscillator Selection Status Interrupt Enable */
|
||||
#define PMC_IER_MOSCSELS (0x01 << 16)
|
||||
|
||||
/* Programmable Clock Ready 2 Interrupt Enable */
|
||||
#define PMC_IER_PCKRDY2 (0x01 << 10)
|
||||
|
||||
/* Programmable Clock Ready 1 Interrupt Enable */
|
||||
#define PMC_IER_PCKRDY1 (0x01 << 9)
|
||||
|
||||
/* Programmable Clock Ready 0 Interrupt Enable */
|
||||
#define PMC_IER_PCKRDY0 (0x01 << 8)
|
||||
|
||||
/* Master Clock Ready Interrupt Enable */
|
||||
#define PMC_IER_MCKRDY (0x01 << 3)
|
||||
|
||||
/* PLLA Lock Interrupt Enable */
|
||||
#define PMC_IER_LOCKA (0x01 << 1)
|
||||
|
||||
/* Main Crystal Oscillator Status Interrupt Enable */
|
||||
#define PMC_IER_MOSCXTS (0x01 << 0)
|
||||
|
||||
|
||||
/* --- PMC Interrupt Disable Register (PMC_IDR) ----------------------------- */
|
||||
|
||||
/* Clock Failure Detector Event Interrupt Disable */
|
||||
#define PMC_IDR_CFDEV (0x01 << 18)
|
||||
|
||||
/* Main On-Chip RC Status Interrupt Disable */
|
||||
#define PMC_IDR_MOSCRCS (0x01 << 17)
|
||||
|
||||
/* Main Oscillator Selection Status Interrupt Disable */
|
||||
#define PMC_IDR_MOSCSELS (0x01 << 16)
|
||||
|
||||
/* Programmable Clock Ready 2 Interrupt Disable */
|
||||
#define PMC_IDR_PCKRDY2 (0x01 << 10)
|
||||
|
||||
/* Programmable Clock Ready 1 Interrupt Disable */
|
||||
#define PMC_IDR_PCKRDY1 (0x01 << 9)
|
||||
|
||||
/* Programmable Clock Ready 0 Interrupt Disable */
|
||||
#define PMC_IDR_PCKRDY0 (0x01 << 8)
|
||||
|
||||
/* Master Clock Ready Interrupt Disable */
|
||||
#define PMC_IDR_MCKRDY (0x01 << 3)
|
||||
|
||||
/* PLLA Lock Interrupt Disable */
|
||||
#define PMC_IDR_LOCKA (0x01 << 1)
|
||||
|
||||
/* Main Crystal Oscillator Status Interrupt Disable */
|
||||
#define PMC_IDR_MOSCXTS (0x01 << 0)
|
||||
|
||||
|
||||
/* --- PMC Status Register (PMC_SR) ---------------------------------------- */
|
||||
|
||||
/* Clock Failure Detector Fault Output Status */
|
||||
#define PMC_SR_FOS (0x01 << 20)
|
||||
|
||||
/* Clock Failure Detector Status */
|
||||
#define PMC_SR_CFDS (0x01 << 19)
|
||||
|
||||
/* Clock Failure Detector Event */
|
||||
#define PMC_SR_CFDEV (0x01 << 18)
|
||||
|
||||
/* Main On-Chip RC Oscillator Status */
|
||||
#define PMC_SR_MOSCRCS (0x01 << 17)
|
||||
|
||||
/* Main Oscillator Selection Status */
|
||||
#define PMC_SR_MOSCSELS (0x01 << 16)
|
||||
|
||||
/* Programmable Clock 2 Ready Status */
|
||||
#define PMC_SR_PCKRDY2 (0x01 << 10)
|
||||
|
||||
/* Programmable Clock 1 Ready Status */
|
||||
#define PMC_SR_PCKRDY1 (0x01 << 9)
|
||||
|
||||
/* Programmable Clock 0 Ready Status */
|
||||
#define PMC_SR_PCKRDY0 (0x01 << 8)
|
||||
|
||||
/* Slow Clock Oscillator Selection */
|
||||
#define PMC_SR_OSCSELS (0x01 << 7)
|
||||
|
||||
/* Master Clock Status */
|
||||
#define PMC_SR_MCKRDY (0x01 << 3)
|
||||
|
||||
/* PLLA Lock Status */
|
||||
#define PMC_SR_LOCKA (0x01 << 1)
|
||||
|
||||
/* Main XTAL Oscillator Status */
|
||||
#define PMC_SR_MOSCXTS (0x01 << 0)
|
||||
|
||||
|
||||
/* --- PMC Interrupt Mask Register (PMC_IMR) ------------------------------- */
|
||||
|
||||
/* Clock Failure Detector Event Interrupt Mask */
|
||||
#define PMC_IMR_CFDEV (0x01 << 18)
|
||||
|
||||
/* Main On-Chip RC Status Interrupt Mask */
|
||||
#define PMC_IMR_MOSCRCS (0x01 << 17)
|
||||
|
||||
/* Main Oscillator Selection Status Interrupt Mask */
|
||||
#define PMC_IMR_MOSCSELS (0x01 << 16)
|
||||
|
||||
/* Programmable Clock Ready 2 Interrupt Mask */
|
||||
#define PMC_IMR_PCKRDY2 (0x01 << 10)
|
||||
|
||||
/* Programmable Clock Ready 1 Interrupt Mask */
|
||||
#define PMC_IMR_PCKRDY1 (0x01 << 9)
|
||||
|
||||
/* Programmable Clock Ready 0 Interrupt Mask */
|
||||
#define PMC_IMR_PCKRDY0 (0x01 << 8)
|
||||
|
||||
/* Master Clock Ready Interrupt Mask */
|
||||
#define PMC_IMR_MCKRDY (0x01 << 3)
|
||||
|
||||
/* PLLA Lock Interrupt Mask */
|
||||
#define PMC_IMR_LOCKA (0x01 << 1)
|
||||
|
||||
/* Main Crystal Oscillator Status Interrupt Mask */
|
||||
#define PMC_IMR_MOSCXTS (0x01 << 0)
|
||||
|
||||
|
||||
/* --- PMC Fast Startup Mode Register (PMC_FSMR) --------------------------- */
|
||||
|
||||
/* Low Power Mode */
|
||||
#define PMC_FSMR_LPM (0x01 << 20)
|
||||
|
||||
/* USB Alarm Enable */
|
||||
#define PMC_FSMR_USBAL (0x01 << 18)
|
||||
|
||||
/* RTC Alarm Enable */
|
||||
#define PMC_FSMR_RTCAL (0x01 << 17)
|
||||
|
||||
/* RTC Alarm Enable */
|
||||
#define PMC_FSMR_RTTAL (0x01 << 16)
|
||||
|
||||
/* Fast Startup Input Enable 0 to 15 */
|
||||
#define PMC_FSMR_FSTT15 (0x01 << 15)
|
||||
#define PMC_FSMR_FSTT14 (0x01 << 14)
|
||||
#define PMC_FSMR_FSTT13 (0x01 << 13)
|
||||
#define PMC_FSMR_FSTT12 (0x01 << 12)
|
||||
#define PMC_FSMR_FSTT11 (0x01 << 11)
|
||||
#define PMC_FSMR_FSTT10 (0x01 << 10)
|
||||
#define PMC_FSMR_FSTT9 (0x01 << 9)
|
||||
#define PMC_FSMR_FSTT8 (0x01 << 8)
|
||||
#define PMC_FSMR_FSTT7 (0x01 << 7)
|
||||
#define PMC_FSMR_FSTT6 (0x01 << 6)
|
||||
#define PMC_FSMR_FSTT5 (0x01 << 5)
|
||||
#define PMC_FSMR_FSTT4 (0x01 << 4)
|
||||
#define PMC_FSMR_FSTT3 (0x01 << 3)
|
||||
#define PMC_FSMR_FSTT2 (0x01 << 2)
|
||||
#define PMC_FSMR_FSTT1 (0x01 << 1)
|
||||
#define PMC_FSMR_FSTT0 (0x01 << 0)
|
||||
|
||||
|
||||
/* --- PMC Fast Startup Polarity Register (PMC_FSPR) ----------------------- */
|
||||
|
||||
/* Fast Startup Input Polarity x */
|
||||
#define PMC_FSPR_FSTP15 (0x01 << 15)
|
||||
#define PMC_FSPR_FSTP14 (0x01 << 14)
|
||||
#define PMC_FSPR_FSTP13 (0x01 << 13)
|
||||
#define PMC_FSPR_FSTP12 (0x01 << 12)
|
||||
#define PMC_FSPR_FSTP11 (0x01 << 11)
|
||||
#define PMC_FSPR_FSTP10 (0x01 << 10)
|
||||
#define PMC_FSPR_FSTP9 (0x01 << 9)
|
||||
#define PMC_FSPR_FSTP8 (0x01 << 8)
|
||||
#define PMC_FSPR_FSTP7 (0x01 << 7)
|
||||
#define PMC_FSPR_FSTP6 (0x01 << 6)
|
||||
#define PMC_FSPR_FSTP5 (0x01 << 5)
|
||||
#define PMC_FSPR_FSTP4 (0x01 << 4)
|
||||
#define PMC_FSPR_FSTP3 (0x01 << 3)
|
||||
#define PMC_FSPR_FSTP2 (0x01 << 2)
|
||||
#define PMC_FSPR_FSTP1 (0x01 << 1)
|
||||
#define PMC_FSPR_FSTP0 (0x01 << 0)
|
||||
|
||||
|
||||
/* --- PMC Fault Output Clear Register (PMC_FOCR) -------------------------- */
|
||||
|
||||
/* Fault Output Clear */
|
||||
#define PMC_FOCR_FOCLR (0x01 << 0)
|
||||
|
||||
|
||||
/* --- PMC Write Protect Mode Register (PMC_WPMR) -------------------------- */
|
||||
|
||||
/* Write Protect Key */
|
||||
#define PMC_WPMR_WPKEY_SHIFT 8
|
||||
#define PMC_WPMR_WPKEY (0x504D43 << PMC_WPMR_WPKEY_SHIFT)
|
||||
|
||||
/* Write Protect Enable */
|
||||
#define PMC_WPMR_WPEN (0x01 << 0)
|
||||
|
||||
|
||||
/* --- PMC Write Protect Status Register (PMC_WPSR) ------------------------ */
|
||||
|
||||
/* Write Protect Violation Source */
|
||||
#define PMC_WPSR_WPVSRC_SHIFT 8
|
||||
#define PMC_WPSR_WPVSRC_MASK (0xFFFF << PMC_WPSR_WPVSRC_SHIFT)
|
||||
|
||||
/* Write Protect Violation Status */
|
||||
#define PMC_WPSR_WPVS (0x01 << 0)
|
||||
|
||||
|
||||
|
||||
|
||||
extern uint32_t pmc_mck_frequency;
|
||||
|
||||
enum mck_src {
|
||||
MCK_SRC_SLOW = 0,
|
||||
MCK_SRC_MAIN = 1,
|
||||
MCK_SRC_PLLA = 2,
|
||||
MCK_SRC_UPLL = 3,
|
||||
};
|
||||
|
||||
void pmc_mck_set_source(enum mck_src src);
|
||||
void pmc_xtal_enable(bool en, uint8_t startup_time);
|
||||
void pmc_plla_config(uint8_t mul, uint8_t div);
|
||||
void pmc_peripheral_clock_enable(uint8_t pid);
|
||||
void pmc_peripheral_clock_disable(uint8_t pid);
|
||||
void pmc_clock_setup_in_xtal_12mhz_out_84mhz(void);
|
||||
void pmc_clock_setup_in_rc_4mhz_out_84mhz(void);
|
||||
|
||||
#endif
|
||||
|
||||
#else
|
||||
#warning "pmc_common_all.h should not be included explicitly, only via pmc.h"
|
||||
#endif
|
||||
|
|
@ -1,8 +1,8 @@
|
|||
/* This provides unification of code over SAM subfamilies */
|
||||
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Gareth McMullin <gareth@blacksphere.co.nz>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
|
|
@ -17,130 +17,16 @@
|
|||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef SAM3X_PMC_H
|
||||
#define SAM3X_PMC_H
|
||||
|
||||
#include <libopencm3/cm3/common.h>
|
||||
#include <libopencm3/sam/memorymap.h>
|
||||
|
||||
/* --- Power Management Controller (PMC) registers ----------------------- */
|
||||
|
||||
#define PMC_SCER MMIO32(PMC_BASE + 0x0000)
|
||||
#define PMC_SCDR MMIO32(PMC_BASE + 0x0004)
|
||||
#define PMC_SCSR MMIO32(PMC_BASE + 0x0008)
|
||||
/* 0x000C - Reserved */
|
||||
#define PMC_PCER0 MMIO32(PMC_BASE + 0x0010)
|
||||
#define PMC_PCDR0 MMIO32(PMC_BASE + 0x0014)
|
||||
#define PMC_PCSR0 MMIO32(PMC_BASE + 0x0018)
|
||||
#define CKGR_UCKR MMIO32(PMC_BASE + 0x001C)
|
||||
#define CKGR_MOR MMIO32(PMC_BASE + 0x0020)
|
||||
#define CKGR_MCFR MMIO32(PMC_BASE + 0x0024)
|
||||
#define CKGR_PLLAR MMIO32(PMC_BASE + 0x0028)
|
||||
/* 0x002C - Reserved */
|
||||
#define PMC_MCKR MMIO32(PMC_BASE + 0x0030)
|
||||
/* 0x0034 - Reserved */
|
||||
#define PMC_USB MMIO32(PMC_BASE + 0x0038)
|
||||
/* 0x003C - Reserved */
|
||||
#define PMC_PCK0 MMIO32(PMC_BASE + 0x0040)
|
||||
#define PMC_PCK1 MMIO32(PMC_BASE + 0x0044)
|
||||
#define PMC_PCK2 MMIO32(PMC_BASE + 0x0048)
|
||||
/* 0x004C-0x005C - Reserved */
|
||||
#define PMC_IER MMIO32(PMC_BASE + 0x0060)
|
||||
#define PMC_IDR MMIO32(PMC_BASE + 0x0064)
|
||||
#define PMC_SR MMIO32(PMC_BASE + 0x0068)
|
||||
#define PMC_IMR MMIO32(PMC_BASE + 0x006C)
|
||||
#define PMC_FSMR MMIO32(PMC_BASE + 0x0070)
|
||||
#define PMC_FSPR MMIO32(PMC_BASE + 0x0074)
|
||||
#define PMC_FOCR MMIO32(PMC_BASE + 0x0078)
|
||||
/* 0x007C-0x00E0 - Reserved */
|
||||
#define PMC_WPMR MMIO32(PMC_BASE + 0x00E4)
|
||||
#define PMC_WPSR MMIO32(PMC_BASE + 0x00E8)
|
||||
/* 0x00EC-0x00FC - Reserved */
|
||||
#define PMC_PCER1 MMIO32(PMC_BASE + 0x0100)
|
||||
#define PMC_PCDR1 MMIO32(PMC_BASE + 0x0104)
|
||||
#define PMC_PCSR1 MMIO32(PMC_BASE + 0x0108)
|
||||
#define PMC_PCR MMIO32(PMC_BASE + 0x010C)
|
||||
|
||||
/* PMC UTMI Clock Configuration Register (CKGR_UCKR) */
|
||||
/* Bit [31:22] - Reserved */
|
||||
#define CKGR_CKGR_UPLLCOUNT_MASK (0x0F << 20)
|
||||
/* Bit [19:17] - Reserved */
|
||||
#define CKGR_CKGR_UPLLEN (0x01 << 16)
|
||||
/* Bit [15:0] - Reserved */
|
||||
|
||||
/* PMC Clock Generator Main Oscillator Register (CKGR_MOR) */
|
||||
/* Bit [31:26] - Reserved */
|
||||
#define CKGR_MOR_CFDEN (0x01 << 25)
|
||||
#define CKGR_MOR_MOSCSEL (0x01 << 24)
|
||||
#define CKGR_MOR_KEY (0x37 << 16)
|
||||
#define CKGR_MOR_MOSCXTST_MASK (0xFF << 8)
|
||||
/* Bit 7 - Reserved */
|
||||
#define CKGR_MOR_MOSCRCF_MASK (0x07 << 4)
|
||||
#define CKGR_MOR_MOSCRCEN (0x01 << 3)
|
||||
/* Bit 2 - Reserved */
|
||||
#define CKGR_MOR_MOSCXTBY (0x01 << 1)
|
||||
#define CKGR_MOR_MOSCXTEN (0x01 << 0)
|
||||
|
||||
/* PMC Clock Generator PLLA Register (CKGR_PLLAR) */
|
||||
#define CKGR_PLLAR_ONE (0x01 << 29)
|
||||
#define CKGR_PLLAR_MULA_MASK (0x7FF << 16)
|
||||
#define CKGR_PLLAR_PLLACOUNT_MASK (0x3F << 8)
|
||||
#define CKGR_PLLAR_DIVA_MASK (0xFF << 0)
|
||||
|
||||
/* PMC Master Clock Register (PMC_MCKR) */
|
||||
/* Bit [31:14] - Reserved */
|
||||
#define PMC_MCKR_UPLLDIV2 (0x01 << 13)
|
||||
#define PMC_MCKR_PLLADIV2 (0x01 << 12)
|
||||
/* Bit [11:7] - Reserved */
|
||||
#define PMC_MCKR_PRES_MASK (0x07 << 4)
|
||||
/* Bit [3:2] - Reserved */
|
||||
#define PMC_MCKR_CSS_MASK (0x03 << 0)
|
||||
#define PMC_MCKR_CSS_SLOW_CLK (0x00 << 0)
|
||||
#define PMC_MCKR_CSS_MAIN_CLK (0x01 << 0)
|
||||
#define PMC_MCKR_CSS_PLLA_CLK (0x02 << 0)
|
||||
#define PMC_MCKR_CSS_UPLL_CLK (0x03 << 0)
|
||||
|
||||
/* PMC USB Clock Register (PMC_USB) */
|
||||
/* Bit [31:12] - Reserved */
|
||||
#define PMC_USB_USBDIV_MASK (0x0F << 8)
|
||||
/* Bit [7:1] - Reserved */
|
||||
#define PMC_USB_USBS (0x01 << 0)
|
||||
|
||||
/* PMC Status Register (PMC_SR) */
|
||||
/* Bits [31:21] - Reserved */
|
||||
#define PMC_SR_FOS (0x01 << 20)
|
||||
#define PMC_SR_CFDS (0x01 << 19)
|
||||
#define PMC_SR_CFDEV (0x01 << 18)
|
||||
#define PMC_SR_MOSCRCS (0x01 << 17)
|
||||
#define PMC_SR_MOSCSELS (0x01 << 16)
|
||||
/* Bits [15:11] - Reserved */
|
||||
#define PMC_SR_PCKRDY2 (0x01 << 10)
|
||||
#define PMC_SR_PCKRDY1 (0x01 << 9)
|
||||
#define PMC_SR_PCKRDY0 (0x01 << 8)
|
||||
#define PMC_SR_OSCSELS (0x01 << 7)
|
||||
#define PMC_SR_LOCKU (0x01 << 6)
|
||||
/* Bits [5:4] - Reserved */
|
||||
#define PMC_SR_MCKRDY (0x01 << 3)
|
||||
/* Bit [2] - Reserved */
|
||||
#define PMC_SR_LOCKA (0x01 << 1)
|
||||
#define PMC_SR_MOSCXTS (0x01 << 0)
|
||||
|
||||
extern uint32_t pmc_mck_frequency;
|
||||
|
||||
enum mck_src {
|
||||
MCK_SRC_SLOW = 0,
|
||||
MCK_SRC_MAIN = 1,
|
||||
MCK_SRC_PLLA = 2,
|
||||
MCK_SRC_UPLL = 3,
|
||||
};
|
||||
|
||||
void pmc_mck_set_source(enum mck_src src);
|
||||
void pmc_xtal_enable(bool en, uint8_t startup_time);
|
||||
void pmc_plla_config(uint8_t mul, uint8_t div);
|
||||
void pmc_peripheral_clock_enable(uint8_t pid);
|
||||
void pmc_peripheral_clock_disable(uint8_t pid);
|
||||
void pmc_clock_setup_in_xtal_12mhz_out_84mhz(void);
|
||||
void pmc_clock_setup_in_rc_4mhz_out_84mhz(void);
|
||||
|
||||
#if defined(SAM3A)
|
||||
# include <libopencm3/sam/3a/pmc.h>
|
||||
#elif defined(SAM3N)
|
||||
# include <libopencm3/sam/3n/pmc.h>
|
||||
#elif defined(SAM3S)
|
||||
# include <libopencm3/sam/3s/pmc.h>
|
||||
#elif defined(SAM3U)
|
||||
# include <libopencm3/sam/3u/pmc.h>
|
||||
#elif defined(SAM3X)
|
||||
# include <libopencm3/sam/3x/pmc.h>
|
||||
#else
|
||||
# error "sam family not defined."
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -44,20 +44,29 @@ void pmc_plla_config(uint8_t mul, uint8_t div)
|
|||
|
||||
void pmc_peripheral_clock_enable(uint8_t pid)
|
||||
{
|
||||
#if defined(PMC_PCER1)
|
||||
if (pid < 32) {
|
||||
PMC_PCER0 = 1 << pid;
|
||||
} else {
|
||||
PMC_PCER1 = 1 << (pid & 31);
|
||||
}
|
||||
#else
|
||||
//SAM3N and SAM3U only have one Peripheral Clock Enable Register
|
||||
PMC_PCER = 1 << pid;
|
||||
#endif
|
||||
}
|
||||
|
||||
void pmc_peripheral_clock_disable(uint8_t pid)
|
||||
{
|
||||
#if defined(PMC_PCER1)
|
||||
if (pid < 32) {
|
||||
PMC_PCDR0 = 1 << pid;
|
||||
} else {
|
||||
PMC_PCDR1 = 1 << (pid & 31);
|
||||
}
|
||||
#else
|
||||
PMC_PCDR = 1 << pid;
|
||||
#endif
|
||||
}
|
||||
|
||||
void pmc_mck_set_source(enum mck_src src)
|
||||
|
|
|
|||
Loading…
Reference in New Issue