stm32f3: rcc: Set prescalers properly.
Copypasta from f4 rcc code was only modified to shift the result, but not clear the existing settings properly. Add mask/shift definitions and use them properly.
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@ -124,6 +124,7 @@
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/* PPRE2: APB high-speed prescaler (APB2) */
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#define RCC_CFGR_PPRE2_SHIFT 11
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#define RCC_CFGR_PPRE2_MASK 0x7
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/* 0XX: HCLK not divided */
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#define RCC_CFGR_PPRE2_DIV_NONE 0x0
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@ -134,6 +135,7 @@
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/* PPRE1:APB Low-speed prescaler (APB1) */
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#define RCC_CFGR_PPRE1_SHIFT 8
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#define RCC_CFGR_PPRE1_MASK 0x7
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/* 0XX: HCLK not divided */
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#define RCC_CFGR_PPRE1_DIV_NONE 0x0
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#define RCC_CFGR_PPRE1_DIV_2 0x4
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@ -143,6 +145,7 @@
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/* HPRE: HLCK prescaler */
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#define RCC_CFGR_HPRE_SHIFT 4
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#define RCC_CFGR_HPRE_MASK 0xf
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/* 0XXX: SYSCLK not divided */
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#define RCC_CFGR_HPRE_DIV_NONE 0x0
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#define RCC_CFGR_HPRE_DIV_2 0x8
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@ -343,8 +343,8 @@ void rcc_set_ppre2(uint32_t ppre2)
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 13) | (1 << 14) | (1 << 15));
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RCC_CFGR = (reg32 | (ppre2 << 11));
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reg32 &= ~(RCC_CFGR_PPRE2_MASK << RCC_CFGR_PPRE2_SHIFT);
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RCC_CFGR = (reg32 | (ppre2 << RCC_CFGR_PPRE2_SHIFT));
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}
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void rcc_set_ppre1(uint32_t ppre1)
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@ -352,8 +352,8 @@ void rcc_set_ppre1(uint32_t ppre1)
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 10) | (1 << 11) | (1 << 12));
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RCC_CFGR = (reg32 | (ppre1 << 8));
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reg32 &= ~(RCC_CFGR_PPRE1_MASK << RCC_CFGR_PPRE1_SHIFT);
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RCC_CFGR = (reg32 | (ppre1 << RCC_CFGR_PPRE1_SHIFT));
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}
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void rcc_set_hpre(uint32_t hpre)
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@ -361,8 +361,8 @@ void rcc_set_hpre(uint32_t hpre)
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7));
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RCC_CFGR = (reg32 | (hpre << 4));
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reg32 &= ~(RCC_CFGR_HPRE_MASK << RCC_CFGR_HPRE_SHIFT);
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RCC_CFGR = (reg32 | (hpre << RCC_CFGR_HPRE_SHIFT));
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}
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