stm32f3: rcc: Update ENR/RST definitions for newer docs
Based on latest RM0316rev5, and fixed a bug in f37x CEC bit definition that overlapped.
This commit is contained in:
Karl Palsson
parent
4d7694b454
commit
674cd9bfe9
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@ -200,9 +200,11 @@
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/* --- RCC_APB2RSTR values ------------------------------------------------- */
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#define RCC_APB2RSTR_TIM20RST (1 << 20)
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#define RCC_APB2RSTR_TIM17RST (1 << 18)
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#define RCC_APB2RSTR_TIM16RST (1 << 17)
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#define RCC_APB2RSTR_TIM15RST (1 << 16)
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#define RCC_APB2RSTR_SPI4RST (1 << 15)
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#define RCC_APB2RSTR_USART1RST (1 << 14)
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#define RCC_APB2RSTR_TIM8RST (1 << 13)
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#define RCC_APB2RSTR_SPI1RST (1 << 12)
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@ -211,8 +213,10 @@
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/* --- RCC_APB1RSTR values ------------------------------------------------- */
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#define RCC_APB1RSTR_DACRST (1 << 29)
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#define RCC_APB1RSTR_I2C3RST (1 << 30)
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#define RCC_APB1RSTR_DAC1RST (1 << 29)
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#define RCC_APB1RSTR_PWRRST (1 << 28)
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#define RCC_APB1RSTR_DAC2RST (1 << 26)
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#define RCC_APB1RSTR_CANRST (1 << 25)
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#define RCC_APB1RSTR_USBRST (1 << 23)
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#define RCC_APB1RSTR_I2C2RST (1 << 22)
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@ -234,13 +238,16 @@
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#define RCC_AHBENR_ADC34EN (1 << 29)
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#define RCC_AHBENR_ADC12EN (1 << 28)
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#define RCC_AHBENR_TSCEN (1 << 24)
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#define RCC_AHBENR_IOPGEN (1 << 23)
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#define RCC_AHBENR_IOPFEN (1 << 22)
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#define RCC_AHBENR_IOPEEN (1 << 21)
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#define RCC_AHBENR_IOPDEN (1 << 20)
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#define RCC_AHBENR_IOPCEN (1 << 19)
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#define RCC_AHBENR_IOPBEN (1 << 18)
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#define RCC_AHBENR_IOPAEN (1 << 17)
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#define RCC_AHBENR_IOPHEN (1 << 16)
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#define RCC_AHBENR_CRCEN (1 << 6)
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#define RCC_AHBENR_FMCEN (1 << 5)
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#define RCC_AHBENR_FLITFEN (1 << 4)
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#define RCC_AHBENR_SRAMEN (1 << 2)
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#define RCC_AHBENR_DMA2EN (1 << 1)
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@ -248,9 +255,11 @@
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/* --- RCC_APB2ENR values -------------------------------------------------- */
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#define RCC_APB2ENR_TIM20EN (1 << 20)
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#define RCC_APB2ENR_TIM17EN (1 << 18)
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#define RCC_APB2ENR_TIM16EN (1 << 17)
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#define RCC_APB2ENR_TIM15EN (1 << 16)
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#define RCC_APB2ENR_SPI4EN (1 << 15)
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#define RCC_APB2ENR_USART1EN (1 << 14)
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#define RCC_APB2ENR_TIM8EN (1 << 13)
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#define RCC_APB2ENR_SPI1EN (1 << 12)
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@ -259,8 +268,10 @@
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/* --- RCC_APB1ENR values -------------------------------------------------- */
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#define RCC_APB1ENR_DACEN (1 << 29)
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#define RCC_APB1ENR_I2C3EN (1 << 30)
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#define RCC_APB1ENR_DAC1EN (1 << 29)
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#define RCC_APB1ENR_PWREN (1 << 28)
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#define RCC_APB1ENR_DAC2EN (1 << 26)
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#define RCC_APB1ENR_CANEN (1 << 25)
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#define RCC_APB1ENR_USBEN (1 << 23)
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#define RCC_APB1ENR_I2C2EN (1 << 22)
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@ -305,12 +316,15 @@
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#define RCC_AHBRSTR_ADC34RST (1 << 29)
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#define RCC_AHBRSTR_ADC12RST (1 << 28)
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#define RCC_AHBRSTR_TSCRST (1 << 24)
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#define RCC_AHBRSTR_IOPGRST (1 << 23)
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#define RCC_AHBRSTR_IOPFRST (1 << 22)
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#define RCC_AHBRSTR_IOPERST (1 << 21)
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#define RCC_AHBRSTR_IOPDRST (1 << 20)
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#define RCC_AHBRSTR_IOPCRST (1 << 19)
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#define RCC_AHBRSTR_IOPBRST (1 << 18)
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#define RCC_AHBRSTR_IOPARST (1 << 17)
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#define RCC_AHBRSTR_IOPHRST (1 << 16)
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#define RCC_AHBRSTR_FMCRST (1 << 5)
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/* --- RCC_CFGR2 values ---------------------------------------------------- */
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/* ADC34PRES: ADC34 prescaler */
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@ -451,13 +465,16 @@ enum rcc_periph_clken {
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RCC_DMA2 = _REG_BIT(0x14, 1),/*0178*/
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RCC_SRAM = _REG_BIT(0x14, 2),/*0178*/
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RCC_FLTIF = _REG_BIT(0x14, 4),/*0178*/
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RCC_FMC = _REG_BIT(0x14, 5),/*0178*/
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RCC_CRC = _REG_BIT(0x14, 6),/*0178*/
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RCC_GPIOH = _REG_BIT(0x14, 16),/*0178*/
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RCC_GPIOA = _REG_BIT(0x14, 17),/*0178*/
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RCC_GPIOB = _REG_BIT(0x14, 18),/*0178*/
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RCC_GPIOC = _REG_BIT(0x14, 19),/*0178*/
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RCC_GPIOD = _REG_BIT(0x14, 20),/*0178*/
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RCC_GPIOE = _REG_BIT(0x14, 21),/*0178*/
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RCC_GPIOF = _REG_BIT(0x14, 22),/*0178*/
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RCC_GPIOG = _REG_BIT(0x14, 23),/*0178*/
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RCC_TSC = _REG_BIT(0x14, 24),/*0178*/
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RCC_ADC12 = _REG_BIT(0x14, 28),/*01--*/
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RCC_ADC34 = _REG_BIT(0x14, 29),/*01--*/
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@ -469,10 +486,12 @@ enum rcc_periph_clken {
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RCC_SPI1 = _REG_BIT(0x18, 12),/*0178*/
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RCC_TIM8 = _REG_BIT(0x18, 13),/*01--*/
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RCC_USART1 = _REG_BIT(0x18, 14),/*0178*/
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RCC_SPI4 = _REG_BIT(0x18, 15),
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RCC_TIM15 = _REG_BIT(0x18, 16),/*0178*/
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RCC_TIM16 = _REG_BIT(0x18, 17),/*0178*/
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RCC_TIM17 = _REG_BIT(0x18, 18),/*0178*/
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RCC_TIM19 = _REG_BIT(0x18, 19),/*--78*/
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RCC_TIM20 = _REG_BIT(0x18, 20),
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RCC_DBGMCU = _REG_BIT(0x18, 22),/*--78*/
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RCC_SDADC1 = _REG_BIT(0x18, 24),/*--78*/
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RCC_SDADC2 = _REG_BIT(0x18, 25),/*--78*/
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@ -500,11 +519,11 @@ enum rcc_periph_clken {
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RCC_I2C2 = _REG_BIT(0x1C, 22),/*0178*/
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RCC_USB = _REG_BIT(0x1C, 23),/*0178*/
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RCC_CAN = _REG_BIT(0x1C, 25),/*0178*/
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RCC_DAC2 = _REG_BIT(0x1C, 26),/*--78*/
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RCC_DAC2 = _REG_BIT(0x1C, 26),
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RCC_PWR = _REG_BIT(0x1C, 28),/*0178*/
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RCC_DAC = _REG_BIT(0x1C, 29),/*12--*/
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RCC_DAC1 = _REG_BIT(0x1C, 29),/*--78*/
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RCC_CEC = _REG_BIT(0x1C, 29),/*--78*/
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RCC_DAC1 = _REG_BIT(0x1C, 29),
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RCC_CEC = _REG_BIT(0x1C, 30),/*--78*/
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RCC_I2C3 = _REG_BIT(0x1C, 30),
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};
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enum rcc_periph_rst {
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@ -515,10 +534,12 @@ enum rcc_periph_rst {
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RST_SPI1 = _REG_BIT(0x0C, 12),/*0178*/
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RST_TIM8 = _REG_BIT(0x0C, 13),/*01--*/
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RST_USART1 = _REG_BIT(0x0C, 14),/*0178*/
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RST_SPI4 = _REG_BIT(0x0C, 15),
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RST_TIM15 = _REG_BIT(0x0C, 16),/*0178*/
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RST_TIM16 = _REG_BIT(0x0C, 17),/*0178*/
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RST_TIM17 = _REG_BIT(0x0C, 18),/*0178*/
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RST_TIM19 = _REG_BIT(0x0C, 19),/*--78*/
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RST_TIM20 = _REG_BIT(0x0C, 20),
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RST_SDADC1 = _REG_BIT(0x0C, 24),/*--78*/
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RST_SDADC2 = _REG_BIT(0x0C, 25),/*--78*/
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RST_SDADC3 = _REG_BIT(0x0C, 26),/*--78*/
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@ -545,19 +566,22 @@ enum rcc_periph_rst {
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RST_I2C2 = _REG_BIT(0x10, 22),/*0178*/
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RST_USB = _REG_BIT(0x10, 23),/*0178*/
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RST_CAN = _REG_BIT(0x10, 25),/*0178*/
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RST_DAC2 = _REG_BIT(0x10, 26),/*--78*/
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RST_DAC2 = _REG_BIT(0x10, 26),
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RST_PWR = _REG_BIT(0x10, 28),/*0178*/
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RST_DAC = _REG_BIT(0x10, 29),/*01--*/
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RST_DAC1 = _REG_BIT(0x10, 29),/*--78*/
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RST_DAC1 = _REG_BIT(0x10, 29),
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RST_CEC = _REG_BIT(0x10, 30),/*--78*/
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RST_I2C3 = _REG_BIT(0x10, 30),
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/* AHB peripherals */
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RST_FMC = _REG_BIT(0x28, 5),
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RST_GPIOH = _REG_BIT(0x28, 16),
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RST_GPIOA = _REG_BIT(0x28, 17),/*0178*/
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RST_GPIOB = _REG_BIT(0x28, 18),/*0178*/
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RST_GPIOC = _REG_BIT(0x28, 19),/*0178*/
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RST_GPIOD = _REG_BIT(0x28, 20),/*0178*/
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RST_GPIOE = _REG_BIT(0x28, 21),/*0178*/
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RST_GPIOF = _REG_BIT(0x28, 22),/*0178*/
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RST_GPIOG = _REG_BIT(0x28, 23),
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RST_TSC = _REG_BIT(0x28, 24),/*0178*/
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RST_ADC12 = _REG_BIT(0x28, 28),/*01--*/
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RST_ADC34 = _REG_BIT(0x28, 29),/*01--*/
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