Commit Graph

12 Commits

Author SHA1 Message Date
Sylvain Munaut 641ac1e3ef gateware: Switch to using Vex CPU
It's a good ~ 3.5x faster than the PicoRV32 (in number of cycles),
which allows to shutdown the system clock more and reduce power
a bit as well.

Signed-off-by: Sylvain Munaut <>
2023-03-23 11:18:14 +01:00
Sylvain Munaut 2188b231be gateware: Switch clk_sys to 12 MHz
This actually helps save a bit of power (at least for sysmgr_3) since
the "always-on" clk_base is slower.

The SoC needs more time to compute frames, but the same number of
cycles so that doesn't change the power on clk_sys itself really.

This will also be helpful for upcoming commits where we switch to
a Vex that has better IPC but doesn't easily meet 24 MHz constraint.

Signed-off-by: Sylvain Munaut <>
2023-03-22 21:54:35 +01:00
Sylvain Munaut 119bc9fa1f gateware: Switch to using the _3 variant of system manager
This alone seems to reduce by ~30% the power usage of the SoC
(when USB is off).

Signed-off-by: Sylvain Munaut <>
2023-03-22 21:49:57 +01:00
Sylvain Munaut b5a4d41477 gateware/cores: Update submodules
Signed-off-by: Sylvain Munaut <>
2023-03-21 16:27:11 +01:00
Sylvain Munaut 4cba7c201b gateware/rtl: Fix sysmgr_3 reset generation
Seems that having the reset not being 1 directly causes some
issue somewhere so fix it.

Signed-off-by: Sylvain Munaut <>
2023-03-21 16:22:17 +01:00
Sylvain Munaut c21605e845 gateware/rtl: Fix sysmgr_2 PLL output order and gating
For some reasons the ports were not in order and also the gating
was applied to the wrong port.

Signed-off-by: Sylvain Munaut <>
2023-03-21 13:04:20 +01:00
Sylvain Munaut 453b3edb26 gateware: Remove debug clk_sys output
Save all the power !

Signed-off-by: Sylvain Munaut <>
2023-03-16 09:59:06 +01:00
Sylvain Munaut 6a7ee1d17a gateware: Set explicit 100K pullup for pwr_usb_n/pwr_chg_n
We want them weak in case any of this can leak back in the 5V

Signed-off-by: Sylvain Munaut <>
2023-03-16 09:59:06 +01:00
Sylvain Munaut b2d95779c6 gateware/sysmgr: Make sure sys_start _always_ forces system clock ON
Before it was only sensitive to rising edge. But for the "start" we
actually want to force it on if active to avoid race condition in the
software where:

- CPU clears the condition of the wakeup
- New wake up event happens right after it
- CPU asks for shutdown
- And then no rising edge happens because wakeup is already high

For shutdown it's good that it's rising edge dependent since the
OFF command signal _might_ stay high if the system clock shuts down

Signed-off-by: Sylvain Munaut <>
2023-03-16 09:59:06 +01:00
Sylvain Munaut 27f35141de gateware/firmware: Add better support for buttons
The press events are detected in the gateware and latched
and the firmware can just read them as "events". They also
trigger sys clock domain wake up if it was sleeping.

This is better since the 'sys' clock domain can be shutdown for
some non-negligible amount of time and it could lead to missed
presses or latency.

Signed-off-by: Sylvain Munaut <>
2023-03-16 09:59:06 +01:00
Sylvain Munaut cb8197a6c7 gateware: Add .gitignore
Signed-off-by: Sylvain Munaut <>
2023-03-12 11:07:38 +01:00
Sylvain Munaut c85dc29b06 gateware: Initial import of the FPGA gateware
Signed-off-by: Sylvain Munaut <>
2023-03-11 23:54:12 +01:00