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gateware/rtl: Fix sysmgr_2 PLL output order and gating 

For some reasons the ports were not in order and also the gating
was applied to the wrong port.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
This commit is contained in:
Sylvain Munaut 2023-03-21 13:04:20 +01:00
parent 4eb2ed52d2
commit c21605e845
1 changed files with 4 additions and 4 deletions
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8
gateware/rtl/sysmgr_2.v
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@ -86,14 +86,14 @@ module sysmgr (
.SHIFTREG_DIV_MODE (2'b00),
.PLLOUT_SELECT_PORTA ("GENCLK"),
.PLLOUT_SELECT_PORTB ("GENCLK"),
.ENABLE_ICEGATE_PORTA (1'b1),
.ENABLE_ICEGATE_PORTB (1'b0),
.ENABLE_ICEGATE_PORTA (1'b0),
.ENABLE_ICEGATE_PORTB (1'b1),
) pll_I (
.REFERENCECLK (clk_osc),
.PLLOUTCOREB (),
.PLLOUTGLOBALB (clk_usb),
.PLLOUTCOREA (clk_base),
.PLLOUTGLOBALA (),
.PLLOUTCOREB (),
.PLLOUTGLOBALB (clk_usb),
.EXTFEEDBACK (1'b0),
.DYNAMICDELAY (8'h00),
.RESETB (1'b1),