gateware/rtl: Fix sysmgr_2 PLL output order and gating

For some reasons the ports were not in order and also the gating
was applied to the wrong port.

Signed-off-by: Sylvain Munaut <>
Sylvain Munaut 2023-03-21 13:04:20 +01:00
parent 4eb2ed52d2
commit c21605e845
1 changed files with 4 additions and 4 deletions

View File

@ -86,14 +86,14 @@ module sysmgr (
) pll_I (
.REFERENCECLK (clk_osc),
.PLLOUTCOREA (clk_base),
.RESETB (1'b1),