Without theses there are too many control-sets generated by yosys and
nextpnr can't find any valid placement.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
By default build full bitstream, but from env or cli, allow to only
enable RX/TX units in channel 0 to speedup dev / testing.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
The hard IP kind of sucks ... but we don't need i2c much (or at
all really) and using the hard IP is nearly free (LC-wise).
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
We have a bunch of Multiply Add units that are un-used, we can
make use of the "accumulate" part to implement the few wide
counters we have to win some LCs.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Theses syntax error are ignored by yosys but trying synopsys, it is more
strict, so fix them. Right thing to do anyway ...
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Current version has second E1 channel disabled to allow the
build to works. Works is in progress to optimize the gateware and
the fpga toolchain to allow full featured build.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
The documentation always had the rRX tick in the LSB which
is consistent with having the RX units before TX.
They can be read as 16 bit value anyway so there isn't any
performance impact.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
This is the project specific to the e1-tracer board that was
initially based on the iCEpick with a couple dev boards attached
but eventually consolidated to a proper board, which still retaining
100% electrical compatibility (and thus same gateware and firmware)
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
This is the project specific to the PMOD based early prototype.
It was used either with the icebreaker or the icebreaker-bitsy
board as host. Set BOARD variable appropriately during build.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Harald Welte
Sylvain Munaut