mirror of https://gerrit.osmocom.org/libusrp
Fixing wbx to use _refclk_freq()
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a27a7bb1f6
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0ba8eaa142
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@ -40,6 +40,7 @@ public:
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double freq_max();
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protected:
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int _refclk_divisor();
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bool _lock_detect();
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bool _set_pga(float pga_gain);
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@ -71,6 +71,12 @@ wbxng_base::~wbxng_base()
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delete d_common;
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}
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int
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wbxng_base::_refclk_divisor()
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{
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return 1;
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}
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struct freq_result_t
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wbxng_base::set_freq(double freq)
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{
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@ -83,8 +89,8 @@ wbxng_base::set_freq(double freq)
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// clamp freq
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freq_t int_freq = freq_t(std::max(freq_min(), std::min(freq, freq_max())));
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bool ok = d_common->_set_freq(int_freq*2);
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double freq_result = (double) d_common->_get_freq()/2.0;
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bool ok = d_common->_set_freq(int_freq*2, _refclk_freq());
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double freq_result = (double) d_common->_get_freq(_refclk_freq())/2.0;
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struct freq_result_t args = {ok, freq_result};
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/* Wait before reading Lock Detect*/
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@ -27,9 +27,7 @@
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#include <stdio.h>
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#define FREQ_C(freq) uint64_t(freq)
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#define INPUT_REF_FREQ FREQ_C(64e6)
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#define DIV_ROUND(num, denom) (((num) + ((denom)/2))/(denom))
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#define INPUT_REF_FREQ_2X (2*INPUT_REF_FREQ) /* input ref freq with doubler turned on */
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#define MIN_INT_DIV uint16_t(23) /* minimum int divider, prescaler 4/5 only */
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#define MAX_RF_DIV uint8_t(16) /* max rf divider, divides rf output */
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#define MIN_VCO_FREQ FREQ_C(2.2e9) /* minimum vco freq */
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@ -130,7 +128,7 @@ adf4350::_write(uint8_t addr, uint32_t data)
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}
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bool
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adf4350::_set_freq(freq_t freq)
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adf4350::_set_freq(freq_t freq, freq_t refclock_freq)
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{
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/* Set the frequency by setting int, frac, mod, r, div */
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if (freq > MAX_FREQ || freq < MIN_FREQ) return false;
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@ -147,7 +145,7 @@ adf4350::_set_freq(freq_t freq)
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d_regs->d_divider_select++; //double the divider
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}
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/* Ramp up the R divider until the N divider is at least the minimum. */
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//d_regs->d_10_bit_r_counter = INPUT_REF_FREQ*MIN_INT_DIV/freq;
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//d_regs->d_10_bit_r_counter = refclock_freq*MIN_INT_DIV/freq;
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d_regs->d_10_bit_r_counter = 2;
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uint64_t n_mod;
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do{
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@ -155,7 +153,7 @@ adf4350::_set_freq(freq_t freq)
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n_mod = freq;
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n_mod *= d_regs->d_10_bit_r_counter;
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n_mod *= d_regs->d_mod;
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n_mod /= INPUT_REF_FREQ;
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n_mod /= refclock_freq;
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/* calculate int and frac */
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d_regs->d_int = n_mod/d_regs->d_mod;
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d_regs->d_frac = (n_mod - (freq_t)d_regs->d_int*d_regs->d_mod) & uint16_t(0xfff);
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@ -169,11 +167,11 @@ adf4350::_set_freq(freq_t freq)
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}while(d_regs->d_int < min_int_div);
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/* calculate the band select so PFD is under 125 KHz */
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d_regs->d_8_bit_band_select_clock_divider_value = \
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INPUT_REF_FREQ/(FREQ_C(30e3)*d_regs->d_10_bit_r_counter) + 1;
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refclock_freq/(FREQ_C(30e3)*d_regs->d_10_bit_r_counter) + 1;
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/*
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fprintf(stderr, "Band Selection: Div %u, Freq %lu\n",
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d_regs->d_8_bit_band_select_clock_divider_value,
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INPUT_REF_FREQ/(d_regs->d_8_bit_band_select_clock_divider_value * d_regs->d_10_bit_r_counter) + 1
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refclock_freq/(d_regs->d_8_bit_band_select_clock_divider_value * d_regs->d_10_bit_r_counter) + 1
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);
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*/
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d_regs->_load_register(5);
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@ -187,7 +185,7 @@ adf4350::_set_freq(freq_t freq)
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}
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freq_t
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adf4350::_get_freq(void)
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adf4350::_get_freq(freq_t refclock_freq)
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{
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/* Calculate the freq from int, frac, mod, ref, r, div:
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* freq = (int + frac/mod) * (ref/r)
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@ -198,7 +196,7 @@ adf4350::_get_freq(void)
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temp = d_regs->d_int;
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temp *= d_regs->d_mod;
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temp += d_regs->d_frac;
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temp *= INPUT_REF_FREQ;
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temp *= refclock_freq;
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temp /= d_regs->d_mod;
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temp /= d_regs->d_10_bit_r_counter;
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temp /= (1 << d_regs->d_divider_select);
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@ -37,8 +37,8 @@ public:
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bool _get_locked();
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void _enable(bool enable);
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void _write(uint8_t addr, uint32_t data);
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bool _set_freq(freq_t freq);
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freq_t _get_freq();
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bool _set_freq(freq_t freq, freq_t refclock_freq);
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freq_t _get_freq(freq_t refclock_freq);
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freq_t _get_max_freq();
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freq_t _get_min_freq();
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