mirror of https://gerrit.osmocom.org/libusrp
205 lines
6.2 KiB
C++
205 lines
6.2 KiB
C++
//
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// Copyright 2009 Free Software Foundation, Inc.
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//
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// This file is part of GNU Radio
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//
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// GNU Radio is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either asversion 3, or (at your option)
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// any later version.
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//
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// GNU Radio is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with GNU Radio; see the file COPYING. If not, write to
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// the Free Software Foundation, Inc., 51 Franklin Street,
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// Boston, MA 02110-1301, USA.
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#ifdef HAVE_CONFIG_H
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#include <config.h>
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#endif
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#include "db_wbxng_adf4350.h"
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#include <db_base_impl.h>
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#include <stdio.h>
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#define FREQ_C(freq) uint64_t(freq)
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#define DIV_ROUND(num, denom) (((num) + ((denom)/2))/(denom))
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#define MIN_INT_DIV uint16_t(23) /* minimum int divider, prescaler 4/5 only */
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#define MAX_RF_DIV uint8_t(16) /* max rf divider, divides rf output */
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#define MIN_VCO_FREQ FREQ_C(2.2e9) /* minimum vco freq */
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#define MAX_VCO_FREQ FREQ_C(4.4e9) /* minimum vco freq */
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#define MAX_FREQ DIV_ROUND(MAX_VCO_FREQ, 1) /* upper bound freq (rf div = 1) */
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#define MIN_FREQ DIV_ROUND(MIN_VCO_FREQ, MAX_RF_DIV) /* calculated lower bound freq */
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#define CE_PIN (1 << 3)
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#define PDB_RF_PIN (1 << 2)
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#define MUX_PIN (1 << 1)
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#define LD_PIN (1 << 0)
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adf4350::adf4350(usrp_basic_sptr _usrp, int _which, int _spi_enable)
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{
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/* Initialize the pin directions. */
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d_usrp = _usrp;
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d_which = _which;
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d_spi_enable = _spi_enable;
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d_spi_format = SPI_FMT_MSB | SPI_FMT_HDR_0;
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d_regs = new adf4350_regs(this);
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/* Outputs */
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d_usrp->_write_oe(d_which, (CE_PIN | PDB_RF_PIN), (CE_PIN | PDB_RF_PIN));
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d_usrp->write_io(d_which, (CE_PIN), (CE_PIN | PDB_RF_PIN));
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/* Initialize the pin levels. */
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_enable(true);
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/* Initialize the registers. */
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d_regs->_load_register(5);
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d_regs->_load_register(4);
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d_regs->_load_register(3);
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d_regs->_load_register(2);
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d_regs->_load_register(1);
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d_regs->_load_register(0);
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}
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adf4350::~adf4350()
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{
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d_usrp->write_io(d_which, (0), (CE_PIN | PDB_RF_PIN));
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delete d_regs;
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}
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freq_t
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adf4350::_get_max_freq(void)
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{
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return MAX_FREQ;
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}
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freq_t
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adf4350::_get_min_freq(void)
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{
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return MIN_FREQ;
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}
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bool
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adf4350::_get_locked(void)
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{
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return d_usrp->read_io(d_which) & LD_PIN;
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}
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void
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adf4350::_enable(bool enable)
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{
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if (enable){ /* chip enable */
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d_usrp->write_io(d_which, (PDB_RF_PIN), (PDB_RF_PIN));
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}else{
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d_usrp->write_io(d_which, 0, (PDB_RF_PIN));
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}
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}
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void
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adf4350::_write(uint8_t addr, uint32_t data)
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{
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data |= addr;
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// create str from data here
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char s[4];
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s[0] = (char)((data >> 24) & 0xff);
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s[1] = (char)((data >> 16) & 0xff);
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s[2] = (char)((data >> 8) & 0xff);
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s[3] = (char)(data & 0xff);
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std::string str(s, 4);
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timespec t;
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t.tv_sec = 0;
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t.tv_nsec = 5e6;
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nanosleep(&t, NULL);
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d_usrp->_write_spi(0, d_spi_enable, d_spi_format, str);
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nanosleep(&t, NULL);
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//fprintf(stderr, "Wrote to WBXNG SPI address %d with data %8x\n", addr, data);
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/* pulse latch */
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//d_usrp->write_io(d_which, 1, LE_PIN);
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//d_usrp->write_io(d_which, 0, LE_PIN);
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}
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bool
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adf4350::_set_freq(freq_t freq, freq_t refclock_freq)
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{
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/* Set the frequency by setting int, frac, mod, r, div */
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if (freq > MAX_FREQ || freq < MIN_FREQ) return false;
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int min_int_div = 23;
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d_regs->d_prescaler = 0;
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if (freq > FREQ_C(3e9)) {
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min_int_div = 75;
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d_regs->d_prescaler = 1;
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}
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/* Ramp up the RF divider until the VCO is within range. */
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d_regs->d_divider_select = 0;
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while (freq < MIN_VCO_FREQ){
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freq <<= 1; //double the freq
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d_regs->d_divider_select++; //double the divider
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}
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/* Ramp up the R divider until the N divider is at least the minimum. */
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//d_regs->d_10_bit_r_counter = refclock_freq*MIN_INT_DIV/freq;
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d_regs->d_10_bit_r_counter = 2;
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uint64_t n_mod;
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do{
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d_regs->d_10_bit_r_counter++;
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n_mod = freq;
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n_mod *= d_regs->d_10_bit_r_counter;
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n_mod *= d_regs->d_mod;
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n_mod /= refclock_freq;
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/* calculate int and frac */
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d_regs->d_int = n_mod/d_regs->d_mod;
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d_regs->d_frac = (n_mod - (freq_t)d_regs->d_int*d_regs->d_mod) & uint16_t(0xfff);
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/*
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fprintf(stderr,
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"VCO %lu KHz, Int %u, Frac %u, Mod %u, R %u, Div %u\n",
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freq, d_regs->d_int, d_regs->d_frac,
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d_regs->d_mod, d_regs->d_10_bit_r_counter, (1 << d_regs->d_divider_select)
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);
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*/
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}while(d_regs->d_int < min_int_div);
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/* calculate the band select so PFD is under 125 KHz */
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d_regs->d_8_bit_band_select_clock_divider_value = \
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refclock_freq/(FREQ_C(30e3)*d_regs->d_10_bit_r_counter) + 1;
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/*
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fprintf(stderr, "Band Selection: Div %u, Freq %lu\n",
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d_regs->d_8_bit_band_select_clock_divider_value,
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refclock_freq/(d_regs->d_8_bit_band_select_clock_divider_value * d_regs->d_10_bit_r_counter) + 1
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);
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*/
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d_regs->_load_register(5);
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d_regs->_load_register(3);
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d_regs->_load_register(1);
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/* load involved registers */
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d_regs->_load_register(2);
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d_regs->_load_register(4);
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d_regs->_load_register(0); /* register 0 must be last */
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return true;
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}
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freq_t
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adf4350::_get_freq(freq_t refclock_freq)
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{
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/* Calculate the freq from int, frac, mod, ref, r, div:
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* freq = (int + frac/mod) * (ref/r)
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* Keep precision by doing multiplies first:
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* freq = (((((((int)*mod) + frac)*ref)/mod)/r)/div)
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*/
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uint64_t temp;
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temp = d_regs->d_int;
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temp *= d_regs->d_mod;
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temp += d_regs->d_frac;
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temp *= refclock_freq;
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temp /= d_regs->d_mod;
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temp /= d_regs->d_10_bit_r_counter;
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temp /= (1 << d_regs->d_divider_select);
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return temp;
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}
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