mirror of https://gerrit.osmocom.org/libusrp
You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
|
1 month ago | |
---|---|---|
contrib | 1 month ago | |
debian | 1 month ago | |
doc | 5 years ago | |
firmware | 2 years ago | |
fpga | 13 years ago | |
host | 11 months ago | |
m4 | 3 years ago | |
.gitignore | 11 months ago | |
.gitreview | 4 years ago | |
Makefile.am | 3 years ago | |
Makefile.common | 3 years ago | |
Makefile.par.gen | 5 years ago | |
Makefile.swig | 5 years ago | |
Makefile.swig.gen.t | 5 years ago | |
README | 17 years ago | |
TODO-RELEASE | 4 years ago | |
configure.ac | 4 months ago | |
git-version-gen | 4 years ago | |
usrp.inf | 17 years ago | |
usrp.iss.in | 16 years ago | |
usrp.pc.in | 5 years ago |
README
# # README -- the short version # The top level makefile handles the host code and FX2 firmware. Besides the normal gcc suite and all the auto tools, you'll need the SDCC free C compiler to build the firmware. You MUST USE VERSION 2.4.0 or VERSION 2.5.0 due to some problems with variable initialization. http://sdcc.sourceforge.net The high level interface to the USRP using our standard FPGA bitstram is contained in usrp/host/lib/usrp_standard.h If you've got doxygen installed, there are html docs in usrp/doc/html/index.html # Compiling the verilog (not required unless you're modifying it) If you want to build the FPGA .rbf file from source (not required; we provide pre-compiled .rbf files in usrp/fpga/rbf directory), you'll need Altera's no cost Quartus II development tools. We're currently building with Quartus II 5.1sp1 Web Edition. The project file is usrp/fpga/toplevel/usrp_std/usrp_std.qpf. The toplevel verilog file is usrp/fpga/toplevel/usrp_std/usrp_std.v. The bulk of the verilog modules are contained in usrp/fpga/sdr_lib