2006-08-03 04:51:51 +00:00
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/*
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* USRP - Universal Software Radio Peripheral
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*
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* Copyright (C) 2003 Free Software Foundation, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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2007-07-21 03:44:38 +00:00
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* the Free Software Foundation; either version 3 of the License, or
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2006-08-03 04:51:51 +00:00
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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2006-09-13 21:30:04 +00:00
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* Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
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2006-08-03 04:51:51 +00:00
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*/
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#include "usrp_common.h"
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#include "fpga_load.h"
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#include "delay.h"
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/*
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* setup altera FPGA serial load (PS).
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*
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* On entry:
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* don't care
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*
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* On exit:
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* ALTERA_DCLK = 0
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* ALTERA_NCONFIG = 1
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* ALTERA_NSTATUS = 1 (input)
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*/
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unsigned char
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fpga_load_begin (void)
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{
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USRP_ALTERA_CONFIG &= ~bmALTERA_BITS; // clear all bits (NCONFIG low)
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udelay (40); // wait 40 us
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USRP_ALTERA_CONFIG |= bmALTERA_NCONFIG; // set NCONFIG high
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if (UC_BOARD_HAS_FPGA){
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// FIXME should really cap this loop with a counter so we
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// don't hang forever on a hardware failure.
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while ((USRP_ALTERA_CONFIG & bmALTERA_NSTATUS) == 0) // wait for NSTATUS to go high
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;
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}
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// ready to xfer now
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return 1;
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}
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/*
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* clock out the low bit of bits.
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*
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* On entry:
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* ALTERA_DCLK = 0
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* ALTERA_NCONFIG = 1
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* ALTERA_NSTATUS = 1 (input)
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*
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* On exit:
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* ALTERA_DCLK = 0
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* ALTERA_NCONFIG = 1
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* ALTERA_NSTATUS = 1 (input)
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*/
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#if 0
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static void
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clock_out_config_byte (unsigned char bits)
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{
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unsigned char i;
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// clock out configuration byte, least significant bit first
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for (i = 0; i < 8; i++){
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USRP_ALTERA_CONFIG = ((USRP_ALTERA_CONFIG & ~bmALTERA_DATA0) | ((bits & 1) ? bmALTERA_DATA0 : 0));
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USRP_ALTERA_CONFIG |= bmALTERA_DCLK; /* set DCLK to 1 */
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USRP_ALTERA_CONFIG &= ~bmALTERA_DCLK; /* set DCLK to 0 */
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bits = bits >> 1;
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}
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}
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#else
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static void
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2019-01-11 16:44:26 +00:00
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clock_out_config_byte (unsigned char bits) __naked
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2006-08-03 04:51:51 +00:00
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{
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2019-01-11 16:44:26 +00:00
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__asm
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2006-08-03 04:51:51 +00:00
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mov a, dpl
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rrc a
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mov _bitALTERA_DATA0,c
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setb _bitALTERA_DCLK
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clr _bitALTERA_DCLK
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rrc a
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mov _bitALTERA_DATA0,c
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setb _bitALTERA_DCLK
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clr _bitALTERA_DCLK
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rrc a
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mov _bitALTERA_DATA0,c
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setb _bitALTERA_DCLK
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clr _bitALTERA_DCLK
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rrc a
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mov _bitALTERA_DATA0,c
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setb _bitALTERA_DCLK
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clr _bitALTERA_DCLK
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rrc a
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mov _bitALTERA_DATA0,c
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setb _bitALTERA_DCLK
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clr _bitALTERA_DCLK
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rrc a
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mov _bitALTERA_DATA0,c
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setb _bitALTERA_DCLK
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clr _bitALTERA_DCLK
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rrc a
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mov _bitALTERA_DATA0,c
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setb _bitALTERA_DCLK
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clr _bitALTERA_DCLK
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rrc a
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mov _bitALTERA_DATA0,c
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setb _bitALTERA_DCLK
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clr _bitALTERA_DCLK
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ret
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2019-01-11 16:44:26 +00:00
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__endasm;
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2006-08-03 04:51:51 +00:00
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}
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#endif
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static void
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clock_out_bytes (unsigned char bytecount,
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2019-01-11 16:44:26 +00:00
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unsigned char __xdata *p)
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2006-08-03 04:51:51 +00:00
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{
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while (bytecount-- > 0)
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clock_out_config_byte (*p++);
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}
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/*
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* Transfer block of bytes from packet to FPGA serial configuration port
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*
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* On entry:
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* ALTERA_DCLK = 0
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* ALTERA_NCONFIG = 1
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* ALTERA_NSTATUS = 1 (input)
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*
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* On exit:
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* ALTERA_DCLK = 0
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* ALTERA_NCONFIG = 1
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* ALTERA_NSTATUS = 1 (input)
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*/
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unsigned char
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2019-01-11 16:44:26 +00:00
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fpga_load_xfer (__xdata unsigned char *p, unsigned char bytecount)
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2006-08-03 04:51:51 +00:00
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{
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clock_out_bytes (bytecount, p);
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return 1;
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}
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/*
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* check for successful load...
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*/
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unsigned char
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fpga_load_end (void)
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{
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unsigned char status = USRP_ALTERA_CONFIG;
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if (!UC_BOARD_HAS_FPGA) // always true if we don't have FPGA
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return 1;
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if ((status & bmALTERA_NSTATUS) == 0) // failed to program
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return 0;
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if ((status & bmALTERA_CONF_DONE) == bmALTERA_CONF_DONE)
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return 1; // everything's cool
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// I don't think this should happen. It indicates that
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// programming is still in progress.
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return 0;
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}
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