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changes/39/5939/1
jcorgan 16 years ago
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  2. 1055
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  3. 25
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  4. 37
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  16. 59
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  17. 38
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  18. 42
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  19. 147
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  20. 114
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  21. 284
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  22. 240
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  23. 716
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  24. 31
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  25. 57
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  26. 32
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  27. 172
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  28. 65
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  29. 35
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  30. 37
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  31. 40
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  32. 88
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  33. 99
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  34. 44
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  35. 78
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  36. 53
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  37. 47
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  38. 86
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  39. 83
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  41. 54
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  42. 129
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  43. 123
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4
AUTHORS

@ -0,0 +1,4 @@
Matt Ettus <matt@ettus.com>
Eric Blossom <eb@comsec.com>
Michael Dickens <mdickens@nd.edu> Fast USB support for OS/X
Martin Dudok van Heel <nldudok1 at olifantasia dot com> Multi usrp synchronisation, 8 bit support

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ChangeLog

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25
Makefile.am

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#
# Copyright 2003 Free Software Foundation, Inc.
#
# This file is part of GNU Radio
#
# GNU Radio is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# GNU Radio is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with GNU Radio; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
# Boston, MA 02111-1307, USA.
#
EXTRA_DIST = usrp.pc.in usrp.iss.in usrp.inf
SUBDIRS = host firmware fpga doc

37
README

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#
# README -- the short version
#
The top level makefile handles the host code and FX2 firmware.
Besides the normal gcc suite and all the auto tools, you'll need
the SDCC free C compiler to build the firmware. You MUST
USE VERSION 2.4.0 or VERSION 2.5.0 due to some problems with variable
initialization. http://sdcc.sourceforge.net
# To get started...
./bootstrap # if you're building from CVS
./configure
make && make check && make install
The high level interface to the USRP using our standard FPGA bitstram
is contained in usrp/host/lib/usrp_standard.h
If you've got doxygen installed, there are html docs in
usrp/doc/html/index.html
# Compiling the verilog (not required unless you're modifying it)
If you want to build the FPGA .rbf file from source (not required; we
provide pre-compiled .rbf files in usrp/fpga/rbf directory), you'll
need Altera's no cost Quartus II development tools. We're currently
building with Quartus II 5.1sp1 Web Edition. The project file is
usrp/fpga/toplevel/usrp_std/usrp_std.qpf. The toplevel verilog file
is usrp/fpga/toplevel/usrp_std/usrp_std.v. The bulk of the verilog
modules are contained in usrp/fpga/sdr_lib

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doc/Makefile.am

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#
# Copyright 2001,2005 Free Software Foundation, Inc.
#
# This file is part of GNU Radio
#
# GNU Radio is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# GNU Radio is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with GNU Radio; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
# Boston, MA 02111-1307, USA.
#
include $(top_srcdir)/Makefile.common
SUBDIRS = other
man3dir = $(mandir)/man3
docdir = $(prefix)/share/doc/@PACKAGE@-@VERSION@
EXTRA_DIST = \
Doxyfile.in \
ddc.eps \
ddc.png \
usrp-block-diagram.eps \
usrp-block-diagram.png \
usrp.jpg \
usrp_guide.xml
if HAS_XMLTO
DOCBOOK_HTML_FILES=usrp_guide.html
all-local: dox docbook-html
else
DOCBOOK_HTML_FILES=
all-local: dox
endif
dox: html/index.html
html/index.html:
mkdir -p html
@DOXYGEN@
docbook-html: usrp_guide.html
usrp_guide.html: usrp_guide.xml
xmlto html-nochunks $<
install-data-local:
$(mkinstalldirs) $(DESTDIR)$(docdir)
@for i in $(top_srcdir)/usrp/README $(top_srcdir)/usrp/ChangeLog; do \
echo "$(INSTALL_DATA) $$i $(DESTDIR)$(docdir)"; \
$(INSTALL_DATA) $$i $(DESTDIR)$(docdir); \
done
mkdir -p $(DESTDIR)$(docdir)/html
@for i in $(DOCBOOK_HTML_FILES); do \
echo "$(INSTALL_DATA) $$i $(DESTDIR)$(docdir)/html"; \
$(INSTALL_DATA) $$i $(DESTDIR)$(docdir)/html; \
done
cp -r html $(DESTDIR)$(docdir)
uninstall-local:
@for i in README ChangeLog; do \
echo "$(RM) $(DESTDIR)$(docdir)/$$i;"; \
$(RM) $(DESTDIR)$(docdir)/$$i; \
done
$(RM) -fr $(DESTDIR)$(docdir)/html
clean-local:
$(RM) -fr latex html man xml $(DOCBOOK_HTML_FILES)

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doc/other/Makefile.am

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#
# Copyright 2005 Free Software Foundation, Inc.
#
# This file is part of GNU Radio
#
# GNU Radio is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# GNU Radio is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with GNU Radio; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
# Boston, MA 02111-1307, USA.
#
include $(top_srcdir)/Makefile.common
EXTRA_DIST = \
mainpage.dox

9
doc/other/mainpage.dox

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/*! \mainpage
The top level interfaces to the USRP are usrp_standard_rx and
usrp_standard_tx. Also take a look at their base classes,
usrp_basic_rx, usrp_basic_tx and usrp_basic.
See also <a href="usrp_guide.html">USRP User's and Developer's Guide</a>
*/

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<?xml version="1.0" encoding="ISO-8859-1"?>
<!DOCTYPE article PUBLIC "-//OASIS//DTD DocBook XML V4.2//EN"
"docbookx.dtd" [
]>
<article>
<articleinfo>
<title>USRP User's and Developer's Guide</title>
<author>
<firstname>Matt</firstname>
<surname>Ettus</surname>
<affiliation>
<orgname>Ettus Research LLC</orgname>
<address>
Ettus Research LLC
<street>604 Mariposa Ave</street>
<city>Mountain View</city>, <state>CA</state> <postcode>94041</postcode>
<country>USA</country>
<email>matt@ettus.com</email>
</address>
</affiliation>
</author>
<abstract>
<para>
This guide explains both basic usage of the USRP as well as how to expand it.
</para>
</abstract>
</articleinfo>
<sect1 id="intro">
<title>Introduction</title>
<para>
The Universal Software Radio Peripheral, or USRP (pronounced "usurp")
is designed to allow general purpose computers to function as high
bandwidth software radios. In essence, it serves as a digital
baseband and IF section of a radio communication system. In addition,
it has a well-defined electrical and mechanical interface to RF
front-ends (daughterboards) which can translate between that IF or
baseband and the RF bands of interest
</para>
<para>
The basic design philosophy behind the USRP has been to do all of the
waveform-specific processing, like modulation and demodulation, on the
host CPU. All of the high-speed general purpose operations like
digital up- and downconversion, decimation and interpolation are done
on the FPGA.
</para>
<para>
It is anticipated that the majority of USRP users will never need to
use anything other than the standard FPGA configuration. However, for
those users that wish to, the FPGA design may be changed or replaced.
All of the interfaces are well defined and documented.
</para>
<figure id="usrp-board">
<title>USRP with Daughterboards</title>
<mediaobject>
<imageobject><imagedata fileref="usrp.jpg" format="JPG"/></imageobject>
<caption><para>
This USRP has 2 BasicTX and 2 BasicRX boards mounted on it.
Notice that the boards on the left are rotated 180 degrees.
</para></caption>
</mediaobject>
</figure>
<sect2 id="requirements">
<title>System Requirements</title>
<para>
The USRP requires a PC or Mac with a USB2 interface.
</para>
</sect2>
<sect2 id="capabilities">
<title>Capabilities</title>
<para>
The USRP has 4 high-speed analog to digital converters (ADCs), each at
12 bits per sample, 64 million samples per second. There are also
4 high-speed digital to analog converters (DACs), each at 14 bits per
sample, 128 million samples per second. These 4 input and 4 output
channels are connected to an Altera Cyclone EP1C12 FPGA. The FPGA, in
turn, connects to a USB2 interface chip, the Cypress FX2, and on to the
computer. The USRP connects to the computer via a high speed USB2
interface only, and will not work with USB1.1.
</para>
<figure id="usrp-block-diagram-fig"><title>Universal Software Radio Peripheral</title>
<mediaobject>
<imageobject><imagedata fileref="usrp-block-diagram.eps" format="EPS"/></imageobject>
<imageobject><imagedata fileref="usrp-block-diagram.png" format="PNG"/></imageobject>
<caption><para></para></caption>
</mediaobject>
</figure>
</sect2>
</sect1>
<sect1 id="getting-started">
<title>Getting Started</title>
<sect2 id="the-code">
<title>Getting all the Software</title>
<para>
The first step in using your USRP system is to get all of GNU Radio installed. This can
sometimes be a daunting process, as there are several other libraries which will need to be
installed first.
</para>
<sect3 id="dependencies">
<title>Library Dependencies</title>
<itemizedlist>
<listitem>
<para>SWIG</para>
<para>
We use SWIG (Simple Wrapper Interface Generator) to tie together the C++ and Python code
in the GNU Radio system. We require that you have version 1.3.24 or newer. You'll
probably have to compile it from source, which you can find here: <ulink url="http://www.swig.org">SWIG</ulink>
</para>
</listitem>
<listitem>
<para>FFTW</para>
<para>
FFTW is the library which GNU Radio uses for FFTs. GNU Radio requires version 3.0.1 or
newer, and it must be compiled for single precision. You can get it from the
<ulink url="http://www.fftw.org">FFTW Homepage</ulink>
</para>
</listitem>
<listitem>
<para>Boost Library</para>
<para>
Boost provides several low-level structures used in our C++ code. If it is not included in
your OS distribution, you can get it here: <ulink url="http://boost.org">Boost</ulink>
</para>
</listitem>
<listitem>
<para>CPP Unit</para>
<para>
CPPUnit provides our unit-testing framework. This creates automated tests to insure that
code does not break when changes are made. Get it at the <ulink url="http://cppunit.sf.net">
CPP Unit Homepage</ulink>
</para>
</listitem>
</itemizedlist>
</sect3>
<sect3 id="getting-gradio">
<title>Getting GNU Radio and the USRP code</title>
<para>
There are several packages of software which make up GNU Radio and the USRP support software.
Links to the latest versions of each can be found on the GNU Radio Wiki at
<ulink url="http://comsec.com/wiki?GnuRadio2.X">Download Links</ulink>. Gr-build
can greatly simplify the installation process, and its use it highly recommended.
</para>
</sect3>
<sect3 id="cvs">
<title>Following CVS Development</title>
<para>
Development for the USRP proceeds very quickly at times, so some users may want to keep up with
the latest by following the CVS trees. There are three separate software repositories
which contain various parts of the USRP system.
<itemizedlist>
<listitem>
<para>
USRP-HW, containing the hardware and FPGA designs.
</para>
<para>
All of the schematics in this repository were created in
<ulink url="http://www.geda.seul.org">gEDA</ulink>. The board
layouts were created in <ulink url="http://pcb.sf.net">PCB</ulink>.
Verilog designs are compiled in Quartus II Web Edition from
<ulink url="http://www.altera.com">Altera</ulink>.
</para>
</listitem>
<listitem>
<para>
<ulink url="https://sourceforge.net/cvs/?group_id=22397">USRP-SW</ulink>,
USRP-SW, containing firmware and host drivers for the USRP
</para>
<para>
Host side drivers and firmware which runs in the USB2 interface chip on the board.
</para>
</listitem>
<listitem>
<para>
<ulink url="http://comsec.com/wiki?CvsAccess">GNU Radio/gr-usrp</ulink>
which contains the GNU Radio interface to the USRP
</para>
</listitem>
</itemizedlist>
</para>
</sect3>
</sect2>
<sect2 id="usrp-start">
<title>Using your USRP</title>
<sect3 id="physical">
<title>Mechanical Connection</title>
<para>
The USRP ships with a complete set of standoffs, nuts and bolts. There are 20 standoffs,
M3x10mm M-F, of which 4 are intended to be used as "feet" for the USRP. Place them in the 4
corner holes on the main board, inserting the male part from below. The remaining 16
are used to hold the daughterboards in place. Four of them should be connected to the male
portion of the 4 standoffs already inserted from below. The remaining 12 should be
connected to the board with the 12 M3x6mm screws from below. At this point there should be
16 standoffs on the board with the male ends up to serve as a guide for the daughterboards.
The 16 M3 nuts are used to fasten the daughterboards down to the main board.
</para>
<para>
The USRP accomodates 2 TX and 2 RX daughterboards. The placement of the standoffs is designed
to prevent the accidental incorrect connection of daughterboards. The 2 sides of the USRP have
their daughterboard slots rotated 180 degrees. The USRP should not be operated without
standoffs, and daughterboards should never be connected or removed while power is applied.
</para>
</sect3>
<sect3 id="electrical">
<title>Electrical Connections</title>
<para>
The USRP is powered by a 6V 4A power converter included in the kit. The converter is
capable of 90-260 Vac, 50/60 Hz operation, and so should work in any country.
If there is a need to use another power supply, the connector is a standard 2.1mm/5.5mm
DC power connector. The USRP itself only needs 5V at 2A, but a 6V supply was chosen to
accomodate future daughterboards. Extra power supplies are available from Ettus Research.
</para>
<para>
The included USB cable should be connected to a USB2-capable socket on a computer. The USRP
does not support USB 1.1 operation at this time.
</para>
</sect3>
<sect3 id="diagnostics">
<title>Troubleshooting</title>
<para>
When first powered up, an LED on the USRP should be flashing at about 3-4x per second.
This indicates that the processor is running, and has put the device in a low power mode.
Once firmware has been downloaded to the USRP, the LED will blink at a slower rate.
If there is no blinking LED, check all power connections, and check for continuity
in the power fuse (F501, near the power connector). If the fuse needs replacement, it
is size 0603, 3 amps.
</para>
</sect3>
</sect2>
</sect1>
<sect1 id="fpga">
<title>FPGA</title>
<sect2 id="fpga-std">
<title>Standard FPGA Configuration</title>
<para>
In the standard fpga configuration, usrp_std, all samples sent over
the USB interface are in 16-bit signed integers in IQ format. When
there are multiple channels (up to 4), the channels are interleaved.
For example, with 4 channels, the sequence would be I0 Q0 I1 Q1 I2 Q2
I3 Q3 I0 Q0, etc.
</para>
<para>
The USRP can operate in full duplex mode. When in this mode, the
transmit and receive sides are completely independent of one another.
The only consideration is that the combined data rate over the bus
must be 32 Megabytes per second or less. The multiple RX channels
(1,2, or 4) must all be the same data rate (i.e. same decimation
ratio). The same applies to the 1,2, or TX channels, which each must
be at the same data rate (which may be different from the RX rate).
</para>
<para>
On the RX side, each of the 4 ADCs can be routed to either of I or the
Q input of any of the 4 downconverters. This allows for having
multiple channels selected out of the same ADC sample stream.
</para>
<para>
The digital upconverters (DUCs) on the transmit side are actually
contained in the AD9862 CODEC chips, not in the FPGA. The only
transmit signal processing blocks in the FPGA are the interpolators.
The interpolator outputs can be routed to any of the 4 CODEC inputs.
</para>
<figure id="ddc-fig"><title>Digital Down Converter Block Diagram</title>
<mediaobject>
<imageobject><imagedata fileref="ddc.eps" format="EPS"/></imageobject>
<imageobject><imagedata fileref="ddc.png" format="PNG"/></imageobject>
<caption><para></para></caption>
</mediaobject>
</figure>
</sect2>
</sect1>
<sect1 id="dboard-int">
<title>Daughterboard Interface</title>
<sect2 id="power-int">
<title>Power</title>
<para>
Daughterboards are provided with clean regulated 3.3V for the analog
and digital sections. Additionally there is a 6V connection straight from
the wall supply which is intended to supply a 5V LDO regulator. All daughterboards
may draw a combined total of 1.5 A.
</para>
</sect2>
<sect2 id="logical-int">
<title>Logical Interface</title>
<para>
There are slots for 2 TX daughterboards, labeled TXA and TXB, and 2
corresponding RX daughterboards, RXA and RXB. Each daughterboard slot has
access to 2 of the 4 high-speed data converter analog signals (DAC outputs
for TX, ADC inputs for RX). This allows each daughterboard which uses real
(not IQ) sampling to have 2 independent RF sections, and 2 antennas
(4 total for the system). If IQ sampling is used, each board can support
a single RF section, for a total of 2 for the whole system.
</para>
<para>
No antialias or reconstruction filtering is provided on the USRP motherboard.
This allows for maximum flexibility in frequency planning for the
daughterboards. The analog input bandwidth of the ADCs is over 200 MHz, so
IF frequencies up to that high may be chosen. If several decibels of loss
is tolerable, and IF frequency as high as 500 MHz can be used.
</para>
<para>
Every daughterboard has an I2C EEPROM (24LC024 or 24LC025) onboard
which identifies the board to the system. This allows the host
software to automatically set up the system properly based on the
installed daughterboard. The EEPROM may also store calibration values
like DC offsets or IQ imbalances. If this EEPROM is not programmed, a
warning message is printed every time USRP software is run.
</para>
</sect2>
<sect2 id="analog-int">
<title>Analog Interface</title>
<para>
Each RX daughterboard has 2 differential analog inputs
(VINP_A/VINN_A and VINP_B/VINN_B) which are sampled at a rate of 64 MS/s.
The input impedance is approximately 1Kohm.
The motherboard has a software-controllable programmable gain amplifier
on these inputs, with 0 to 20 dB of gain. With gain set to zero, full
scale inputs are 2 Volts peak-to-peak differential. When set to 20 dB,
only .2 V pk-pk differential is needed to reach full scale.
</para>
<para>
If signals are AC-coupled, there is no need to provide DC bias as long as the
internal buffer is turned on. It will provide an approximately 2V bias.
If signals are DC-couple, a DC bias of Vdd/2 (1.65V) should be provided to
both the positive and negative inputs, and the internal buffer should be turned off.
VREF provides a clean 1 V reference.
</para>
<para>
Each TX daughterboard has a pair of differential analog outputs which are
updated at 128 MS/s. The signals (IOUTP_A/IOUTN_A and IOUTP_B/IOUTN_B) are
current-output, each varying between 0 and 20 mA. Since they are high-impedance,
they can be converted into differential voltages with a resistor.
</para>
<para>
In addition to the high-speed signals, each daughterboard has exclusive access to 2 low-speed ADC inputs
(labeled AUX_ADC_A and AUX_ADC_B) which can be read from software.
These are useful for sensing RSSI signal levels, temperatures, bias
levels, etc. Additionally, each board has shared access to 4 low-speed DAC
signals, labeled AUX_DAC_A through AUX_DAC_D. RXA and TXA share one set
of these 4 lines, and RXB and TXB share their own independent set. These
signals are useful for controlling gain of variable-gain amplifiers, for example.
AUX_ADC_REF provides a reference level for gain setting if it is necessary.
</para>
</sect2>
<sect2 id="dig-int">
<title>Digital Interface</title>
<para></para>
</sect2>
<sect2 id="mech-int">
<title>Connector Pinouts</title>
<table frame='all'><title>RX DBoard Connector</title>
<tgroup cols='3' align='left' colsep='1' rowsep='1'>
<thead>
<row>
<entry>Pin #</entry>
<entry>Name</entry>
<entry>Description</entry>
</row>
</thead>
<tbody>
<row>
<entry>1</entry>
<entry>power</entry>
<entry>This is power</entry>
</row>
<row>
<entry>c1</entry>
<entry>c4</entry>
</row>
<row>
<entry>d1</entry>
<entry>d4</entry>
<entry>d5</entry>
</row>
</tbody>
</tgroup>
</table>
</sect2>
</sect1>
<sect1 id="dboards">
<title>Available Daughterboards</title>
<sect2 id="basicrx">
<title>BasicRX</title>
<para>
</para>
</sect2>
<sect2 id="basictx">
<title>BasicTX</title>
<para>
</para>
</sect2>
</sect1>
</article>

22
firmware/Makefile.am

@ -0,0 +1,22 @@
#
# Copyright 2003 Free Software Foundation, Inc.
#
# This file is part of GNU Radio
#
# GNU Radio is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# GNU Radio is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with GNU Radio; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
# Boston, MA 02111-1307, USA.
#
SUBDIRS = include lib src

59
firmware/include/Makefile.am

@ -0,0 +1,59 @@
#
# Copyright 2003 Free Software Foundation, Inc.
#
# This file is part of GNU Radio
#
# GNU Radio is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# GNU Radio is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with GNU Radio; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
# Boston, MA 02111-1307, USA.
#
include_HEADERS = \
usrp_i2c_addr.h \
usrp_spi_defs.h
noinst_HEADERS = \
delay.h \
fpga_regs_common.h \
fpga_regs_common.v \
fpga_regs_standard.h \
fpga_regs_standard.v \
fpga_regs0.h \
fx2regs.h \
fx2utils.h \
i2c.h \
isr.h \
syncdelay.h \
timer.h \
usb_common.h \
usb_descriptors.h \
usb_requests.h \
usrp_commands.h \
usrp_config.h \
usrp_ids.h \
usrp_interfaces.h
CODE_GENERATOR = \
generate_regs.py
EXTRA_DIST = \
$(CODE_GENERATOR)
fpga_regs_common.v: fpga_regs_common.h generate_regs.py
PYTHONPATH=$(top_srcdir)/usrp/firmware/include $(srcdir)/generate_regs.py $< $@
fpga_regs_standard.v: fpga_regs_standard.h generate_regs.py
PYTHONPATH=$(top_srcdir)/usrp/firmware/include $(srcdir)/generate_regs.py $< $@

38
firmware/include/delay.h

@ -0,0 +1,38 @@
/* -*- c++ -*- */
/*
* Copyright 2003 Free Software Foundation, Inc.
*
* This file is part of GNU Radio
*
* GNU Radio is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* GNU Radio is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GNU Radio; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
* Boston, MA 02111-1307, USA.
*/
#ifndef _DELAY_H_
#define _DELAY_H_
/*
* delay for approximately usecs microseconds
* Note limit of 255 usecs.
*/
void udelay (unsigned char usecs);
/*
* delay for approximately msecs milliseconds
*/
void mdelay (unsigned short msecs);
#endif /* _DELAY_H_ */

42
firmware/include/fpga_regs0.h

@ -0,0 +1,42 @@
/* -*- c++ -*- */
/*
* Copyright 2003 Free Software Foundation, Inc.
*
* This file is part of GNU Radio
*
* GNU Radio is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* GNU Radio is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GNU Radio; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
* Boston, MA 02111-1307, USA.
*/
#ifndef _FPGA_REGS0_H_
#define _FPGA_REGS0_H_
#define FR_RX_FREQ_0 0
#define FR_RX_FREQ_1 1
#define FR_RX_FREQ_2 2
#define FR_RX_FREQ_3 3
#define FR_TX_FREQ_0 4
#define FR_TX_FREQ_1 5
#define FR_TX_FREQ_2 6
#define FR_TX_FREQ_3 7
#define FR_COMBO 8
#define FR_ADC_CLK_DIV 128 // pseudo regs mapped to FR_COMBO by f/w
#define FR_EXT_CLK_DIV 129
#define FR_INTERP 130
#define FR_DECIM 131
#endif

147
firmware/include/fpga_regs_common.h

@ -0,0 +1,147 @@
/* -*- c++ -*- */
/*
* Copyright 2003,2004 Free Software Foundation, Inc.
*
* This file is part of GNU Radio
*
* GNU Radio is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* GNU Radio is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GNU Radio; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
* Boston, MA 02111-1307, USA.
*/
#ifndef INCLUDED_FPGA_REGS_COMMON_H
#define INCLUDED_FPGA_REGS_COMMON_H
// This file defines registers common to all FPGA configurations.
// Registers 0 to 31 are reserved for use in this file.
// The FPGA needs to know the rate that samples are coming from and
// going to the A/D's and D/A's. div = 128e6 / sample_rate
#define FR_TX_SAMPLE_RATE_DIV 0
#define FR_RX_SAMPLE_RATE_DIV 1
// 2 is available.
// 3 is available.
#define FR_MASTER_CTRL 4 // master enable and reset controls
# define bmFR_MC_ENABLE_TX (1 << 0)
# define bmFR_MC_ENABLE_RX (1 << 1)
# define bmFR_MC_RESET_TX (1 << 2)
# define bmFR_MC_RESET_RX (1 << 3)
// i/o direction registers for pins that go to daughterboards.
// Setting the bit makes it an output from the FPGA to the d'board.
// top 16 is mask, low 16 is value
#define FR_OE_0 5 // slot 0
#define FR_OE_1 6
#define FR_OE_2 7
#define FR_OE_3 8
// i/o registers for pins that go to daughterboards.
// top 16 is a mask, low 16 is value
#define FR_IO_0 9 // slot 0
#define FR_IO_1 10
#define FR_IO_2 11
#define FR_IO_3 12
#define FR_MODE 13
# define bmFR_MODE_NORMAL 0
# define bmFR_MODE_LOOPBACK (1 << 0) // enable digital loopback
# define bmFR_MODE_RX_COUNTING (1 << 1) // Rx is counting
# define bmFR_MODE_RX_COUNTING_32BIT (1 << 2) // Rx is counting with a 32 bit counter
// low and high 16 bits are multiplexed across channel I and Q
// If the corresponding bit is set, internal FPGA debug circuitry
// controls the i/o pins for the associated bank of daughterboard
// i/o pins. Typically used for debugging FPGA designs.
#define FR_DEBUG_EN 14
# define bmFR_DEBUG_EN_TX_A (1 << 0) // debug controls TX_A i/o
# define bmFR_DEBUG_EN_RX_A (1 << 1) // debug controls RX_A i/o
# define bmFR_DEBUG_EN_TX_B (1 << 2) // debug controls TX_B i/o
# define bmFR_DEBUG_EN_RX_B (1 << 3) // debug controls RX_B i/o
// If the corresponding bit is set, enable the automatic DC
// offset correction control loop.
//
// The 4 low bits are significant:
//
// ADC0 = (1 << 0)
// ADC1 = (1 << 1)
// ADC2 = (1 << 2)
// ADC3 = (1 << 3)
//
// This control loop works if the attached daugherboard blocks DC.
// Currently all daughterboards do block DC. This includes:
// basic rx, dbs_rx, tv_rx, flex_xxx_rx.
#define FR_DC_OFFSET_CL_EN 15 // DC Offset Control Loop Enable
// offset corrections for ADC's and DAC's (2's complement)
#define FR_ADC_OFFSET_0 16
#define FR_ADC_OFFSET_1 17
#define FR_ADC_OFFSET_2 18
#define FR_ADC_OFFSET_3 19
// ------------------------------------------------------------------------
// Automatic Transmit/Receive switching
//
// If automatic transmit/receive (ATR) switching is enabled in the
// FR_ATR_CTL register, the presence or absence of data in the FPGA
// transmit fifo selects between two sets of values for each of the 4
// banks of daughterboard i/o pins.
//
// Each daughterboard slot has 3 16-bit registers associated with it:
// FR_ATR_MASK_*, FR_ATR_TXVAL_* and FR_ATR_RXVAL_*
//
// FR_ATR_MASK_{0,1,2,3}:
//
// These registers determine which of the daugherboard i/o pins are
// affected by ATR switching. If a bit in the mask is set, the
// corresponding i/o bit is controlled by ATR, else it's output
// value comes from the normal i/o pin output register:
// FR_IO_{0,1,2,3}.
//
// FR_ATR_TXVAL_{0,1,2,3}:
// FR_ATR_RXVAL_{0,1,2,3}:
//
// If the Tx fifo contains data, then the bits from TXVAL that are
// selected by MASK are output. Otherwise, the bits from RXVAL that
// are selected by MASK are output.
#define FR_ATR_MASK_0 20 // slot 0
#define FR_ATR_TXVAL_0 21
#define FR_ATR_RXVAL_0 22
#define FR_ATR_MASK_1 23 // slot 1
#define FR_ATR_TXVAL_1 24
#define FR_ATR_RXVAL_1 25
#define FR_ATR_MASK_2 26 // slot 2
#define FR_ATR_TXVAL_2 27
#define FR_ATR_RXVAL_2 28
#define FR_ATR_MASK_3 29 // slot 3
#define FR_ATR_TXVAL_3 30
#define FR_ATR_RXVAL_3 31
#endif /* INCLUDED_FPGA_REGS_COMMON_H */

114
firmware/include/fpga_regs_common.v

@ -0,0 +1,114 @@
//
// This file is machine generated from fpga_regs_common.h
// Do not edit by hand; your edits will be overwritten.
//
// This file defines registers common to all FPGA configurations.
// Registers 0 to 31 are reserved for use in this file.
// The FPGA needs to know the rate that samples are coming from and
// going to the A/D's and D/A's. div = 128e6 / sample_rate
`define FR_TX_SAMPLE_RATE_DIV 7'd0
`define FR_RX_SAMPLE_RATE_DIV 7'd1
// 2 is available.
// 3 is available.
`define FR_MASTER_CTRL 7'd4 // master enable and reset controls
// i/o direction registers for pins that go to daughterboards.
// Setting the bit makes it an output from the FPGA to the d'board.
// top 16 is mask, low 16 is value
`define FR_OE_0 7'd5 // slot 0
`define FR_OE_1 7'd6
`define FR_OE_2 7'd7
`define FR_OE_3 7'd8
// i/o registers for pins that go to daughterboards.
// top 16 is a mask, low 16 is value
`define FR_IO_0 7'd9 // slot 0
`define FR_IO_1 7'd10
`define FR_IO_2 7'd11
`define FR_IO_3 7'd12
`define FR_MODE 7'd13
// If the corresponding bit is set, internal FPGA debug circuitry
// controls the i/o pins for the associated bank of daughterboard
// i/o pins. Typically used for debugging FPGA designs.
`define FR_DEBUG_EN 7'd14
// If the corresponding bit is set, enable the automatic DC
// offset correction control loop.
//
// The 4 low bits are significant:
//
// ADC0 = (1 << 0)
// ADC1 = (1 << 1)
// ADC2 = (1 << 2)
// ADC3 = (1 << 3)
//
// This control loop works if the attached daugherboard blocks DC.
// Currently all daughterboards do block DC. This includes:
// basic rx, dbs_rx, tv_rx, flex_xxx_rx.
`define FR_DC_OFFSET_CL_EN 7'd15 // DC Offset Control Loop Enable
// offset corrections for ADC's and DAC's (2's complement)
`define FR_ADC_OFFSET_0 7'd16
`define FR_ADC_OFFSET_1 7'd17
`define FR_ADC_OFFSET_2 7'd18
`define FR_ADC_OFFSET_3 7'd19
// ------------------------------------------------------------------------
// Automatic Transmit/Receive switching
//
// If automatic transmit/receive (ATR) switching is enabled in the
// FR_ATR_CTL register, the presence or absence of data in the FPGA
// transmit fifo selects between two sets of values for each of the 4
// banks of daughterboard i/o pins.
//
// Each daughterboard slot has 3 16-bit registers associated with it:
// FR_ATR_MASK_*, FR_ATR_TXVAL_* and FR_ATR_RXVAL_*
//
// FR_ATR_MASK_{0,1,2,3}:
//
// These registers determine which of the daugherboard i/o pins are
// affected by ATR switching. If a bit in the mask is set, the
// corresponding i/o bit is controlled by ATR, else it's output
// value comes from the normal i/o pin output register:
// FR_IO_{0,1,2,3}.
//
// FR_ATR_TXVAL_{0,1,2,3}:
// FR_ATR_RXVAL_{0,1,2,3}:
//
// If the Tx fifo contains data, then the bits from TXVAL that are
// selected by MASK are output. Otherwise, the bits from RXVAL that
// are selected by MASK are output.
`define FR_ATR_MASK_0 7'd20 // slot 0
`define FR_ATR_TXVAL_0 7'd21
`define FR_ATR_RXVAL_0 7'd22
`define FR_ATR_MASK_1 7'd23 // slot 1
`define FR_ATR_TXVAL_1 7'd24
`define FR_ATR_RXVAL_1 7'd25
`define FR_ATR_MASK_2 7'd26 // slot 2
`define FR_ATR_TXVAL_2 7'd27
`define FR_ATR_RXVAL_2 7'd28
`define FR_ATR_MASK_3 7'd29 // slot 3
`define FR_ATR_TXVAL_3 7'd30
`define FR_ATR_RXVAL_3 7'd31

284
firmware/include/fpga_regs_standard.h

@ -0,0 +1,284 @@
/* -*- c++ -*- */
/*
* Copyright 2003,2004,2006 Free Software Foundation, Inc.
*
* This file is part of GNU Radio
*
* GNU Radio is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* GNU Radio is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GNU Radio; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
* Boston, MA 02111-1307, USA.
*/
#ifndef INCLUDED_FPGA_REGS_STANDARD_H
#define INCLUDED_FPGA_REGS_STANDARD_H
// Register numbers 0 to 31 are reserved for use in fpga_regs_common.h.
// Registers 64 to 79 are available for custom FPGA builds.
// DDC / DUC
#define FR_INTERP_RATE 32 // [1,1024]
#define FR_DECIM_RATE 33 // [1,256]
// DDC center freq
#define FR_RX_FREQ_0 34
#define FR_RX_FREQ_1 35
#define FR_RX_FREQ_2 36
#define FR_RX_FREQ_3 37
// See below for DDC Starting Phase
// ------------------------------------------------------------------------
// configure FPGA Rx mux
//
// 3 2 1
// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
// +-----------------------+-------+-------+-------+-------+-+-----+
// | must be zero | Q3| I3| Q2| I2| Q1| I1| Q0| I0|Z| NCH |
// +-----------------------+-------+-------+-------+-------+-+-----+
//
// There are a maximum of 4 digital downconverters in the the FPGA.
// Each DDC has two 16-bit inputs, I and Q, and two 16-bit outputs, I & Q.
//
// DDC I inputs are specified by the two bit fields I3, I2, I1 & I0
//
// 0 = DDC input is from ADC 0
// 1 = DDC input is from ADC 1
// 2 = DDC input is from ADC 2
// 3 = DDC input is from ADC 3
//
// If Z == 1, all DDC Q inputs are set to zero
// If Z == 0, DDC Q inputs are specified by the two bit fields Q3, Q2, Q1 & Q0
//
// NCH specifies the number of complex channels that are sent across
// the USB. The legal values are 1, 2 or 4, corresponding to 2, 4 or
// 8 16-bit values.
#define FR_RX_MUX 38
// ------------------------------------------------------------------------
// configure FPGA Tx Mux.
//
// 3 2 1
// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
// +-----------------------+-------+-------+-------+-------+-+-----+
// | | DAC3 | DAC2 | DAC1 | DAC0 |0| NCH |
// +-----------------------------------------------+-------+-+-----+
//
// NCH specifies the number of complex channels that are sent across
// the USB. The legal values are 1 or 2, corresponding to 2 or 4
// 16-bit values.
//
// There are two interpolators with complex inputs and outputs.
// There are four DACs. (We use the DUC in each AD9862.)
//
// Each 4-bit DACx field specifies the source for the DAC and
// whether or not that DAC is enabled. Each subfield is coded
// like this:
//
// 3 2 1 0
// +-+-----+
// |E| N |
// +-+-----+
//
// Where E is set if the DAC is enabled, and N specifies which
// interpolator output is connected to this DAC.
//
// N which interp output
// --- -------------------
// 0 chan 0 I
// 1 chan 0 Q
// 2 chan 1 I
// 3 chan 1 Q
#define FR_TX_MUX 39
// ------------------------------------------------------------------------
// REFCLK control
//
// Control whether a reference clock is sent to the daughterboards,
// and what frequency. The refclk is sent on d'board i/o pin 0.
//
// 3 2 1
// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
// +-----------------------------------------------+-+------------+
// | Reserved (Must be zero) |E| DIVISOR |
// +-----------------------------------------------+-+------------+
//
// Bit 7 -- 1 turns on refclk, 0 allows IO use
// Bits 6:0 Divider value
#define FR_TX_A_REFCLK 40
#define FR_RX_A_REFCLK 41
#define FR_TX_B_REFCLK 42
#define FR_RX_B_REFCLK 43
# define bmFR_REFCLK_EN 0x80
# define bmFR_REFCLK_DIVISOR_MASK 0x7f
// ------------------------------------------------------------------------
// DDC Starting Phase
#define FR_RX_PHASE_0 44
#define FR_RX_PHASE_1 45
#define FR_RX_PHASE_2 46
#define FR_RX_PHASE_3 47
// ------------------------------------------------------------------------
// Tx data format control register
//
// 3 2 1
// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
// +-------------------------------------------------------+-------+
// | Reserved (Must be zero) | FMT |
// +-------------------------------------------------------+-------+
//
// FMT values:
#define FR_TX_FORMAT 48
# define bmFR_TX_FORMAT_16_IQ 0 // 16-bit I, 16-bit Q
// ------------------------------------------------------------------------
// Rx data format control register
//
// 3 2 1
// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
// +-----------------------------------------+-+-+---------+-------+
// | Reserved (Must be zero) |B|Q| WIDTH | SHIFT |
// +-----------------------------------------+-+-+---------+-------+
//
// FMT values:
#define FR_RX_FORMAT 49
# define bmFR_RX_FORMAT_SHIFT_MASK (0x0f << 0) // arithmetic right shift [0, 15]
# define bmFR_RX_FORMAT_SHIFT_SHIFT 0
# define bmFR_RX_FORMAT_WIDTH_MASK (0x1f << 4) // data width in bits [1, 16] (not all valid)
# define bmFR_RX_FORMAT_WIDTH_SHIFT 4
# define bmFR_RX_FORMAT_WANT_Q (0x1 << 9) // deliver both I & Q, else just I
# define bmFR_RX_FORMAT_BYPASS_HB (0x1 << 10) // bypass half-band filter
// The valid combinations currently are:
//
// B Q WIDTH SHIFT
// 0 1 16 0
// 0 1 8 8
// Possible future values of WIDTH = {4, 2, 1}
// 12 takes a bit more work, since we need to know packet alignment.
// ------------------------------------------------------------------------
// FIXME register numbers 50 to 63 are available
// ------------------------------------------------------------------------
// Registers 64 to 79 are reserved for user custom FPGA builds.
// The standard USRP software will not touch these.
#define FR_USER_0 64
#define FR_USER_1 65
#define FR_USER_2 66
#define FR_USER_3 67
#define FR_USER_4 68
#define FR_USER_5 69
#define FR_USER_6 70
#define FR_USER_7 71
#define FR_USER_8 72
#define FR_USER_9 73
#define FR_USER_10 74
#define FR_USER_11 75
#define FR_USER_12 76
#define FR_USER_13 77
#define FR_USER_14 78
#define FR_USER_15 79
//Registers needed for multi usrp master/slave configuration
//
//Rx Master/slave control register (FR_RX_MASTER_SLAVE = FR_USER_0)
//
#define FR_RX_MASTER_SLAVE 64
#define bitnoFR_RX_SYNC 0
#define bitnoFR_RX_SYNC_MASTER 1
#define bitnoFR_RX_SYNC_SLAVE 2
# define bmFR_RX_SYNC (1 <<bitnoFR_RX_SYNC) //1 If this is a master "sync now" and send sync to slave.
// If this is a slave "sync now" (testing purpose only)
// Sync is allmost the same as reset (clear all counters and buffers)
// except that the io outputs and settings don't get reset (otherwise it couldn't send the sync to the slave)
//0 Normal operation
# define bmFR_RX_SYNC_MASTER (1 <<bitnoFR_RX_SYNC_MASTER) //1 This is a rx sync master, output sync_rx on rx_a_io[15]
//0 This is not a rx sync master
# define bmFR_RX_SYNC_SLAVE (1 <<bitnoFR_RX_SYNC_SLAVE) //1 This is a rx sync slave, follow sync_rx on rx_a_io[bitnoFR_RX_SYNC_INPUT_IOPIN]
//0 This is not an rx sync slave.
//Caution The master settings will output values on the io lines.
//They inheritely enable these lines as output. If you have a daughtercard which uses these lines also as output then you will burn your usrp and daughtercard.
//If you set the slave bits then your usrp won't do anything if you don't connect a master.
// Rx Master/slave control register
//
// The way this is supposed to be used is connecting a (short) 16pin flatcable from an rx daughterboard in RXA master io_rx[8..15] to slave io_rx[8..15] on RXA of slave usrp
// This can be done with basic_rx boards or dbsrx boards
//dbsrx: connect master-J25 to slave-J25
//basic rx: connect J25 to slave-J25
//CAUTION: pay attention to the lineup of your connector.
//The red line (pin1) should be at the same side of the daughterboards on master and slave.
//If you turnaround the cable on one end you will burn your usrp.
//You cannot use a 16pin flatcable if you are using FLEX400 or FLEX2400 daughterboards, since these use a lot of the io pins.
//You can still link them but you must use only a 2pin or 1pin cable
//You can also use a 2-wire link. put a 2pin header on io[15],gnd of the master RXA daughterboard and connect it to io15,gnd of the slave RXA db.
//You can use a cable like the ones found with the leds on the mainbord of a PC.
//Make sure you don't twist the cable, otherwise you connect the sync output to ground.
//To be save you could also just use a single wire from master io[15] to slave io[15], but this is not optimal for signal integrity.
// Since rx_io[0] can normally be used as a refclk and is not exported on all daughterboards this line
// still has the refclk function if you use the master/slave setup (it is not touched by the master/slave settings).
// The master/slave circuitry will only use io pin 15 and does not touch any of the other io pins.
#define bitnoFR_RX_SYNC_INPUT_IOPIN 15
#define bmFR_RX_SYNC_INPUT_IOPIN (1<<bitnoFR_RX_SYNC_INPUT_IOPIN)
//TODO the output pin is still hardcoded in the verilog code, make it listen to the following define
#define bitnoFR_RX_SYNC_OUTPUT_IOPIN 15
#define bmFR_RX_SYNC_OUTPUT_IOPIN (1<<bitnoFR_RX_SYNC_OUTPUT_IOPIN)
// =======================================================================
// READBACK Registers
// =======================================================================
#define FR_RB_IO_RX_A_IO_TX_A 1 // read back a-side i/o pins
#define FR_RB_IO_RX_B_IO_TX_B 2 // read back b-side i/o pins
// ------------------------------------------------------------------------
// FPGA Capability register
//
// 3 2 1
// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
// +-----------------------------------------------+-+-----+-+-----+
// | Reserved (Must be zero) |T|NDUC |R|NDDC |
// +-----------------------------------------------+-+-----+-+-----+
//
// Bottom 4-bits are Rx capabilities
// Next 4-bits are Tx capabilities
#define FR_RB_CAPS 3
# define bmFR_RB_CAPS_NDDC_MASK (0x7 << 0) // # of digital down converters 0,1,2,4
# define bmFR_RB_CAPS_NDDC_SHIFT 0
# define bmFR_RB_CAPS_RX_HAS_HALFBAND (0x1 << 3)
# define bmFR_RB_CAPS_NDUC_MASK (0x7 << 4) // # of digital up converters 0,1,2
# define bmFR_RB_CAPS_NDUC_SHIFT 4
# define bmFR_RB_CAPS_TX_HAS_HALFBAND (0x1 << 7)
#endif /* INCLUDED_FPGA_REGS_STANDARD_H */

240
firmware/include/fpga_regs_standard.v

@ -0,0 +1,240 @@
//
// This file is machine generated from fpga_regs_standard.h
// Do not edit by hand; your edits will be overwritten.
//
// Register numbers 0 to 31 are reserved for use in fpga_regs_common.h.
// Registers 64 to 79 are available for custom FPGA builds.
// DDC / DUC
`define FR_INTERP_RATE 7'd32 // [1,1024]
`define FR_DECIM_RATE 7'd33 // [1,256]
// DDC center freq
`define FR_RX_FREQ_0 7'd34
`define FR_RX_FREQ_1 7'd35
`define FR_RX_FREQ_2 7'd36
`define FR_RX_FREQ_3 7'd37
// See below for DDC Starting Phase
// ------------------------------------------------------------------------
// configure FPGA Rx mux
//
// 3 2 1
// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
// +-----------------------+-------+-------+-------+-------+-+-----+
// | must be zero | Q3| I3| Q2| I2| Q1| I1| Q0| I0|Z| NCH |
// +-----------------------+-------+-------+-------+-------+-+-----+
//
// There are a maximum of 4 digital downconverters in the the FPGA.
// Each DDC has two 16-bit inputs, I and Q, and two 16-bit outputs, I & Q.
//
// DDC I inputs are specified by the two bit fields I3, I2, I1 & I0
//
// 0 = DDC input is from ADC 0
// 1 = DDC input is from ADC 1
// 2 = DDC input is from ADC 2
// 3 = DDC input is from ADC 3
//
// If Z == 1, all DDC Q inputs are set to zero
// If Z == 0, DDC Q inputs are specified by the two bit fields Q3, Q2, Q1 & Q0
//
// NCH specifies the number of complex channels that are sent across
// the USB. The legal values are 1, 2 or 4, corresponding to 2, 4 or
// 8 16-bit values.
`define FR_RX_MUX 7'd38
// ------------------------------------------------------------------------
// configure FPGA Tx Mux.
//
// 3 2 1
// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
// +-----------------------+-------+-------+-------+-------+-+-----+
// | | DAC3 | DAC2 | DAC1 | DAC0 |0| NCH |
// +-----------------------------------------------+-------+-+-----+
//
// NCH specifies the number of complex channels that are sent across
// the USB. The legal values are 1 or 2, corresponding to 2 or 4
// 16-bit values.
//
// There are two interpolators with complex inputs and outputs.
// There are four DACs. (We use the DUC in each AD9862.)
//
// Each 4-bit DACx field specifies the source for the DAC and
// whether or not that DAC is enabled. Each subfield is coded
// like this:
//
// 3 2 1 0
// +-+-----+
// |E| N |
// +-+-----+
//
// Where E is set if the DAC is enabled, and N specifies which
// interpolator output is connected to this DAC.
//
// N which interp output
// --- -------------------
// 0 chan 0 I
// 1 chan 0 Q
// 2 chan 1 I
// 3 chan 1 Q
`define FR_TX_MUX 7'd39
// ------------------------------------------------------------------------
// REFCLK control
//
// Control whether a reference clock is sent to the daughterboards,
// and what frequency. The refclk is sent on d'board i/o pin 0.
//
// 3 2 1
// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
// +-----------------------------------------------+-+------------+
// | Reserved (Must be zero) |E| DIVISOR |
// +-----------------------------------------------+-+------------+
//
// Bit 7 -- 1 turns on refclk, 0 allows IO use
// Bits 6:0 Divider value
`define FR_TX_A_REFCLK 7'd40
`define FR_RX_A_REFCLK 7'd41