Sylvain Munaut c756644205 gateware: no_rw_check fixes to cope with new yosys BRAM inferrence ... Signed-off-by: Sylvain Munaut <tnt@246tNt.com> Change-Id: Ic27dc22112f6603982126d447689dbe2202039c4		2022-10-04 21:34:56 +02:00
..
capcnt.v	gateware: Wrap capture/counter units and allow use of SB_MAC16	2020-10-03 20:15:28 +02:00
capcnt_sb_mac16.v	gateware: Wrap capture/counter units and allow use of SB_MAC16	2020-10-03 20:15:28 +02:00
dfu_helper.v	gateware: Initial import of all common parts	2020-09-14 10:56:49 +02:00
picorv32.v	gateware/common: Add iCE40 optimized register file for picorv32	2020-10-03 20:04:19 +02:00
picorv32_ice40_regs.v	gateware/common: Add iCE40 optimized register file for picorv32	2020-10-03 20:04:19 +02:00
soc_base.v	gateware/common: Add register stage for the 'ack' and 'rdata'	2020-10-09 13:05:53 +02:00
soc_bram.v	gateware: no_rw_check fixes to cope with new yosys BRAM inferrence	2022-10-04 21:34:56 +02:00
soc_iobuf.v	gateware: Initial import of all common parts	2020-09-14 10:56:49 +02:00
soc_picorv32_bridge.v	gateware/common: Unify a bit with other repo	2022-05-02 20:45:08 +02:00
soc_spram.v	gateware: Initial import of all common parts	2020-09-14 10:56:49 +02:00
wb_arbiter.v	gateware: Initial import of all common parts	2020-09-14 10:56:49 +02:00
wb_dma.v	gateware: Initial import of all common parts	2020-09-14 10:56:49 +02:00
wb_epbuf.v	gateware/common: Fix whitespace formatting in wb_epbuf	2020-10-28 00:43:13 +01:00