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osmo-e1-hardware
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Sylvain Munaut c756644205 gateware: no_rw_check fixes to cope with new yosys BRAM inferrence 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Change-Id: Ic27dc22112f6603982126d447689dbe2202039c4
 		2022-10-04 21:34:56 +02:00
..
build@87481ca25e gateware/build: Update submodule 2022-08-25 17:05:01 +02:00
common gateware: no_rw_check fixes to cope with new yosys BRAM inferrence 2022-10-04 21:34:56 +02:00
cores gateware: no_rw_check fixes to cope with new yosys BRAM inferrence 2022-10-04 21:34:56 +02:00
doc gateware: Initial import of all common parts 2020-09-14 10:56:49 +02:00
e1-tracer gateware: Small tweaks and add option to ignore timing failure 2020-10-09 13:26:39 +02:00
icE1usb gateware/icE1usb: Use custom I2C core by default rather than SB_I2C 2022-05-03 14:00:35 +02:00
icE1usb-proto gateware: Small tweaks and add option to ignore timing failure 2020-10-09 13:26:39 +02:00
README.md gateware/README.md: Fix typo (CERL->CERN) 2020-11-04 15:54:25 +01:00

README.md

E1 related gateware

This directory contains the iCE40 gateware for various boards hosted in this repository.

Licensing

Most of the cores/HDL in here is licensed under one of the CERN OHL 2.0 license. See the doc/ subdirectory for the full license texts and refer to each file header to know the license applicable to each file.

Some files have been imported from other projects with compatible licenses. Refer to each file header for the proper copyright and license information.

The repository also includes submodules which have their own licensing and copyright terms.