Commit Graph

2582 Commits

Author SHA1 Message Date
Karl Palsson 911d4be35b gitignore: ensure some non-generated are included
A normal git clone doesn't catch these, as it _knows_ that the files are
in the git repo and should be tracked.  However, downloading a tarball,
and adding it to a new git repo shows up the problem as important files
are simply not added, and would be dropped by git clean.

Reported-by: https://github.com/libopencm3/libopencm3/issues/1153
2020-01-04 23:01:57 +00:00
Guillaume Revaillot 9d15ac7ae7 cortex: FAULTMASK does not exist on armv6m. 2020-01-04 21:53:34 +00:00
Guillaume Revaillot db6237cd1e stm32: extract g0 exti stuff to exti_common_v2.
stm32l5 basically uses the same stuff.
2020-01-01 19:47:13 +01:00
Sam Protsenko f7a952c41a stm32: Fix typo in RCC related comments
ABP -> APB

Signed-off-by: Sam Protsenko <joe.skb7@gmail.com>
2019-12-26 13:46:30 +00:00
Karl Palsson df15b263d2 usb: hid: add a stub file for doxygen
Unlike with the doxygen source generation, we can't autoguess which of
the class files are eligible automatically.  Instead, make a stub hid
file, (which we can now start adding to, if desired) and include it in
all builds that include other class stubs.
2019-12-25 21:04:17 +00:00
Fabio Pugliese Ornellas f2f5083761 usb: Add more HID Class constants 2019-12-25 20:44:46 +00:00
Karl Palsson aabd4da3c0 stm32g0: syscfg: doc: fix missing grouping 2019-12-25 20:43:02 +00:00
Guillaume Revaillot 87dbf40cde stm32g0: rcc: group rcc_registers and registers values 2019-12-25 20:34:11 +00:00
Guillaume Revaillot f70f0d0b7b stm32g0: pwr: doc: remove duplicated ingroup 2019-12-25 20:34:11 +00:00
Guillaume Revaillot 48afe3ca67 stm32g0: flash: fix wrong comment. 2019-12-25 20:34:11 +00:00
Guillaume Revaillot ebd265ce42 stm32g0: rng: typo in header. 2019-12-25 20:34:11 +00:00
Guillaume Revaillot 169d23568f stm32: lptimer: fix documentation 2019-12-25 20:34:11 +00:00
Guillaume Revaillot 070058f80c stm32: adc: doc fix
declare chselr group in v2 single header, where adc_chselr reg is declared
2019-12-25 20:34:11 +00:00
Guillaume Revaillot e7c8f18f7c stm32: adc: group adc_registers 2019-12-25 20:34:11 +00:00
Karl Palsson 86b4cf6787 stm32h7: fix typo in doxygen description 2019-12-25 20:30:17 +00:00
Karl Palsson a5b6673b62 stm32: usart-v2: fix some doxygen linking problems 2019-12-25 20:30:03 +00:00
Brian Viele aabefeac92 stm32h7: usart: support new fifo features
Supported by H7 and G4 varieties at present.
2019-12-25 20:29:24 +00:00
Karl Palsson fa3c1df6f5 pac55xx: fix up and simplify some doxygen 2019-12-25 13:44:49 +00:00
Brian Viele a3406f100b pac55xx: gpio: Initial Implementation of PAC55xx GPIO Driver
* Conforms mostly to the STM32 GPIO API where possible.
* Supports pin configuration (direction, pull-up/down, etc.) as well
  as pinmux configuration.
* Supports set/clear/get operations to the GPIO port/pins.
* Created base doxy header and groups to align with existing formatting.
2019-12-25 13:44:35 +00:00
Karl Palsson 9598b7f424 doc: stm32:rcc: flag "better" periph enable options
The original rcc_peripheral_enable_clock aren't explicitly deprecated,
as they do let you enable multiple periphs in one call.  But they're
error prone, from user feedback, so update the docs to ensure people
know what the other options are.
2019-12-12 20:37:58 +00:00
Karl Palsson 85275fd62e stm32f1: adc: doc: drop undocumented examples
There's already example code, this was just conflicting extra code that
wasn't being included in doxygen anyway.
2019-12-12 20:36:51 +00:00
Karl Palsson 557e7aa50f doc: avoid usage of rcc_peripheral_enable_clock
Use the simpler, safer rcc_periph_clock_enable instead
2019-12-12 20:35:57 +00:00
TomasPech 4a9ba30138 stm32f4: rcc_clock_setup_pll() correctly enable PWR
Original code used the special macros for rcc_periph_clock_enable
instead of the appropraite APB1ENR bit definition.

Switch to the correct, simpler form, using the correct parameter.
2019-12-12 20:12:27 +00:00
Darrell Harmon 3c34f0033c genlink: avoid creating blank linker script if gcc fails
When piping to a file, if arm-none-eabi-gcc is not present in the path,
a blank linker script is created with genlink. After sourcing a bash
script to add GCC to the path, the linker script doesn't get rebuilt
due to a fresh timestamp despite failing to generate.
2019-12-11 09:42:05 +00:00
Mathias Nord 9af9a1dbfa stm32g0: use spi v2 2019-12-03 14:45:47 +01:00
Karl Palsson 867e38209b readme: add h7 and g0 2019-11-28 22:25:36 +00:00
Karl Palsson af384dbc7c doc: fix some broken groups uncovered while reviewing h7 code 2019-11-28 22:16:54 +00:00
Karl Palsson af8a1773b7 stm32h7: doc: fix some missing group definitions 2019-11-28 22:16:34 +00:00
Brian Viele 53302439df stm32h7: Initial introduction into libopencm3.
Updates to a base set of includes to map to the h7 include files which are
mainly based on the f7 versions for simple devices (e.g. SPI, USART, GPIO).

Custom files that have been implemented from the datasheet/ref manual include
the memory map, RCC, PWR definitions, and irq.json file for generation of
nvic files for interrupt mapping.

Additional functionality, especially PLL and tweaks for non-F7 compatible
implementations coming in future commits.

Added documentation tree configuration.

Reviewed-by: Karl Palsson <karlp@tweak.net.au>
Changed dmaX_streamX to dmaX_strX in a few places for consistency
2019-11-28 22:15:24 +00:00
Karl Palsson da0c6a6724 swm050: wdt: doxygen polish 2019-11-28 11:43:01 +00:00
Caleb Szalacinski 47b59e2df4 swm050: Adds WDT peripheral
Reviewed-by: Karl Palsson <karlp@tweak.net.au> (Fixed an &| in
wdt_set_time)
2019-11-28 11:42:31 +00:00
Brian Viele dd18b9fdbc Qorvo pac55xx: initial support
Qorvo (Nee Active Semi) PAC55xx "Intelligent Motor Control" parts,
cortex-m4 SoCs
2019-11-26 23:28:02 +00:00
Guillaume Revaillot bcfdcc09ac stm32g0: add syscfg header. 2019-11-25 20:49:20 +00:00
larchuto 0a68b012a1 stm32l4: Fix typo impacting uart4 and uart5 2019-11-21 18:59:32 +01:00
Guillaume Revaillot 38b45c8786 stm32g0: add adc.
v2 "single" peripheral with a couple of tweaks :
 - added registers to configure two additionnal advanced analog watchdog.
 - different adc sampling time time based on channel groups.
 - 8 steps adc sequence injection, using chselr/chselrmode.

And a note on the rm explaining that after every configuration change to ADC_CFGR1's
SCANDIR or CHSELRMOD or CHSELR register, user need to check that configuration
is applied before any other modification / adc conversion start.. making adc_set_reqular
a bit painfull to read..
2019-11-08 14:19:17 +00:00
Guillaume Revaillot a34da53c30 stm32g0: add dmamux
DMAMUX peripheral is a dma request router/trigger, present on g0, wb, h7 and l4+.

Basically it allows to easily map peripheral requests to whatever dma channel we
want to use (similarily to the DMA_CSELR register, but without limitation) but,
it also also adds some clever dma request synchronization and even some dma request
generation logic via internal request generator "channels", allowing some requests
chaining, or triggering reqs from non dma capable peripherals.

nb: g0 only features 1 dmamux bloc, supports 7 irq and 4 generators, l4+ supports 13
dma channels and 3 generators and h7 has two dmamuxes, with support for the 15 dma
channels and 7 generators - so as much CxCR and RGxCR register - but they are bit
to bit compatible - excluding of course the sync/sig and dma requests id mappings.
btw, currently, request generator channels are defined in common header, but maybe
we should define them in device header ? or we dont care (like for dma channels,
only defined in dma_f24 but not for other devices ?).

See ST AN5224 for more information
2019-11-08 13:47:41 +01:00
Guillaume Revaillot b9f183bf1e stm32g0: add dma.
same same, bit for bit, except not ;) - Channel request mapping now
depends on a new DMAMUX peripheral, and there's no default preset.
So, before enabling dma channel after its configuration, request
must be configured by :

dmamux_set_dma_channel_request(DMAMUX1, DMA_CHANNELx, request_number_from_datasheet);
2019-11-08 13:47:41 +01:00
Karl Palsson 7a27397b9e stm32: rtcv2: don't shift the "month tens" bit
None of the other masks are shifted, don't shift this field either.

Fixes: https://github.com/libopencm3/libopencm3/issues/1123
2019-11-06 19:45:20 +00:00
Karl Palsson 6d9139934c devices.data: add some more l0 parts 2019-10-22 10:35:04 +00:00
Karl Palsson 88b32e3ac0 devices.data: stm32f4: add all missing parts 2019-10-22 10:23:18 +00:00
Eivind Alexander Bergem af0509826d devices.data: Added stm32f410 2019-10-22 09:04:53 +02:00
Karl Palsson 2b54119b78 cm3: scs: drop all duplicate information
Keeps the best version of the documentation.

Fixes: https://github.com/libopencm3/libopencm3/pull/269
2019-10-18 22:38:16 +00:00
Karl Palsson 833da4b672 cm3: extract SCB SHPR to the SCB world it belongs to
Pull out the duplicate into the right file, keeping the newly fixed
version.
2019-10-18 22:33:23 +00:00
Karl Palsson 3ebd71b464 cm3: extract Coresight LSR/LAR definitions
Use a single point of definition for the offset, and add it where it was
missing.
2019-10-18 22:29:13 +00:00
Matt Anderson d8579dde95 CortexM0: IPR and SHPR are only word addressable
For ARMv6M, the IPR and SHPR registers are accessible only when
adddressed with a 32bit word read or write.

Currently in libopencm3 all NVIC interrupt priority register accesses
are made using an 8bit read or write, which results in the hardware
ignoring the write or always returning 0 on read.

Address this by introducing NVIC_IPR32() and SCS_SHPR32() macro and
conditional implementation of nvic_set_priority when building for
cortex-m0.

See ARMv6M developer documentation:
IPR: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0497a/Cihgjeed.html
SHPR: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0497a/CIAGECDD.html
2019-10-17 21:26:13 +00:00
Karl Palsson baa2f13592 swm050: doc: tweak peripheral apis groupings
Makes it more consistent with the other families.
2019-10-17 11:41:55 +00:00
Caleb Szalacinski 3c4ee6f4c0 SWM050: Finishes GPIO, IAP flash, sysclock, sleep/stop, and the sysctl memory map.
Updates the main memory map and the makefile.
Adds the SWM050 to devices.data, so that a linker script can be automatically generated.

Reviewed-by: Karl Palsson <karlp@tweak.net.au>
2019-10-17 11:41:33 +00:00
Bryan PEREIRA 1fbfdecb17 stm32f3: Add SPI4 BASE 2019-10-16 14:41:00 +00:00
Nicholas Rossomando 77d96a3430 stm32l0: crc: enable common code 2019-10-12 14:11:39 +00:00
Karl Palsson b5d66ee63f devices.data: add all missing stm32f3 parts
Filled missing variants, added missing families, corrected one or two
mistakes in ccm availability

Fixes: https://github.com/libopencm3/libopencm3/pull/1109
2019-10-03 11:37:47 +00:00