cm3: extract Coresight LSR/LAR definitions
Use a single point of definition for the offset, and add it where it was missing.
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@ -52,6 +52,12 @@
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#define DWT_MASK(n) MMIO32(DWT_BASE + 0x24 + (n) * 16)
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#define DWT_FUNCTION(n) MMIO32(DWT_BASE + 0x28 + (n) * 16)
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/* CoreSight Lock Status Register for this peripheral */
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#define DWT_LSR MMIO32(DWT_BASE + CORESIGHT_LSR_OFFSET)
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/* CoreSight Lock Access Register for this peripheral */
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#define DWT_LAR MMIO32(DWT_BASE + CORESIGHT_LAR_OFFSET)
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/*****************************************************************************/
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/* Register values */
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/*****************************************************************************/
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@ -45,9 +45,9 @@
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#define FPB_COMP (&MMIO32(FPB_BASE + 8))
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/* CoreSight Lock Status Register for this peripheral */
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#define FPB_LSR MMIO32(FPB_BASE + 0xFB4)
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#define FPB_LSR MMIO32(FPB_BASE + CORESIGHT_LSR_OFFSET)
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/* CoreSight Lock Access Register for this peripheral */
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#define FPB_LAR MMIO32(FPB_BASE + 0xFB0)
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#define FPB_LAR MMIO32(FPB_BASE + CORESIGHT_LAR_OFFSET)
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/* TODO: PID, CID */
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@ -48,9 +48,9 @@
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#define ITM_TCR MMIO32(ITM_BASE + 0xE80)
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/* CoreSight Lock Status Register for this peripheral */
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#define ITM_LSR MMIO32(ITM_BASE + 0xFB4)
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#define ITM_LSR MMIO32(ITM_BASE + CORESIGHT_LSR_OFFSET)
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/* CoreSight Lock Access Register for this peripheral */
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#define ITM_LAR MMIO32(ITM_BASE + 0xFB0)
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#define ITM_LAR MMIO32(ITM_BASE + CORESIGHT_LAR_OFFSET)
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/* TODO: PID, CID */
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@ -82,4 +82,22 @@
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#define ID_BASE (SCS_BASE + 0x0FD0)
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#endif
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/**
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* @defgroup coresight_registers Coresight Registers
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* @{
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* CoreSight Lock Status Registers and Lock Access Registers are
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* documented for the DWT, ITM, FPB and TPIU peripherals
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*/
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#define CORESIGHT_LSR_OFFSET 0xfb4
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#define CORESIGHT_LAR_OFFSET 0xfb0
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/** CoreSight Lock Status Register lock status bit */
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#define CORESIGHT_LSR_SLK (1<<1)
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/** CoreSight Lock Status Register lock availability bit */
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#define CORESIGHT_LSR_SLI (1<<0)
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/** CoreSight Lock Access key, common for all */
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#define CORESIGHT_LAR_KEY 0xC5ACCE55
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/**@}*/
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#endif
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@ -334,12 +334,6 @@
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*/
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#define SCS_DWT_CTRL_CYCCNTENA (BIT0)
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/* CoreSight Lock Status Register lock status bit */
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#define SCS_LSR_SLK (1<<1)
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/* CoreSight Lock Status Register lock availability bit */
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#define SCS_LSR_SLI (1<<0)
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/* CoreSight Lock Access key, common for all */
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#define SCS_LAR_KEY 0xC5ACCE55
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/**@}*/
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#endif
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@ -55,9 +55,9 @@
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#define TPIU_DEVID MMIO32(TPIU_BASE + 0xFC8)
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/* CoreSight Lock Status Register for this peripheral */
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#define TPIU_LSR MMIO32(TPIU_BASE + 0xFB4)
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#define TPIU_LSR MMIO32(TPIU_BASE + CORESIGHT_LSR_OFFSET)
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/* CoreSight Lock Access Register for this peripheral */
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#define TPIU_LAR MMIO32(TPIU_BASE + 0xFB0)
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#define TPIU_LAR MMIO32(TPIU_BASE + CORESIGHT_LAR_OFFSET)
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/* TODO: PID, CID */
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