cm3: scs: drop all duplicate information
Keeps the best version of the documentation. Fixes: https://github.com/libopencm3/libopencm3/pull/269
This commit is contained in:
Karl Palsson
parent
833da4b672
commit
2b54119b78
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@ -20,25 +20,63 @@
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#ifndef LIBOPENCM3_CM3_DWT_H
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#define LIBOPENCM3_CM3_DWT_H
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/**
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* @defgroup cm_fpb Cortex-M Flash Patch and Breakpoint (FPB) unit
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* @ingroup CM3_defines
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* @{
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*/
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/cm3/memorymap.h>
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/**
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* @defgroup cm_dwt Cortex-M Data Watch and Trace unit.
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* @ingroup CM3_defines
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* System Control Space (SCS) => Data Watchpoint and Trace (DWT).
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* See "ARMv7-M Architecture Reference Manual"
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* and "ARMv6-M Architecture Reference Manual"
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* The DWT is an optional debug unit that provides watchpoints, data tracing,
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* and system profiling for the processor.
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* @{
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*/
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/*****************************************************************************/
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/* Register definitions */
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/*****************************************************************************/
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/** DWT Control register
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* Purpose Provides configuration and status information for the DWT block, and
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* used to control features of the block
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* Usage constraints: There are no usage constraints.
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* Configurations Always implemented.
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*/
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#define DWT_CTRL MMIO32(DWT_BASE + 0x00)
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/* Those defined only on ARMv7 and above */
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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/**
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* DWT_CYCCNT register
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* Cycle Count Register (Shows or sets the value of the processor cycle
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* counter, CYCCNT)
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* When enabled, CYCCNT increments on each processor clock cycle. On overflow,
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* CYCCNT wraps to zero.
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*
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* Purpose Shows or sets the value of the processor cycle counter, CYCCNT.
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* Usage constraints: The DWT unit suspends CYCCNT counting when the processor
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* is in Debug state.
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* Configurations Implemented: only when DWT_CTRL.NOCYCCNT is RAZ, see Control
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* register, DWT_CTRL.
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* When DWT_CTRL.NOCYCCNT is RAO no cycle counter is implemented and this
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* register is UNK/SBZP.
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*/
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#define DWT_CYCCNT MMIO32(DWT_BASE + 0x04)
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/** DWT_CPICNT register
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* Purpose Counts additional cycles required to execute multi-cycle
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* instructions and instruction fetch stalls.
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* Usage constraints: The counter initializes to 0 when software enables its
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* counter overflow event by
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* setting the DWT_CTRL.CPIEVTENA bit to 1.
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* Configurations Implemented: only when DWT_CTRL.NOPRFCNT is RAZ, see Control
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* register, DWT_CTRL.
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* If DWT_CTRL.NOPRFCNT is RAO, indicating that the implementation does not
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* include the profiling counters, this register is UNK/SBZP.
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*/
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#define DWT_CPICNT MMIO32(DWT_BASE + 0x08)
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#define DWT_EXCCNT MMIO32(DWT_BASE + 0x0C)
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#define DWT_SLEEPCNT MMIO32(DWT_BASE + 0x10)
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@ -99,6 +137,11 @@
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#define DWT_CTRL_POSTPRESET_SHIFT 1
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#define DWT_CTRL_POSTPRESET (0x0F << DWT_CTRL_POSTPRESET_SHIFT)
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/**
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* CYCCNTENA Enables the Cycle counter.
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* 0 = Disabled, 1 = Enabled
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* This bit is UNK/SBZP if the NOCYCCNT bit is RAO.
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*/
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#define DWT_CTRL_CYCCNTENA (1 << 0)
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#endif /* defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) */
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@ -24,6 +24,11 @@
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/**
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* @defgroup cm_scb Cortex-M System Control Block
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* @ingroup CM3_defines
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*
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* The System Control Block is a section of the System Control Space.
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* Other members of the SCS are, for instance, DWT, ITM, SYSTICKK.
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* The exact details of the SCB are defined in the "Architecture Reference
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* Manual" for either ARMv7-M or ARMV6-m.
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* @{
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*/
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#include <libopencm3/cm3/memorymap.h>
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@ -21,13 +21,6 @@
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#ifndef LIBOPENCM3_CM3_SCS_H
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#define LIBOPENCM3_CM3_SCS_H
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/*
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* All the definition hereafter are generic for CortexMx ARMv7-M
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* See ARM document "ARMv7-M Architecture Reference Manual" for more details.
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* See also ARM document "ARM Compiler toolchain Developing Software for ARM
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* Processors" for details on System Timer/SysTick.
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*/
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/**
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* @defgroup cm_scs Cortex-M System Control Space
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* @ingroup CM3_defines
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@ -42,6 +35,9 @@
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* - a Nested Vectored Interrupt Controller (NVIC)
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* - a Protected Memory System Architecture (PMSA)
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* - system debug.
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*
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* Most portions of the SCS are covered by their own header files, eg
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* systick.h, dwt.h, scb.h, itm.h, fpb.h
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* @{
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*/
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@ -149,180 +145,11 @@
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/* Bits 3:1 - Reserved */
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#define SCS_DEMCR_VC_CORERESET (1 << 0)
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/*
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* System Control Space (SCS) => System timer register support in the SCS.
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* To configure SysTick, load the interval required between SysTick events to
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* the SysTick Reload Value register. The timer interrupt, or COUNTFLAG bit in
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* the SysTick Control and Status register, is activated on the transition from
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* 1 to 0, therefore it activates every n+1 clock ticks. If you require a
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* period of 100, write 99 to the SysTick Reload Value register. The SysTick
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* Reload Value register supports values between 0x1 and 0x00FFFFFF.
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*
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* If you want to use SysTick to generate an event at a timed interval, for
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* example 1ms, you can use the SysTick Calibration Value Register to scale
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* your value for the Reload register. The SysTick Calibration Value Register
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* is a read-only register that contains the number of pulses for a period of
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* 10ms, in the TENMS field, bits[23:0].
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*
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* This register also has a SKEW bit. Bit[30] == 1 indicates that the
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* calibration for 10ms in the TENMS section is not exactly 10ms due to clock
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* frequency. Bit[31] == 1 indicates that the reference clock is not provided.
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*/
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/*
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* SysTick Control and Status Register (CSR).
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* Purpose Controls the system timer and provides status data.
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* Usage constraints: There are no usage constraints.
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* Configurations Always implemented.
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*/
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#define SCS_SYST_CSR MMIO32(SCS_BASE + 0x10)
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/* SysTick Reload Value Register (CVR).
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* Purpose Reads or clears the current counter value.
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* Usage constraints:
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* - Any write to the register clears the register to zero.
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* - The counter does not provide read-modify-write protection.
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* - Unsupported bits are read as zero
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* Configurations Always implemented.
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*/
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#define CM_SCS_SYST_RVR MMIO32(SCS_BASE + 0x14)
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/* SysTick Current Value Register (RVR).
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* Purpose Holds the reload value of the SYST_CVR.
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* Usage constraints There are no usage constraints.
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* Configurations Always implemented.
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*/
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#define CM_SCS_SYST_CVR MMIO32(SCS_BASE + 0x18)
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/*
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* SysTick Calibration value Register(Read Only) (CALIB)
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* Purpose Reads the calibration value and parameters for SysTick.
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* Usage constraints: There are no usage constraints.
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* Configurations Always implemented.
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*/
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#define CM_SCS_SYST_CALIB MMIO32(SCS_BASE + 0x1C)
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/* --- SCS_SYST_CSR values ----------------------------------------------- */
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/* Counter is operating. */
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#define SCS_SYST_CSR_ENABLE (BIT0)
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/* Count to 0 changes the SysTick exception status to pending. */
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#define SCS_SYST_CSR_TICKINT (BIT1)
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/* SysTick uses the processor clock. */
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#define SCS_SYST_CSR_CLKSOURCE (BIT2)
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/*
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* Indicates whether the counter has counted to 0 since the last read of this
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* register:
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* 0 = Timer has not counted to 0
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* 1 = Timer has counted to 0.
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*/
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#define SCS_SYST_CSR_COUNTFLAG (BIT16)
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/* --- CM_SCS_SYST_RVR values ---------------------------------------------- */
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/* Bit 0 to 23 => RELOAD The value to load into the SYST_CVR when the counter
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* reaches 0.
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*/
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/* Bit 24 to 31 are Reserved */
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/* --- CM_SCS_SYST_CVR values ---------------------------------------------- */
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/* Bit0 to 31 => Reads or clears the current counter value. */
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/* --- CM_SCS_SYST_CALIB values -------------------------------------------- */
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/*
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* Bit0 to 23 => TENMS Optionally, holds a reload value to be used for 10ms
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* (100Hz) timing, subject to system clock skew errors. If this field is zero,
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* the calibration value is not known.
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*/
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#define SCS_SYST_SYST_CALIB_TENMS_MASK (BIT24-1)
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/*
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* Bit30 => SKEW Indicates whether the 10ms calibration value is exact:
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* 0 = 10ms calibration value is exact.
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* 1 = 10ms calibration value is inexact, because of the clock frequency
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*/
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#define SCS_SYST_SYST_CALIB_VALUE_INEXACT (BIT30)
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/*
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* Bit31 => NOREF Indicates whether the IMPLEMENTATION DEFINED reference clock
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* is implemented:
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* 0 = The reference clock is implemented.
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* 1 = The reference clock is not implemented.
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* When this bit is 1, the CLKSOURCE bit of the SYST_CSR register is forced to
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* 1 and cannot be cleared to 0.
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*/
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#define SCS_SYST_SYST_CALIB_REF_NOT_IMPLEMENTED (BIT31)
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/*
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* System Control Space (SCS) => Data Watchpoint and Trace (DWT).
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* See "ARMv7-M Architecture Reference Manual"
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* (https://github.com/libopencm3/libopencm3-archive/blob/master/arm/
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* ARMv7-M_ARM.pdf)
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* The DWT is an optional debug unit that provides watchpoints, data tracing,
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* and system profiling for the processor.
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*/
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/*
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* DWT Control register
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* Purpose Provides configuration and status information for the DWT block, and
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* used to control features of the block
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* Usage constraints: There are no usage constraints.
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* Configurations Always implemented.
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*/
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#define SCS_DWT_CTRL MMIO32(DWT_BASE + 0x00)
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/*
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* DWT_CYCCNT register
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* Cycle Count Register (Shows or sets the value of the processor cycle
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* counter, CYCCNT)
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* When enabled, CYCCNT increments on each processor clock cycle. On overflow,
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* CYCCNT wraps to zero.
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*
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* Purpose Shows or sets the value of the processor cycle counter, CYCCNT.
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* Usage constraints: The DWT unit suspends CYCCNT counting when the processor
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* is in Debug state.
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* Configurations Implemented: only when DWT_CTRL.NOCYCCNT is RAZ, see Control
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* register, DWT_CTRL.
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* When DWT_CTRL.NOCYCCNT is RAO no cycle counter is implemented and this
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* register is UNK/SBZP.
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*/
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#define SCS_DWT_CYCCNT MMIO32(DWT_BASE + 0x04)
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/* DWT_CPICNT register
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* Purpose Counts additional cycles required to execute multi-cycle
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* instructions and instruction fetch stalls.
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* Usage constraints: The counter initializes to 0 when software enables its
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* counter overflow event by
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* setting the DWT_CTRL.CPIEVTENA bit to 1.
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* Configurations Implemented: only when DWT_CTRL.NOPRFCNT is RAZ, see Control
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* register, DWT_CTRL.
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* If DWT_CTRL.NOPRFCNT is RAO, indicating that the implementation does not
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* include the profiling counters, this register is UNK/SBZP.
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*/
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#define SCS_DWT_CPICNT MMIO32(DWT_BASE + 0x08)
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/* DWT_EXCCNT register */
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#define SCS_DWT_EXCCNT MMIO32(DWT_BASE + 0x0C)
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/* DWT_EXCCNT register */
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#define SCS_DWT_SLEEPCNT MMIO32(DWT_BASE + 0x10)
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/* DWT_EXCCNT register */
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#define SCS_DWT_LSUCNT MMIO32(DWT_BASE + 0x14)
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/* DWT_EXCCNT register */
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#define SCS_DWT_FOLDCNT MMIO32(DWT_BASE + 0x18)
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/* DWT_PCSR register */
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#define SCS_DWT_PCSR MMIO32(DWT_BASE + 0x18)
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/* CoreSight Lock Status Register for this peripheral */
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#define SCS_DWT_LSR MMIO32(SCS_DWT_BASE + 0xFB4)
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/* CoreSight Lock Access Register for this peripheral */
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#define SCS_DWT_LAR MMIO32(SCS_DWT_BASE + 0xFB0)
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/* --- SCS_DWT_CTRL values ------------------------------------------------- */
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/*
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* Enables CYCCNT:
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* 0 = Disabled, 1 = Enabled
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* This bit is UNK/SBZP if the NOCYCCNT bit is RAO.
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*/
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#define SCS_DWT_CTRL_CYCCNTENA (BIT0)
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/**@}*/
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#endif
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@ -29,15 +29,27 @@
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*
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* @date 19 August 2012
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*
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* System Control Space (SCS) => System timer register support in the SCS.
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* To configure SysTick, load the interval required between SysTick events to
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* the SysTick Reload Value register. The timer interrupt, or COUNTFLAG bit in
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* the SysTick Control and Status register, is activated on the transition from
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* 1 to 0, therefore it activates every n+1 clock ticks. If you require a
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* period of 100, write 99 to the SysTick Reload Value register. The SysTick
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* Reload Value register supports values between 0x1 and 0x00FFFFFF.
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*
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* If you want to use SysTick to generate an event at a timed interval, for
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* example 1ms, you can use the SysTick Calibration Value Register to scale
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* your value for the Reload register. The SysTick Calibration Value Register
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* is a read-only register that contains the number of pulses for a period of
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* 10ms, in the TENMS field, bits[23:0].
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*
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* This register also has a SKEW bit. Bit[30] == 1 indicates that the
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* calibration for 10ms in the TENMS section is not exactly 10ms due to clock
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* frequency. Bit[31] == 1 indicates that the reference clock is not provided.
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/**
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* @note this file has been not following the register naming scheme, the
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* correct names defined, and the old ones stay there for compatibility with
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* old software (will be deprecated in the future)
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*/
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/**@{*/
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#ifndef LIBOPENCM3_SYSTICK_H
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@ -46,28 +58,54 @@
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#include <libopencm3/cm3/memorymap.h>
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#include <libopencm3/cm3/common.h>
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/* --- SYSTICK registers --------------------------------------------------- */
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/* Control and status register (STK_CTRL) */
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/** SysTick Control and Status Register (CSR).
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* Controls the system timer and provides status data.
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* Usage constraints: There are no usage constraints.
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* Configurations Always implemented.
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*/
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#define STK_CSR MMIO32(SYS_TICK_BASE + 0x00)
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/* reload value register (STK_LOAD) */
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/** SysTick Reload Value Register (RVR).
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* Reads or clears the value that will be loaded to the counter.
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* Usage constraints:
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* - Any write to the register clears the register to zero.
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* - The counter does not provide read-modify-write protection.
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* - Unsupported bits are read as zero
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* Configurations Always implemented.
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*/
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#define STK_RVR MMIO32(SYS_TICK_BASE + 0x04)
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/* current value register (STK_VAL) */
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/** SysTick Current Value Register (CVR).
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* Holds the current value of the counter.
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* Usage constraints: There are no usage constraints.
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* Configurations Always implemented.
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*/
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#define STK_CVR MMIO32(SYS_TICK_BASE + 0x08)
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/* calibration value register (STK_CALIB) */
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/** SysTick Calibration Value Register(Read Only) (CALIB)
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* Reads the calibration value and parameters for SysTick.
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* Usage constraints: There are no usage constraints.
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* Configurations Always implemented.
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*/
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#define STK_CALIB MMIO32(SYS_TICK_BASE + 0x0C)
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/* --- STK_CSR values ------------------------------------------------------ */
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/* Bits [31:17] Reserved, must be kept cleared. */
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/* COUNTFLAG: */
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/** @defgroup STK_CSR_VALUES STK_CSR Values
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* @{
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*/
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/** COUNTFLAG
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* Indicates whether the counter has counted to 0 since the last read of this
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* register:
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* 0 = Timer has not counted to 0
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* 1 = Timer has counted to 0.
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*/
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#define STK_CSR_COUNTFLAG (1 << 16)
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/* Bits [15:3] Reserved, must be kept cleared. */
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/* CLKSOURCE: Clock source selection */
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#define STK_CSR_CLKSOURCE_LSB 2
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/** CLKSOURCE: Clock source selection
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* for 0, SysTick uses the IMPLEMENTATION DEFINED external reference clock.
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* for 1, SysTick uses the processor clock.
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* If no external clock is provided, this bit reads as 1 and ignores writes.
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*/
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#define STK_CSR_CLKSOURCE (1 << STK_CSR_CLKSOURCE_LSB)
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/** @defgroup systick_clksource Clock source selection
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@ -83,31 +121,57 @@
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#endif
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/**@}*/
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/* TICKINT: SysTick exception request enable */
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/** TICKINT: SysTick exception request enable */
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#define STK_CSR_TICKINT (1 << 1)
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/* ENABLE: Counter enable */
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/** ENABLE: Counter enable */
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#define STK_CSR_ENABLE (1 << 0)
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/**@}*/
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/* --- STK_RVR values ------------------------------------------------------ */
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/* Bits [31:24] Reserved, must be kept cleared. */
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/* RELOAD[23:0]: RELOAD value */
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/** @defgroup STK_RVR_VALUES STK_RVR Values
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* @{
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*/
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/** RELOAD[23:0]: RELOAD value */
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#define STK_RVR_RELOAD 0x00FFFFFF
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/**@}*/
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/* --- STK_CVR values ------------------------------------------------------ */
|
||||
/* Bits [31:24] Reserved, must be kept cleared. */
|
||||
/* CURRENT[23:0]: Current counter value */
|
||||
|
||||
/** @defgroup STK_RVR_VALUES STK_RVR Values
|
||||
* @{
|
||||
*/
|
||||
/** CURRENT[23:0]: Current counter value */
|
||||
#define STK_CVR_CURRENT 0x00FFFFFF
|
||||
/**@}*/
|
||||
|
||||
|
||||
/* --- STK_CALIB values ---------------------------------------------------- */
|
||||
/* NOREF: NOREF flag */
|
||||
/** @defgroup STK_CALIB_VALUES STK_CALIB Values
|
||||
* @{
|
||||
*/
|
||||
/** NOREF: NOREF flag
|
||||
* Bit31 => NOREF Indicates whether the IMPLEMENTATION DEFINED reference clock
|
||||
* is implemented:
|
||||
* 0 = The reference clock is implemented.
|
||||
* 1 = The reference clock is not implemented.
|
||||
* When this bit is 1, the CLKSOURCE bit of the SYST_CSR register is forced to
|
||||
* 1 and cannot be cleared to 0.
|
||||
*/
|
||||
#define STK_CALIB_NOREF (1 << 31)
|
||||
/* SKEW: SKEW flag */
|
||||
|
||||
/** SKEW: SKEW flag
|
||||
* Bit30 => SKEW Indicates whether the 10ms calibration value is exact:
|
||||
* 0 = 10ms calibration value is exact.
|
||||
* 1 = 10ms calibration value is inexact, because of the clock frequency
|
||||
*/
|
||||
#define STK_CALIB_SKEW (1 << 30)
|
||||
|
||||
/* Bits [29:24] Reserved, must be kept cleared. */
|
||||
/* TENMS[23:0]: Calibration value */
|
||||
/** TENMS Calibration value for 10ms.
|
||||
* Bit0 to 23 => TENMS Optionally, holds a reload value to be used for 10ms
|
||||
* (100Hz) timing, subject to system clock skew errors. If this field is zero,
|
||||
* the calibration value is not known.
|
||||
*/
|
||||
#define STK_CALIB_TENMS 0x00FFFFFF
|
||||
/**@}*/
|
||||
|
||||
/* --- Function Prototypes ------------------------------------------------- */
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue