Added USART_ prefix to bit definitions.
This matches the new convention used throughout libopenstm32.
This commit is contained in:
Piotr Esden-Tempski
parent
afc9cc84de
commit
667f32bd45
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@ -53,10 +53,10 @@ void usart_setup(void)
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/* Setup UART parameters. */
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usart_set_baudrate(USART3, 38400);
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usart_set_databits(USART3, 8);
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usart_set_stopbits(USART3, STOPBITS_1);
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usart_set_mode(USART3, MODE_TX);
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usart_set_parity(USART3, PARITY_NONE);
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usart_set_flow_control(USART3, FLOWCONTROL_NONE);
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usart_set_stopbits(USART3, USART_STOPBITS_1);
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usart_set_mode(USART3, USART_MODE_TX);
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usart_set_parity(USART3, USART_PARITY_NONE);
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usart_set_flow_control(USART3, USART_FLOWCONTROL_NONE);
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/* Finally enable the USART. */
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usart_enable(USART3);
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@ -90,16 +90,16 @@
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/* --- USART_SR values ----------------------------------------------------- */
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#define SR_CTS (1 << 9) /* N/A on UART4/5 */
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#define SR_LBD (1 << 8)
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#define SR_TXE (1 << 7)
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#define SR_TC (1 << 6)
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#define SR_RXNE (1 << 5)
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#define SR_IDLE (1 << 4)
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#define SR_ORE (1 << 3)
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#define SR_NE (1 << 2)
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#define SR_FE (1 << 1)
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#define SR_PE (1 << 0)
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#define USART_SR_CTS (1 << 9) /* N/A on UART4/5 */
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#define USART_SR_LBD (1 << 8)
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#define USART_SR_TXE (1 << 7)
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#define USART_SR_TC (1 << 6)
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#define USART_SR_RXNE (1 << 5)
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#define USART_SR_IDLE (1 << 4)
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#define USART_SR_ORE (1 << 3)
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#define USART_SR_NE (1 << 2)
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#define USART_SR_FE (1 << 1)
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#define USART_SR_PE (1 << 0)
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/* --- USART_DR values ----------------------------------------------------- */
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@ -112,68 +112,68 @@
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/* --- USART_CR1 values ---------------------------------------------------- */
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#define CR1_UE (1 << 13)
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#define CR1_M (1 << 12)
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#define CR1_WAKE (1 << 11)
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#define CR1_PCE (1 << 10)
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#define CR1_PS (1 << 9)
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#define CR1_PEIE (1 << 8)
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#define CR1_TXEIE (1 << 7)
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#define CR1_TCIE (1 << 6)
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#define CR1_RXNEIE (1 << 5)
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#define CR1_IDLEIE (1 << 4)
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#define CR1_TE (1 << 3)
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#define CR1_RE (1 << 2)
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#define CR1_RWU (1 << 1)
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#define CR1_SBK (1 << 0)
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#define USART_CR1_UE (1 << 13)
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#define USART_CR1_M (1 << 12)
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#define USART_CR1_WAKE (1 << 11)
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#define USART_CR1_PCE (1 << 10)
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#define USART_CR1_PS (1 << 9)
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#define USART_CR1_PEIE (1 << 8)
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#define USART_CR1_TXEIE (1 << 7)
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#define USART_CR1_TCIE (1 << 6)
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#define USART_CR1_RXNEIE (1 << 5)
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#define USART_CR1_IDLEIE (1 << 4)
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#define USART_CR1_TE (1 << 3)
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#define USART_CR1_RE (1 << 2)
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#define USART_CR1_RWU (1 << 1)
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#define USART_CR1_SBK (1 << 0)
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/* CR1_PCE / CR1_PS combined values */
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#define PARITY_NONE 0x00
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#define PARITY_ODD 0x02
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#define PARITY_EVEN 0x03
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#define USART_PARITY_NONE 0x00
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#define USART_PARITY_ODD 0x02
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#define USART_PARITY_EVEN 0x03
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/* CR1_TE/CR1_RE combined values */
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#define MODE_RX 0x01
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#define MODE_TX 0x02
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#define MODE_TX_RX 0x03
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#define USART_MODE_RX 0x01
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#define USART_MODE_TX 0x02
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#define USART_MODE_TX_RX 0x03
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/* --- USART_CR2 values ---------------------------------------------------- */
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#define CR2_LINEN (1 << 14) /* LIN mode enable */
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#define USART_CR2_LINEN (1 << 14) /* LIN mode enable */
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/* USART_CR2[13:12]: STOP */
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#define CR2_CLKEN (1 << 11) /* Clock enable */
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#define CR2_CPOL (1 << 10) /* Clock polarity */
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#define CR2_CPHA (1 << 9) /* Clock phase */
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#define CR2_LBCL (1 << 8) /* Last bit clock pulse */
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#define CR2_LBDIE (1 << 6) /* LIN break det. int. en. */
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#define CR2_LBDL (1 << 5) /* LIN break det. length */
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#define USART_CR2_CLKEN (1 << 11) /* Clock enable */
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#define USART_CR2_CPOL (1 << 10) /* Clock polarity */
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#define USART_CR2_CPHA (1 << 9) /* Clock phase */
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#define USART_CR2_LBCL (1 << 8) /* Last bit clock pulse */
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#define USART_CR2_LBDIE (1 << 6) /* LIN break det. int. en. */
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#define USART_CR2_LBDL (1 << 5) /* LIN break det. length */
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/* USART_CR2[3:0]: ADD */
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/* STOP values */
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#define STOPBITS_1 0x00 /* 1 stop bit */
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#define STOPBITS_0_5 0x01 /* 0.5 stop bits */
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#define STOPBITS_2 0x02 /* 2 stop bits */
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#define STOPBITS_1_5 0x03 /* 1.5 stop bits */
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#define USART_STOPBITS_1 0x00 /* 1 stop bit */
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#define USART_STOPBITS_0_5 0x01 /* 0.5 stop bits */
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#define USART_STOPBITS_2 0x02 /* 2 stop bits */
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#define USART_STOPBITS_1_5 0x03 /* 1.5 stop bits */
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/* --- USART_CR3 values ---------------------------------------------------- */
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#define CR3_CTSIE (1 << 10) /* CTS interrupt enable */
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#define CR3_CTSE (1 << 9) /* CTS enable */
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#define CR3_RTSE (1 << 8) /* RTS enable */
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#define CR3_DMAT (1 << 7) /* DMA enable transmitter */
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#define CR3_DMAR (1 << 6) /* DMA enable receiver */
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#define CR3_SCEN (1 << 5) /* Smartcard mode enable */
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#define CR3_NACK (1 << 4) /* Smartcard NACK enable */
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#define CR3_HDSEL (1 << 3) /* Half-duplex selection */
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#define CR3_IRLP (1 << 2) /* IrDA low-power */
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#define CR3_IREN (1 << 1) /* IrDA mode enable */
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#define CR3_EIE (1 << 0) /* Error interrupt enable */
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#define USART_CR3_CTSIE (1 << 10) /* CTS interrupt enable */
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#define USART_CR3_CTSE (1 << 9) /* CTS enable */
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#define USART_CR3_RTSE (1 << 8) /* RTS enable */
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#define USART_CR3_DMAT (1 << 7) /* DMA enable transmitter */
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#define USART_CR3_DMAR (1 << 6) /* DMA enable receiver */
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#define USART_CR3_SCEN (1 << 5) /* Smartcard mode enable */
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#define USART_CR3_NACK (1 << 4) /* Smartcard NACK enable */
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#define USART_CR3_HDSEL (1 << 3) /* Half-duplex selection */
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#define USART_CR3_IRLP (1 << 2) /* IrDA low-power */
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#define USART_CR3_IREN (1 << 1) /* IrDA mode enable */
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#define USART_CR3_EIE (1 << 0) /* Error interrupt enable */
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/* CR3_CTSE/CR3_RTSE combined values */
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#define FLOWCONTROL_NONE 0x00
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#define FLOWCONTROL_RTS 0x01
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#define FLOWCONTROL_CTS 0x02
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#define FLOWCONTROL_RTS_CTS 0x03
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#define USART_FLOWCONTROL_NONE 0x00
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#define USART_FLOWCONTROL_RTS 0x01
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#define USART_FLOWCONTROL_CTS 0x02
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#define USART_FLOWCONTROL_RTS_CTS 0x03
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/* --- USART_GTPR values --------------------------------------------------- */
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12
lib/usart.c
12
lib/usart.c
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@ -30,9 +30,9 @@ void usart_set_baudrate(u32 usart, u32 baud)
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void usart_set_databits(u32 usart, u32 bits)
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{
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if (bits == 8)
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USART_CR1(usart) &= ~CR1_M; /* 8 data bits */
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USART_CR1(usart) &= ~USART_CR1_M; /* 8 data bits */
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else
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USART_CR1(usart) |= CR1_M; /* 9 data bits */
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USART_CR1(usart) |= USART_CR1_M; /* 9 data bits */
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}
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void usart_set_stopbits(u32 usart, u32 stopbits)
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@ -73,12 +73,12 @@ void usart_set_flow_control(u32 usart, u32 flowcontrol)
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void usart_enable(u32 usart)
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{
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USART_CR1(usart) |= CR1_UE;
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USART_CR1(usart) |= USART_CR1_UE;
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}
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void usart_disable(u32 usart)
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{
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USART_CR1(usart) &= ~CR1_UE;
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USART_CR1(usart) &= ~USART_CR1_UE;
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}
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void usart_send(u32 usart, u16 data)
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@ -87,13 +87,13 @@ void usart_send(u32 usart, u16 data)
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USART_DR(usart) = (data & 0x1ff);
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/* Wait until the data has been transferred into the shift register. */
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while ((USART_SR(usart) & SR_TXE) == 0);
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while ((USART_SR(usart) & USART_SR_TXE) == 0);
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}
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u16 usart_recv(u32 usart)
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{
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/* Wait until the data is ready to be received. */
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while ((USART_SR(usart) & SR_RXNE) == 0);
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while ((USART_SR(usart) & USART_SR_RXNE) == 0);
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/* Receive data. */
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return USART_DR(usart) & 0x1ff;
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