diff --git a/examples/usart/usart.c b/examples/usart/usart.c
index 7e34e581..922ec899 100644
--- a/examples/usart/usart.c
+++ b/examples/usart/usart.c
@@ -53,10 +53,10 @@ void usart_setup(void)
 	/* Setup UART parameters. */
 	usart_set_baudrate(USART3, 38400);
 	usart_set_databits(USART3, 8);
-	usart_set_stopbits(USART3, STOPBITS_1);
-	usart_set_mode(USART3, MODE_TX);
-	usart_set_parity(USART3, PARITY_NONE);
-	usart_set_flow_control(USART3, FLOWCONTROL_NONE);
+	usart_set_stopbits(USART3, USART_STOPBITS_1);
+	usart_set_mode(USART3, USART_MODE_TX);
+	usart_set_parity(USART3, USART_PARITY_NONE);
+	usart_set_flow_control(USART3, USART_FLOWCONTROL_NONE);
 
 	/* Finally enable the USART. */
 	usart_enable(USART3);
diff --git a/include/libopenstm32/usart.h b/include/libopenstm32/usart.h
index 422a8936..63caf05a 100644
--- a/include/libopenstm32/usart.h
+++ b/include/libopenstm32/usart.h
@@ -90,16 +90,16 @@
 
 /* --- USART_SR values ----------------------------------------------------- */
 
-#define SR_CTS				(1 << 9) /* N/A on UART4/5 */
-#define SR_LBD				(1 << 8)
-#define SR_TXE				(1 << 7)
-#define SR_TC				(1 << 6)
-#define SR_RXNE				(1 << 5)
-#define SR_IDLE				(1 << 4)
-#define SR_ORE				(1 << 3)
-#define SR_NE				(1 << 2)
-#define SR_FE				(1 << 1)
-#define SR_PE				(1 << 0)
+#define USART_SR_CTS				(1 << 9) /* N/A on UART4/5 */
+#define USART_SR_LBD				(1 << 8)
+#define USART_SR_TXE				(1 << 7)
+#define USART_SR_TC				(1 << 6)
+#define USART_SR_RXNE				(1 << 5)
+#define USART_SR_IDLE				(1 << 4)
+#define USART_SR_ORE				(1 << 3)
+#define USART_SR_NE				(1 << 2)
+#define USART_SR_FE				(1 << 1)
+#define USART_SR_PE				(1 << 0)
 
 /* --- USART_DR values ----------------------------------------------------- */
 
@@ -112,68 +112,68 @@
 
 /* --- USART_CR1 values ---------------------------------------------------- */
 
-#define CR1_UE				(1 << 13)
-#define CR1_M				(1 << 12)
-#define CR1_WAKE			(1 << 11)
-#define CR1_PCE				(1 << 10)
-#define CR1_PS				(1 << 9)
-#define CR1_PEIE			(1 << 8)
-#define CR1_TXEIE			(1 << 7)
-#define CR1_TCIE			(1 << 6)
-#define CR1_RXNEIE			(1 << 5)
-#define CR1_IDLEIE			(1 << 4)
-#define CR1_TE				(1 << 3)
-#define CR1_RE				(1 << 2)
-#define CR1_RWU				(1 << 1)
-#define CR1_SBK				(1 << 0)
+#define USART_CR1_UE				(1 << 13)
+#define USART_CR1_M				(1 << 12)
+#define USART_CR1_WAKE			        (1 << 11)
+#define USART_CR1_PCE				(1 << 10)
+#define USART_CR1_PS				(1 << 9)
+#define USART_CR1_PEIE			        (1 << 8)
+#define USART_CR1_TXEIE			        (1 << 7)
+#define USART_CR1_TCIE		                (1 << 6)
+#define USART_CR1_RXNEIE			(1 << 5)
+#define USART_CR1_IDLEIE			(1 << 4)
+#define USART_CR1_TE				(1 << 3)
+#define USART_CR1_RE				(1 << 2)
+#define USART_CR1_RWU				(1 << 1)
+#define USART_CR1_SBK				(1 << 0)
 
 /* CR1_PCE / CR1_PS combined values */
-#define PARITY_NONE			0x00
-#define PARITY_ODD			0x02
-#define PARITY_EVEN			0x03
+#define USART_PARITY_NONE			0x00
+#define USART_PARITY_ODD			0x02
+#define USART_PARITY_EVEN			0x03
 
 /* CR1_TE/CR1_RE combined values */
-#define MODE_RX				0x01
-#define MODE_TX				0x02
-#define MODE_TX_RX			0x03
+#define USART_MODE_RX				0x01
+#define USART_MODE_TX				0x02
+#define USART_MODE_TX_RX			0x03
 
 /* --- USART_CR2 values ---------------------------------------------------- */
 
-#define CR2_LINEN			(1 << 14) /* LIN mode enable */
+#define USART_CR2_LINEN			(1 << 14) /* LIN mode enable */
 /* USART_CR2[13:12]: STOP */
-#define CR2_CLKEN			(1 << 11) /* Clock enable */
-#define CR2_CPOL			(1 << 10) /* Clock polarity */
-#define CR2_CPHA			(1 << 9)  /* Clock phase */
-#define CR2_LBCL			(1 << 8)  /* Last bit clock pulse */
-#define CR2_LBDIE			(1 << 6)  /* LIN break det. int. en. */
-#define CR2_LBDL			(1 << 5)  /* LIN break det. length */
+#define USART_CR2_CLKEN			(1 << 11) /* Clock enable */
+#define USART_CR2_CPOL			(1 << 10) /* Clock polarity */
+#define USART_CR2_CPHA			(1 << 9)  /* Clock phase */
+#define USART_CR2_LBCL			(1 << 8)  /* Last bit clock pulse */
+#define USART_CR2_LBDIE			(1 << 6)  /* LIN break det. int. en. */
+#define USART_CR2_LBDL			(1 << 5)  /* LIN break det. length */
 /* USART_CR2[3:0]: ADD */
 
 /* STOP values */
-#define STOPBITS_1			0x00      /* 1 stop bit */
-#define STOPBITS_0_5			0x01      /* 0.5 stop bits */
-#define STOPBITS_2			0x02      /* 2 stop bits */
-#define STOPBITS_1_5			0x03      /* 1.5 stop bits */
+#define USART_STOPBITS_1			0x00      /* 1 stop bit */
+#define USART_STOPBITS_0_5			0x01      /* 0.5 stop bits */
+#define USART_STOPBITS_2			0x02      /* 2 stop bits */
+#define USART_STOPBITS_1_5			0x03      /* 1.5 stop bits */
 
 /* --- USART_CR3 values ---------------------------------------------------- */
 
-#define CR3_CTSIE			(1 << 10) /* CTS interrupt enable */
-#define CR3_CTSE			(1 << 9)  /* CTS enable */
-#define CR3_RTSE			(1 << 8)  /* RTS enable */
-#define CR3_DMAT			(1 << 7)  /* DMA enable transmitter */
-#define CR3_DMAR			(1 << 6)  /* DMA enable receiver */
-#define CR3_SCEN			(1 << 5)  /* Smartcard mode enable */
-#define CR3_NACK			(1 << 4)  /* Smartcard NACK enable */
-#define CR3_HDSEL			(1 << 3)  /* Half-duplex selection */
-#define CR3_IRLP			(1 << 2)  /* IrDA low-power */
-#define CR3_IREN			(1 << 1)  /* IrDA mode enable */
-#define CR3_EIE				(1 << 0)  /* Error interrupt enable */
+#define USART_CR3_CTSIE			(1 << 10) /* CTS interrupt enable */
+#define USART_CR3_CTSE			(1 << 9)  /* CTS enable */
+#define USART_CR3_RTSE			(1 << 8)  /* RTS enable */
+#define USART_CR3_DMAT			(1 << 7)  /* DMA enable transmitter */
+#define USART_CR3_DMAR			(1 << 6)  /* DMA enable receiver */
+#define USART_CR3_SCEN			(1 << 5)  /* Smartcard mode enable */
+#define USART_CR3_NACK			(1 << 4)  /* Smartcard NACK enable */
+#define USART_CR3_HDSEL			(1 << 3)  /* Half-duplex selection */
+#define USART_CR3_IRLP			(1 << 2)  /* IrDA low-power */
+#define USART_CR3_IREN			(1 << 1)  /* IrDA mode enable */
+#define USART_CR3_EIE				(1 << 0)  /* Error interrupt enable */
 
 /* CR3_CTSE/CR3_RTSE combined values */
-#define FLOWCONTROL_NONE		0x00
-#define FLOWCONTROL_RTS			0x01
-#define FLOWCONTROL_CTS			0x02
-#define FLOWCONTROL_RTS_CTS		0x03
+#define USART_FLOWCONTROL_NONE		0x00
+#define USART_FLOWCONTROL_RTS			0x01
+#define USART_FLOWCONTROL_CTS			0x02
+#define USART_FLOWCONTROL_RTS_CTS		0x03
 
 /* --- USART_GTPR values --------------------------------------------------- */
 
diff --git a/lib/usart.c b/lib/usart.c
index fdcc9321..abed18b2 100644
--- a/lib/usart.c
+++ b/lib/usart.c
@@ -30,9 +30,9 @@ void usart_set_baudrate(u32 usart, u32 baud)
 void usart_set_databits(u32 usart, u32 bits)
 {
 	if (bits == 8)
-		USART_CR1(usart) &= ~CR1_M; /* 8 data bits */
+		USART_CR1(usart) &= ~USART_CR1_M; /* 8 data bits */
 	else
-		USART_CR1(usart) |= CR1_M;  /* 9 data bits */
+		USART_CR1(usart) |= USART_CR1_M;  /* 9 data bits */
 }
 
 void usart_set_stopbits(u32 usart, u32 stopbits)
@@ -73,12 +73,12 @@ void usart_set_flow_control(u32 usart, u32 flowcontrol)
 
 void usart_enable(u32 usart)
 {
-	USART_CR1(usart) |= CR1_UE;
+	USART_CR1(usart) |= USART_CR1_UE;
 }
 
 void usart_disable(u32 usart)
 {
-	USART_CR1(usart) &= ~CR1_UE;
+	USART_CR1(usart) &= ~USART_CR1_UE;
 }
 
 void usart_send(u32 usart, u16 data)
@@ -87,13 +87,13 @@ void usart_send(u32 usart, u16 data)
 	USART_DR(usart) = (data & 0x1ff);
 
 	/* Wait until the data has been transferred into the shift register. */
-	while ((USART_SR(usart) & SR_TXE) == 0);
+	while ((USART_SR(usart) & USART_SR_TXE) == 0);
 }
 
 u16 usart_recv(u32 usart)
 {
 	/* Wait until the data is ready to be received. */
-	while ((USART_SR(usart) & SR_RXNE) == 0);
+	while ((USART_SR(usart) & USART_SR_RXNE) == 0);
 
 	/* Receive data. */
 	return USART_DR(usart) & 0x1ff;