HAVE_SSE3 and HAVE_SSE4_1 were never defined if CPU architecture
doesn't match the (86*|x86_64*|amd64*) condition.
Change-Id: I3350b14dbc91e9b388d0b04a0ed22ba27d436313
Despite the macro message says, that cpuid functionality was stripped
it was still partially preset and wasn't used anyhow.
Change-Id: I380bc9c13d29319685781ef27973afe6744fcf3d
This bug only affects generation of normal bursts filled with random bits which
are used in test mode. It doesn't affect operation of osmo-trx during normal
operation. That's why it has stayed unnoticed for so long.
Each Normal Burst has 3 tail bits, not 4.
Also it's better to set stealing bits to 0 for maximum compatibility. We may want to
introduce a selector for each bit whether to set it to 0, to 1 or to a random number.
Change-Id: I0377029556c8b681b3ba3b635bf19572b34546ea
This should fix package build for Ubuntu 17.04: obsolete package
hardening-wrapper was removed which cause .deb build failure.
The dependency on it is incorrect to begin with because we use
DEB_BUILD_MAINT_OPTIONS instead.
Change-Id: I3ea72b4123a280a846086d083c4f3189d611f8cf
The 'diversity' option was an experimental 2 antenna receiver
implementation for UmTRX. The implementation has not been
maintained and current working status is unknown.
In addition to code rot, Coverity is triggering errors in the
associated code sections.
Removal of code cleans up many cases of special handling that
were necessary to accommodate the implementation.
Change-Id: I46752ccf5dbcffbec806081dec03e69a0fbdcdb7
The osmo-trx binary outputs no info about its SSE support status.
This commits adds some putput that informs about the SSE of the
binary and also tells which of the SSE levels the CPU supports.
Change-Id: Iacc83fd668c31644e0efb3e18962cf2870ed1daf
Currently we find SSE3 and SSE4.1 code mixed togehter along with
generic code in one file. This introduces the risk that the
compiler exidantly mixes SSE4.1 instructions into an SSE3, or
even worse into a generic code path.
This commit splits the SSE3 and SSE4.1 code into separate files
and compiles them with the matching target options.
Change-Id: I846e190e92f1258cd412d1b2d79b539e204e04b3
Currently the build environment checks which extension the current
CPU supports and picks the compiler flags accordingly.
If the build is happening on a machine that does not support the
extensions we need (SSE3, SSE4.1), the binary will lack those
extensions, even if its intended to be used on a more powerful
machine that would support the extensions.
This commit removes the CPU tests from the build process.
Change-Id: Ic913aa13c23c348ae62e78c9dfd6ed8b0a62798c
The ARM and the X86 implementation of the conversion functions share
the same, non cpu specific implementation in separate files.
This commit removes the code duplication by putting the generic
implementation into a convert_base.c, similar to to convolve_base.c
Change-Id: Ic8d8534a343e27cde79ddc85be4998ebd0cb6e5c
The current implementation can select the SSE support level during
compiletime only.
This commit adds functionality to automatically detect and switch
the SSE support level and automatically switch the Implementation
if the CPU does not support the required SSE level.
Change-Id: Iba74f8a6e4e921ff31e4bd9f0c7c881fe547423a
Convolution is a complex process and we should be able to verify
if computing results change when the implementation is touched.
This commit adds a test program that executes some testcases.
The testcases are crafted in a way that every implmentation
(several different ones for SSE) is executed once. The output
can be compared against the included .ok file.
Change-Id: Ic702ecb356c652fbcd76bee689717fb5d3526fe9
The non-sse implementation and the sse implementation of the convert
and convolve functions have different parameter lists. This makes it
difficult to use function pointers in order to select the right
function depending on the SSE-Level and CPU.
This commit uniformizes the parameter lists in preparation for
planned runtime cpu detection support
Change-Id: Ice063b89791537c4b591751f12f5ef5c413a2d27
The compiler option -march=native instructs the compiler to auto-optimize
the code for the current build architecture. This is fine for building
and using locally, but contraproductive when generating binary packages.
This commit replaces -march=native with $(SIMD_FLAGS), which contains a
collection of supported SIMD options, so we won't loose the SSE support.
Change-Id: I3df4b8db9692016115edbe2247beeec090715687
OpenBTS relies on reading in configuration values from the OpenBTS.config
sqlite3 database. This configuration method is not maintained and not
recommended for Osmocom or OpenBTS use. Command line setup is the
recommended approach.
Note that when the osmo-trx logging mechanism is replaced, the sqlite
dependency will be removed.
Change-Id: I95d7b771fde976818bee76f89163e72c3a44ecdd
Convert negative value check on unsigned value to zero check
to avoid potential divide-by-zero error condition.
Change-Id: Ib0d7d1bceb5fe66e69345db93a74e3e0773a2257
Fixes: Coverity CID 165059
Improper length values will cause the polyphase resampler
rotation to fail. Check return and return NULL on error.
Change-Id: I3ad22f9fd7a20754f589c04258dcca3770474a9b
Fixes: Coverity CID 165235
demodCommon() used to scale input vector in place which changed original data.
That's a bad practice and is not really necessary, so I've changed the code to
scale burst after it's copied to a new vector during a delay operation.
Change-Id: Ic45f71b634e48808356d68925bb9f5783e0bf0d3
The file seem to be using "2 spaces" indent, bt some lines are using
tabs which breaks formatting.
Change-Id: I7718cca45c245c9e91250ab2877f5436d4029698
This makes code simpler and will allow us send -127..127 soft bits towards
osmo-bts instead of 0..255 bits.
Change-Id: I16ecc3d4c829dcf0f619ad995bc9d4a4ed8af0a4
Now we have more fexibility in how we represent SoftVector, since we
no longer depend on the particular convolutional codec implementation.
Change-Id: I3006b6a26c5eff59dbe9c034f689961802f1d0d0
We use other symbols to show that these bits has less confidence:
o and . for 0 with less confidence
| and ' for 1 with less confidence
Change-Id: I747a17568ee48f1f3163e8dfab2e450af85e6435
vectorSlicer() converts soft-bits from -1..+1 to 0..1 while we want
to keep SoftVector in -1..+1 mode until the last minute, because at some
point we'll want to transmit -1..+1 to osmo-bts instead of converting it
from 0..1 back to -1..+1 on the osmo-bts side.
Plus it removes code duplication - we call it once instead of twice.
Change-Id: Idd6ddd7ac219afb0df055a692632678b66373764
This makes it similar to 8-PSK demod and also saves a bit of lines ofcode and
should give us a tiny improvement in performance.
Ideally we need to remove vector slicing at all, because in osmo-bts-trx
we convert back to +-1.0 again (actually to +-127, but it doesn't mater).
So we should rather transmit +-1.0 values to avoid double conversion.
Change-Id: If9ed6f0f80fbe88c994b2f9c3cae91d0d57f4442
Documentation in sigProcLib.h was noticeably out of sync with the actual
implementation - e.g. not all arguments were documented and arguments
which are already removed are still in the documentation. Also argument
names were different between declaration in .h and implementation in .cpp
which was confusing.
I've fixed this for detect*Burst() functions.
Change-Id: I4dfd07125d9a1e9a42a78b79faff539f003deb16
We use AX_EXT in ./configure for checking CPU features anyway, so it's
better to add it as explicit dependency.
Related: OS#1923
Change-Id: I7ba48e1df4ede8b477574da3faa15fd02e15c69b
Addresses following issues where UHD 3.9 and likely other UHD versions
would report a master clock (FPGA) rate error. Update MC-BTS FPGA clock
for B200 and B210 to 51.2 MHz, which is supported by all UHD versions.
Only B200/B210 is supported for MC-BTS operation.
https://osmocom.org/issues/1963https://osmocom.org/issues/1648
ALERT UHDDevice.cpp:548:set_master_clk: Failed to set master clock rate
ALERT UHDDevice.cpp:549:set_master_clk: Requested clock rate 3.2e+06
ALERT UHDDevice.cpp:550:set_master_clk: Actual clock rate 5e+06
Change-Id: I78fb2c0959abd0e666628ba39f433162aafb067e