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Revert "Get rid of _t suffix" 

In the very least, a change like this requires discussion on the list.

The naming convention is goofy and it causes a massive merge problem.  Something
like this _must_ be presented on the list first so people can provide input
and cope with it.

This reverts commit 99a0949b72.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Anthony Liguori 2009-10-01 16:12:16 -05:00
parent 99a0949b72
commit c227f0995e
316 changed files with 3332 additions and 3325 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
CODING_STYLE
View File

@ -40,10 +40,14 @@ Rationale:
3. Naming
Variables are lower_case_with_underscores; easy to type and read.
Structured type names are in CamelCase; harder to type but standing
out. Scalar type names are a_lower_case_beginning_with_an a or an.
Do not use _t suffix if you are including any headers.
Variables are lower_case_with_underscores; easy to type and read. Structured
type names are in CamelCase; harder to type but standing out. Scalar type
names are lower_case_with_underscores_ending_with_a_t, like the POSIX
uint64_t and family. Note that this last convention contradicts POSIX
and is therefore likely to be changed.
Typedefs are used to eliminate the redundant 'struct' keyword. It is the
QEMU coding style.
4. Block structure

6
balloon.h
View File

@ -16,12 +16,12 @@
#include "cpu-defs.h"
typedef a_ram_addr (QEMUBalloonEvent)(void *opaque, a_ram_addr target);
typedef ram_addr_t (QEMUBalloonEvent)(void *opaque, ram_addr_t target);
void qemu_add_balloon_handler(QEMUBalloonEvent *func, void *opaque);
void qemu_balloon(a_ram_addr target);
void qemu_balloon(ram_addr_t target);
a_ram_addr qemu_balloon_status(void);
ram_addr_t qemu_balloon_status(void);
#endif

288
block/vvfat.c
View File

@ -71,12 +71,12 @@ void nonono(const char* file, int line, const char* msg) {
#endif
/* dynamic array functions */
typedef struct array {
typedef struct array_t {
char* pointer;
unsigned int size,next,item_size;
} an_array;
} array_t;
static inline void array_init(an_array* array,unsigned int item_size)
static inline void array_init(array_t* array,unsigned int item_size)
{
array->pointer = NULL;
array->size=0;
@ -84,7 +84,7 @@ static inline void array_init(an_array* array,unsigned int item_size)
array->item_size=item_size;
}
static inline void array_free(an_array* array)
static inline void array_free(array_t* array)
{
if(array->pointer)
free(array->pointer);
@ -92,12 +92,12 @@ static inline void array_free(an_array* array)
}
/* does not automatically grow */
static inline void* array_get(an_array* array,unsigned int index) {
static inline void* array_get(array_t* array,unsigned int index) {
assert(index < array->next);
return array->pointer + index * array->item_size;
}
static inline int array_ensure_allocated(an_array* array, int index)
static inline int array_ensure_allocated(array_t* array, int index)
{
if((index + 1) * array->item_size > array->size) {
int new_size = (index + 32) * array->item_size;
@ -111,7 +111,7 @@ static inline int array_ensure_allocated(an_array* array, int index)
return 0;
}
static inline void* array_get_next(an_array* array) {
static inline void* array_get_next(array_t* array) {
unsigned int next = array->next;
void* result;
@ -124,7 +124,7 @@ static inline void* array_get_next(an_array* array) {
return result;
}
static inline void* array_insert(an_array* array,unsigned int index,unsigned int count) {
static inline void* array_insert(array_t* array,unsigned int index,unsigned int count) {
if((array->next+count)*array->item_size>array->size) {
int increment=count*array->item_size;
array->pointer=qemu_realloc(array->pointer,array->size+increment);
@ -141,7 +141,7 @@ static inline void* array_insert(an_array* array,unsigned int index,unsigned int
/* this performs a "roll", so that the element which was at index_from becomes
* index_to, but the order of all other elements is preserved. */
static inline int array_roll(an_array* array,int index_to,int index_from,int count)
static inline int array_roll(array_t* array,int index_to,int index_from,int count)
{
char* buf;
char* from;
@ -174,7 +174,7 @@ static inline int array_roll(an_array* array,int index_to,int index_from,int cou
return 0;
}
static inline int array_remove_slice(an_array* array,int index, int count)
static inline int array_remove_slice(array_t* array,int index, int count)
{
assert(index >=0);
assert(count > 0);
@ -185,13 +185,13 @@ static inline int array_remove_slice(an_array* array,int index, int count)
return 0;
}
static int array_remove(an_array* array,int index)
static int array_remove(array_t* array,int index)
{
return array_remove_slice(array, index, 1);
}
/* return the index for a given member */
static int array_index(an_array* array, void* pointer)
static int array_index(array_t* array, void* pointer)
{
size_t offset = (char*)pointer - array->pointer;
assert((offset % array->item_size) == 0);
@ -202,7 +202,7 @@ static int array_index(an_array* array, void* pointer)
/* These structures are used to fake a disk and the VFAT filesystem.
* For this reason we need to use __attribute__((packed)). */
typedef struct bootsector {
typedef struct bootsector_t {
uint8_t jump[3];
uint8_t name[8];
uint16_t sector_size;
@ -238,32 +238,32 @@ typedef struct bootsector {
uint8_t fat_type[8];
uint8_t ignored[0x1c0];
uint8_t magic[2];
} __attribute__((packed)) a_bootsector;
} __attribute__((packed)) bootsector_t;
typedef struct {
uint8_t head;
uint8_t sector;
uint8_t cylinder;
} a_mbr_chs;
} mbr_chs_t;
typedef struct partition {
typedef struct partition_t {
uint8_t attributes; /* 0x80 = bootable */
a_mbr_chs start_CHS;
mbr_chs_t start_CHS;
uint8_t fs_type; /* 0x1 = FAT12, 0x6 = FAT16, 0xe = FAT16_LBA, 0xb = FAT32, 0xc = FAT32_LBA */
a_mbr_chs end_CHS;
mbr_chs_t end_CHS;
uint32_t start_sector_long;
uint32_t length_sector_long;
} __attribute__((packed)) a_partition;
} __attribute__((packed)) partition_t;
typedef struct mbr {
typedef struct mbr_t {
uint8_t ignored[0x1b8];
uint32_t nt_id;
uint8_t ignored2[2];
a_partition partition[4];
partition_t partition[4];
uint8_t magic[2];
} __attribute__((packed)) a_mbr;
} __attribute__((packed)) mbr_t;
typedef struct direntry {
typedef struct direntry_t {
uint8_t name[8];
uint8_t extension[3];
uint8_t attributes;
@ -276,11 +276,11 @@ typedef struct direntry {
uint16_t mdate;
uint16_t begin;
uint32_t size;
} __attribute__((packed)) a_direntry;
} __attribute__((packed)) direntry_t;
/* this structure are used to transparently access the files */
typedef struct mapping {
typedef struct mapping_t {
/* begin is the first cluster, end is the last+1 */
uint32_t begin,end;
/* as s->directory is growable, no pointer may be used here */
@ -308,11 +308,11 @@ typedef struct mapping {
MODE_DIRECTORY = 4, MODE_FAKED = 8,
MODE_DELETED = 16, MODE_RENAMED = 32 } mode;
int read_only;
} a_mapping;
} mapping_t;
#ifdef DEBUG
static void print_direntry(const struct a_direntry*);
static void print_mapping(const struct a_mapping* mapping);
static void print_direntry(const struct direntry_t*);
static void print_mapping(const struct mapping_t* mapping);
#endif
/* here begins the real VVFAT driver */
@ -323,7 +323,7 @@ typedef struct BDRVVVFATState {
unsigned char first_sectors[0x40*0x200];
int fat_type; /* 16 or 32 */
an_array fat,directory,mapping;
array_t fat,directory,mapping;
unsigned int cluster_size;
unsigned int sectors_per_cluster;
@ -336,7 +336,7 @@ typedef struct BDRVVVFATState {
uint32_t max_fat_value;
int current_fd;
a_mapping* current_mapping;
mapping_t* current_mapping;
unsigned char* cluster; /* points to current cluster */
unsigned char* cluster_buffer; /* points to a buffer to hold temp data */
unsigned int current_cluster;
@ -347,7 +347,7 @@ typedef struct BDRVVVFATState {
BlockDriverState* qcow;
void* fat2;
char* used_clusters;
an_array commits;
array_t commits;
const char* path;
int downcase_short_names;
} BDRVVVFATState;
@ -356,7 +356,7 @@ typedef struct BDRVVVFATState {
* if the position is outside the specified geometry, fill maximum value for CHS
* and return 1 to signal overflow.
*/
static int sector2CHS(BlockDriverState* bs, a_mbr_chs * chs, int spos){
static int sector2CHS(BlockDriverState* bs, mbr_chs_t * chs, int spos){
int head,sector;
sector = spos % (bs->secs); spos/= bs->secs;
head = spos % (bs->heads); spos/= bs->heads;
@ -378,8 +378,8 @@ static int sector2CHS(BlockDriverState* bs, a_mbr_chs * chs, int spos){
static void init_mbr(BDRVVVFATState* s)
{
/* TODO: if the files mbr.img and bootsect.img exist, use them */
a_mbr* real_mbr=(a_mbr*)s->first_sectors;
a_partition* partition = &(real_mbr->partition[0]);
mbr_t* real_mbr=(mbr_t*)s->first_sectors;
partition_t* partition = &(real_mbr->partition[0]);
int lba;
memset(s->first_sectors,0,512);
@ -425,12 +425,12 @@ static inline int short2long_name(char* dest,const char* src)
return len;
}
static inline a_direntry* create_long_filename(BDRVVVFATState* s,const char* filename)
static inline direntry_t* create_long_filename(BDRVVVFATState* s,const char* filename)
{
char buffer[258];
int length=short2long_name(buffer,filename),
number_of_entries=(length+25)/26,i;
a_direntry* entry;
direntry_t* entry;
for(i=0;i<number_of_entries;i++) {
entry=array_get_next(&(s->directory));
@ -450,53 +450,53 @@ static inline a_direntry* create_long_filename(BDRVVVFATState* s,const char* fil
return array_get(&(s->directory),s->directory.next-number_of_entries);
}
static char is_free(const a_direntry* direntry)
static char is_free(const direntry_t* direntry)
{
return direntry->name[0]==0xe5 || direntry->name[0]==0x00;
}
static char is_volume_label(const a_direntry* direntry)
static char is_volume_label(const direntry_t* direntry)
{
return direntry->attributes == 0x28;
}
static char is_long_name(const a_direntry* direntry)
static char is_long_name(const direntry_t* direntry)
{
return direntry->attributes == 0xf;
}
static char is_short_name(const a_direntry* direntry)
static char is_short_name(const direntry_t* direntry)
{
return !is_volume_label(direntry) && !is_long_name(direntry)
&& !is_free(direntry);
}
static char is_directory(const a_direntry* direntry)
static char is_directory(const direntry_t* direntry)
{
return direntry->attributes & 0x10 && direntry->name[0] != 0xe5;
}
static inline char is_dot(const a_direntry* direntry)
static inline char is_dot(const direntry_t* direntry)
{
return is_short_name(direntry) && direntry->name[0] == '.';
}
static char is_file(const a_direntry* direntry)
static char is_file(const direntry_t* direntry)
{
return is_short_name(direntry) && !is_directory(direntry);
}
static inline uint32_t begin_of_direntry(const a_direntry* direntry)
static inline uint32_t begin_of_direntry(const direntry_t* direntry)
{
return le16_to_cpu(direntry->begin)|(le16_to_cpu(direntry->begin_hi)<<16);
}
static inline uint32_t filesize_of_direntry(const a_direntry* direntry)
static inline uint32_t filesize_of_direntry(const direntry_t* direntry)
{
return le32_to_cpu(direntry->size);
}
static void set_begin_of_direntry(a_direntry* direntry, uint32_t begin)
static void set_begin_of_direntry(direntry_t* direntry, uint32_t begin)
{
direntry->begin = cpu_to_le16(begin & 0xffff);
direntry->begin_hi = cpu_to_le16((begin >> 16) & 0xffff);
@ -504,7 +504,7 @@ static void set_begin_of_direntry(a_direntry* direntry, uint32_t begin)
/* fat functions */
static inline uint8_t fat_chksum(const a_direntry* entry)
static inline uint8_t fat_chksum(const direntry_t* entry)
{
uint8_t chksum=0;
int i;
@ -603,12 +603,12 @@ static inline void init_fat(BDRVVVFATState* s)
/* TODO: in create_short_filename, 0xe5->0x05 is not yet handled! */
/* TODO: in parse_short_filename, 0x05->0xe5 is not yet handled! */
static inline a_direntry* create_short_and_long_name(BDRVVVFATState* s,
static inline direntry_t* create_short_and_long_name(BDRVVVFATState* s,
unsigned int directory_start, const char* filename, int is_dot)
{
int i,j,long_index=s->directory.next;
a_direntry* entry = NULL;
a_direntry* entry_long = NULL;
direntry_t* entry = NULL;
direntry_t* entry_long = NULL;
if(is_dot) {
entry=array_get_next(&(s->directory));
@ -646,7 +646,7 @@ static inline a_direntry* create_short_and_long_name(BDRVVVFATState* s,
/* mangle duplicates */
while(1) {
a_direntry* entry1=array_get(&(s->directory),directory_start);
direntry_t* entry1=array_get(&(s->directory),directory_start);
int j;
for(;entry1<entry;entry1++)
@ -693,12 +693,12 @@ static inline a_direntry* create_short_and_long_name(BDRVVVFATState* s,
*/
static int read_directory(BDRVVVFATState* s, int mapping_index)
{
a_mapping* mapping = array_get(&(s->mapping), mapping_index);
a_direntry* direntry;
mapping_t* mapping = array_get(&(s->mapping), mapping_index);
direntry_t* direntry;
const char* dirname = mapping->path;
int first_cluster = mapping->begin;
int parent_index = mapping->info.dir.parent_mapping_index;
a_mapping* parent_mapping = (a_mapping*)
mapping_t* parent_mapping = (mapping_t*)
(parent_index >= 0 ? array_get(&(s->mapping), parent_index) : NULL);
int first_cluster_of_parent = parent_mapping ? parent_mapping->begin : -1;
@ -720,7 +720,7 @@ static int read_directory(BDRVVVFATState* s, int mapping_index)
while((entry=readdir(dir))) {
unsigned int length=strlen(dirname)+2+strlen(entry->d_name);
char* buffer;
a_direntry* direntry;
direntry_t* direntry;
struct stat st;
int is_dot=!strcmp(entry->d_name,".");
int is_dotdot=!strcmp(entry->d_name,"..");
@ -762,7 +762,7 @@ static int read_directory(BDRVVVFATState* s, int mapping_index)
/* create mapping for this file */
if(!is_dot && !is_dotdot && (S_ISDIR(st.st_mode) || st.st_size)) {
s->current_mapping=(a_mapping*)array_get_next(&(s->mapping));
s->current_mapping=(mapping_t*)array_get_next(&(s->mapping));
s->current_mapping->begin=0;
s->current_mapping->end=st.st_size;
/*
@ -788,8 +788,8 @@ static int read_directory(BDRVVVFATState* s, int mapping_index)
/* fill with zeroes up to the end of the cluster */
while(s->directory.next%(0x10*s->sectors_per_cluster)) {
a_direntry* direntry=array_get_next(&(s->directory));
memset(direntry,0,sizeof(a_direntry));
direntry_t* direntry=array_get_next(&(s->directory));
memset(direntry,0,sizeof(direntry_t));
}
/* TODO: if there are more entries, bootsector has to be adjusted! */
@ -799,16 +799,16 @@ static int read_directory(BDRVVVFATState* s, int mapping_index)
int cur = s->directory.next;
array_ensure_allocated(&(s->directory), ROOT_ENTRIES - 1);
memset(array_get(&(s->directory), cur), 0,
(ROOT_ENTRIES - cur) * sizeof(a_direntry));
(ROOT_ENTRIES - cur) * sizeof(direntry_t));
}
/* reget the mapping, since s->mapping was possibly realloc()ed */
mapping = (a_mapping*)array_get(&(s->mapping), mapping_index);
mapping = (mapping_t*)array_get(&(s->mapping), mapping_index);
first_cluster += (s->directory.next - mapping->info.dir.first_dir_index)
* 0x20 / s->cluster_size;
mapping->end = first_cluster;
direntry = (a_direntry*)array_get(&(s->directory), mapping->dir_index);
direntry = (direntry_t*)array_get(&(s->directory), mapping->dir_index);
set_begin_of_direntry(direntry, mapping->begin);
return 0;
@ -830,19 +830,19 @@ static inline uint32_t sector_offset_in_cluster(BDRVVVFATState* s,off_t sector_n
}
#ifdef DBG
static a_direntry* get_direntry_for_mapping(BDRVVVFATState* s,a_mapping* mapping)
static direntry_t* get_direntry_for_mapping(BDRVVVFATState* s,mapping_t* mapping)
{
if(mapping->mode==MODE_UNDEFINED)
return 0;
return (a_direntry*)(s->directory.pointer+sizeof(a_direntry)*mapping->dir_index);
return (direntry_t*)(s->directory.pointer+sizeof(direntry_t)*mapping->dir_index);
}
#endif
static int init_directories(BDRVVVFATState* s,
const char* dirname)
{
a_bootsector* bootsector;
a_mapping* mapping;
bootsector_t* bootsector;
mapping_t* mapping;
unsigned int i;
unsigned int cluster;
@ -861,12 +861,12 @@ static int init_directories(BDRVVVFATState* s,
i = 1+s->sectors_per_cluster*0x200*8/s->fat_type;
s->sectors_per_fat=(s->sector_count+i)/i; /* round up */
array_init(&(s->mapping),sizeof(a_mapping));
array_init(&(s->directory),sizeof(a_direntry));
array_init(&(s->mapping),sizeof(mapping_t));
array_init(&(s->directory),sizeof(direntry_t));
/* add volume label */
{
a_direntry* entry=array_get_next(&(s->directory));
direntry_t* entry=array_get_next(&(s->directory));
entry->attributes=0x28; /* archive | volume label */
snprintf((char*)entry->name,11,"QEMU VVFAT");
}
@ -910,7 +910,7 @@ static int init_directories(BDRVVVFATState* s,
mapping->mode=MODE_NORMAL;
mapping->begin = cluster;
if (mapping->end > 0) {
a_direntry* direntry = array_get(&(s->directory),
direntry_t* direntry = array_get(&(s->directory),
mapping->dir_index);
mapping->end = cluster + 1 + (mapping->end-1)/s->cluster_size;
@ -954,7 +954,7 @@ static int init_directories(BDRVVVFATState* s,
s->current_mapping = NULL;
bootsector=(a_bootsector*)(s->first_sectors+(s->first_sectors_number-1)*0x200);
bootsector=(bootsector_t*)(s->first_sectors+(s->first_sectors_number-1)*0x200);
bootsector->jump[0]=0xeb;
bootsector->jump[1]=0x3e;
bootsector->jump[2]=0x90;
@ -1100,7 +1100,7 @@ static inline int find_mapping_for_cluster_aux(BDRVVVFATState* s,int cluster_num
{
int index3=index1+1;
while(1) {
a_mapping* mapping;
mapping_t* mapping;
index3=(index1+index2)/2;
mapping=array_get(&(s->mapping),index3);
assert(mapping->begin < mapping->end);
@ -1123,10 +1123,10 @@ static inline int find_mapping_for_cluster_aux(BDRVVVFATState* s,int cluster_num
}
}
static inline a_mapping* find_mapping_for_cluster(BDRVVVFATState* s,int cluster_num)
static inline mapping_t* find_mapping_for_cluster(BDRVVVFATState* s,int cluster_num)
{
int index=find_mapping_for_cluster_aux(s,cluster_num,0,s->mapping.next);
a_mapping* mapping;
mapping_t* mapping;
if(index>=s->mapping.next)
return NULL;
mapping=array_get(&(s->mapping),index);
@ -1140,13 +1140,13 @@ static inline a_mapping* find_mapping_for_cluster(BDRVVVFATState* s,int cluster_
* This function simply compares path == mapping->path. Since the mappings
* are sorted by cluster, this is expensive: O(n).
*/
static inline a_mapping* find_mapping_for_path(BDRVVVFATState* s,
static inline mapping_t* find_mapping_for_path(BDRVVVFATState* s,
const char* path)
{
int i;
for (i = 0; i < s->mapping.next; i++) {
a_mapping* mapping = array_get(&(s->mapping), i);
mapping_t* mapping = array_get(&(s->mapping), i);
if (mapping->first_mapping_index < 0 &&
!strcmp(path, mapping->path))
return mapping;
@ -1155,7 +1155,7 @@ static inline a_mapping* find_mapping_for_path(BDRVVVFATState* s,
return NULL;
}
static int open_file(BDRVVVFATState* s,a_mapping* mapping)
static int open_file(BDRVVVFATState* s,mapping_t* mapping)
{
if(!mapping)
return -1;
@ -1182,7 +1182,7 @@ static inline int read_cluster(BDRVVVFATState *s,int cluster_num)
|| s->current_mapping->begin>cluster_num
|| s->current_mapping->end<=cluster_num) {
/* binary search of mappings for file */
a_mapping* mapping=find_mapping_for_cluster(s,cluster_num);
mapping_t* mapping=find_mapping_for_cluster(s,cluster_num);
assert(!mapping || (cluster_num>=mapping->begin && cluster_num<mapping->end));
@ -1238,7 +1238,7 @@ static void hexdump(const void* address, uint32_t len)
}
}
static void print_direntry(const a_direntry* direntry)
static void print_direntry(const direntry_t* direntry)
{
int j = 0;
char buffer[1024];
@ -1270,7 +1270,7 @@ static void print_direntry(const a_direntry* direntry)
}
}
static void print_mapping(const a_mapping* mapping)
static void print_mapping(const mapping_t* mapping)
{
fprintf(stderr, "mapping (0x%x): begin, end = %d, %d, dir_index = %d, first_mapping_index = %d, name = %s, mode = 0x%x, " , (int)mapping, mapping->begin, mapping->end, mapping->dir_index, mapping->first_mapping_index, mapping->path, mapping->mode);
if (mapping->mode & MODE_DIRECTORY)
@ -1346,7 +1346,7 @@ DLOG(fprintf(stderr, "sector %d not allocated\n", (int)sector_num));
*
*/
typedef struct commit {
typedef struct commit_t {
char* path;
union {
struct { uint32_t cluster; } rename;
@ -1358,14 +1358,14 @@ typedef struct commit {
enum {
ACTION_RENAME, ACTION_WRITEOUT, ACTION_NEW_FILE, ACTION_MKDIR
} action;
} a_commit;
} commit_t;
static void clear_commits(BDRVVVFATState* s)
{
int i;
DLOG(fprintf(stderr, "clear_commits (%d commits)\n", s->commits.next));
for (i = 0; i < s->commits.next; i++) {
a_commit* commit = array_get(&(s->commits), i);
commit_t* commit = array_get(&(s->commits), i);
assert(commit->path || commit->action == ACTION_WRITEOUT);
if (commit->action != ACTION_WRITEOUT) {
assert(commit->path);
@ -1379,7 +1379,7 @@ DLOG(fprintf(stderr, "clear_commits (%d commits)\n", s->commits.next));
static void schedule_rename(BDRVVVFATState* s,
uint32_t cluster, char* new_path)
{
a_commit* commit = array_get_next(&(s->commits));
commit_t* commit = array_get_next(&(s->commits));
commit->path = new_path;
commit->param.rename.cluster = cluster;
commit->action = ACTION_RENAME;
@ -1388,7 +1388,7 @@ static void schedule_rename(BDRVVVFATState* s,
static void schedule_writeout(BDRVVVFATState* s,
int dir_index, uint32_t modified_offset)
{
a_commit* commit = array_get_next(&(s->commits));
commit_t* commit = array_get_next(&(s->commits));
commit->path = NULL;
commit->param.writeout.dir_index = dir_index;
commit->param.writeout.modified_offset = modified_offset;
@ -1398,7 +1398,7 @@ static void schedule_writeout(BDRVVVFATState* s,
static void schedule_new_file(BDRVVVFATState* s,
char* path, uint32_t first_cluster)
{
a_commit* commit = array_get_next(&(s->commits));
commit_t* commit = array_get_next(&(s->commits));
commit->path = path;
commit->param.new_file.first_cluster = first_cluster;
commit->action = ACTION_NEW_FILE;
@ -1406,7 +1406,7 @@ static void schedule_new_file(BDRVVVFATState* s,
static void schedule_mkdir(BDRVVVFATState* s, uint32_t cluster, char* path)
{
a_commit* commit = array_get_next(&(s->commits));
commit_t* commit = array_get_next(&(s->commits));
commit->path = path;
commit->param.mkdir.cluster = cluster;
commit->action = ACTION_MKDIR;
@ -1431,7 +1431,7 @@ static void lfn_init(long_file_name* lfn)
/* return 0 if parsed successfully, > 0 if no long name, < 0 if error */
static int parse_long_name(long_file_name* lfn,
const a_direntry* direntry)
const direntry_t* direntry)
{
int i, j, offset;
const unsigned char* pointer = (const unsigned char*)direntry;
@ -1474,7 +1474,7 @@ static int parse_long_name(long_file_name* lfn,
/* returns 0 if successful, >0 if no short_name, and <0 on error */
static int parse_short_name(BDRVVVFATState* s,
long_file_name* lfn, a_direntry* direntry)
long_file_name* lfn, direntry_t* direntry)
{
int i, j;
@ -1566,7 +1566,7 @@ static const char* get_basename(const char* path)
*/
typedef enum {
USED_DIRECTORY = 1, USED_FILE = 2, USED_ANY = 3, USED_ALLOCATED = 4
} e_used;
} used_t;
/*
* get_cluster_count_for_direntry() not only determines how many clusters
@ -1579,7 +1579,7 @@ typedef enum {
* assumed to be *not* deleted (and *only* those).
*/
static uint32_t get_cluster_count_for_direntry(BDRVVVFATState* s,
a_direntry* direntry, const char* path)
direntry_t* direntry, const char* path)
{
/*
* This is a little bit tricky:
@ -1605,7 +1605,7 @@ static uint32_t get_cluster_count_for_direntry(BDRVVVFATState* s,
uint32_t cluster_num = begin_of_direntry(direntry);
uint32_t offset = 0;
int first_mapping_index = -1;
a_mapping* mapping = NULL;
mapping_t* mapping = NULL;
const char* basename2 = NULL;
vvfat_close_current_file(s);
@ -1730,8 +1730,8 @@ static int check_directory_consistency(BDRVVVFATState *s,
{
int ret = 0;
unsigned char* cluster = qemu_malloc(s->cluster_size);
a_direntry* direntries = (a_direntry*)cluster;
a_mapping* mapping = find_mapping_for_cluster(s, cluster_num);
direntry_t* direntries = (direntry_t*)cluster;
mapping_t* mapping = find_mapping_for_cluster(s, cluster_num);
long_file_name lfn;
int path_len = strlen(path);
@ -1889,7 +1889,7 @@ DLOG(checkpoint());
* (check_directory_consistency() will unmark those still present). */
if (s->qcow)
for (i = 0; i < s->mapping.next; i++) {
a_mapping* mapping = array_get(&(s->mapping), i);
mapping_t* mapping = array_get(&(s->mapping), i);
if (mapping->first_mapping_index < 0)
mapping->mode |= MODE_DELETED;
}
@ -1929,7 +1929,7 @@ static inline void adjust_mapping_indices(BDRVVVFATState* s,
int i;
for (i = 0; i < s->mapping.next; i++) {
a_mapping* mapping = array_get(&(s->mapping), i);
mapping_t* mapping = array_get(&(s->mapping), i);
#define ADJUST_MAPPING_INDEX(name) \
if (mapping->name >= offset) \
@ -1942,7 +1942,7 @@ static inline void adjust_mapping_indices(BDRVVVFATState* s,
}
/* insert or update mapping */
static a_mapping* insert_mapping(BDRVVVFATState* s,
static mapping_t* insert_mapping(BDRVVVFATState* s,
uint32_t begin, uint32_t end)
{
/*
@ -1953,8 +1953,8 @@ static a_mapping* insert_mapping(BDRVVVFATState* s,
* - replace name
*/
int index = find_mapping_for_cluster_aux(s, begin, 0, s->mapping.next);
a_mapping* mapping = NULL;
a_mapping* first_mapping = array_get(&(s->mapping), 0);
mapping_t* mapping = NULL;
mapping_t* first_mapping = array_get(&(s->mapping), 0);
if (index < s->mapping.next && (mapping = array_get(&(s->mapping), index))
&& mapping->begin < begin) {
@ -1971,12 +1971,12 @@ static a_mapping* insert_mapping(BDRVVVFATState* s,
mapping->begin = begin;
mapping->end = end;
DLOG(a_mapping* next_mapping;
DLOG(mapping_t* next_mapping;
assert(index + 1 >= s->mapping.next ||
((next_mapping = array_get(&(s->mapping), index + 1)) &&
next_mapping->begin >= end)));
if (s->current_mapping && first_mapping != (a_mapping*)s->mapping.pointer)
if (s->current_mapping && first_mapping != (mapping_t*)s->mapping.pointer)
s->current_mapping = array_get(&(s->mapping),
s->current_mapping - first_mapping);
@ -1985,8 +1985,8 @@ assert(index + 1 >= s->mapping.next ||
static int remove_mapping(BDRVVVFATState* s, int mapping_index)
{
a_mapping* mapping = array_get(&(s->mapping), mapping_index);
a_mapping* first_mapping = array_get(&(s->mapping), 0);
mapping_t* mapping = array_get(&(s->mapping), mapping_index);
mapping_t* first_mapping = array_get(&(s->mapping), 0);
/* free mapping */
if (mapping->first_mapping_index < 0)
@ -1998,7 +1998,7 @@ static int remove_mapping(BDRVVVFATState* s, int mapping_index)
/* adjust all references to mappings */
adjust_mapping_indices(s, mapping_index, -1);
if (s->current_mapping && first_mapping != (a_mapping*)s->mapping.pointer)
if (s->current_mapping && first_mapping != (mapping_t*)s->mapping.pointer)
s->current_mapping = array_get(&(s->mapping),
s->current_mapping - first_mapping);
@ -2009,7 +2009,7 @@ static void adjust_dirindices(BDRVVVFATState* s, int offset, int adjust)
{
int i;
for (i = 0; i < s->mapping.next; i++) {
a_mapping* mapping = array_get(&(s->mapping), i);
mapping_t* mapping = array_get(&(s->mapping), i);
if (mapping->dir_index >= offset)
mapping->dir_index += adjust;
if ((mapping->mode & MODE_DIRECTORY) &&
@ -2018,14 +2018,14 @@ static void adjust_dirindices(BDRVVVFATState* s, int offset, int adjust)
}
}
static a_direntry* insert_direntries(BDRVVVFATState* s,
static direntry_t* insert_direntries(BDRVVVFATState* s,
int dir_index, int count)
{
/*
* make room in s->directory,
* adjust_dirindices
*/
a_direntry* result = array_insert(&(s->directory), dir_index, count);
direntry_t* result = array_insert(&(s->directory), dir_index, count);
if (result == NULL)
return NULL;
adjust_dirindices(s, dir_index, count);
@ -2050,8 +2050,8 @@ static int remove_direntries(BDRVVVFATState* s, int dir_index, int count)
static int commit_mappings(BDRVVVFATState* s,
uint32_t first_cluster, int dir_index)
{
a_mapping* mapping = find_mapping_for_cluster(s, first_cluster);
a_direntry* direntry = array_get(&(s->directory), dir_index);
mapping_t* mapping = find_mapping_for_cluster(s, first_cluster);
direntry_t* direntry = array_get(&(s->directory), dir_index);
uint32_t cluster = first_cluster;
vvfat_close_current_file(s);
@ -2083,7 +2083,7 @@ static int commit_mappings(BDRVVVFATState* s,
if (!fat_eof(s, c1)) {
int i = find_mapping_for_cluster_aux(s, c1, 0, s->mapping.next);
a_mapping* next_mapping = i >= s->mapping.next ? NULL :
mapping_t* next_mapping = i >= s->mapping.next ? NULL :
array_get(&(s->mapping), i);
if (next_mapping == NULL || next_mapping->begin > c1) {
@ -2127,9 +2127,9 @@ static int commit_mappings(BDRVVVFATState* s,
static int commit_direntries(BDRVVVFATState* s,
int dir_index, int parent_mapping_index)
{
a_direntry* direntry = array_get(&(s->directory), dir_index);
direntry_t* direntry = array_get(&(s->directory), dir_index);
uint32_t first_cluster = dir_index == 0 ? 0 : begin_of_direntry(direntry);
a_mapping* mapping = find_mapping_for_cluster(s, first_cluster);
mapping_t* mapping = find_mapping_for_cluster(s, first_cluster);
int factor = 0x10 * s->sectors_per_cluster;
int old_cluster_count, new_cluster_count;
@ -2207,10 +2207,10 @@ DLOG(fprintf(stderr, "commit_direntries for %s, parent_mapping_index %d\n", mapp
static int commit_one_file(BDRVVVFATState* s,
int dir_index, uint32_t offset)
{
a_direntry* direntry = array_get(&(s->directory), dir_index);
direntry_t* direntry = array_get(&(s->directory), dir_index);
uint32_t c = begin_of_direntry(direntry);
uint32_t first_cluster = c;
a_mapping* mapping = find_mapping_for_cluster(s, c);
mapping_t* mapping = find_mapping_for_cluster(s, c);
uint32_t size = filesize_of_direntry(direntry);
char* cluster = qemu_malloc(s->cluster_size);
uint32_t i;
@ -2268,14 +2268,14 @@ static void check1(BDRVVVFATState* s)
{
int i;
for (i = 0; i < s->mapping.next; i++) {
a_mapping* mapping = array_get(&(s->mapping), i);
mapping_t* mapping = array_get(&(s->mapping), i);
if (mapping->mode & MODE_DELETED) {
fprintf(stderr, "deleted\n");
continue;
}
assert(mapping->dir_index >= 0);
assert(mapping->dir_index < s->directory.next);
a_direntry* direntry = array_get(&(s->directory), mapping->dir_index);
direntry_t* direntry = array_get(&(s->directory), mapping->dir_index);
assert(mapping->begin == begin_of_direntry(direntry) || mapping->first_mapping_index >= 0);
if (mapping->mode & MODE_DIRECTORY) {
assert(mapping->info.dir.first_dir_index + 0x10 * s->sectors_per_cluster * (mapping->end - mapping->begin) <= s->directory.next);
@ -2291,10 +2291,10 @@ static void check2(BDRVVVFATState* s)
int first_mapping = -1;
for (i = 0; i < s->directory.next; i++) {
a_direntry* direntry = array_get(&(s->directory), i);
direntry_t* direntry = array_get(&(s->directory), i);
if (is_short_name(direntry) && begin_of_direntry(direntry)) {
a_mapping* mapping = find_mapping_for_cluster(s, begin_of_direntry(direntry));
mapping_t* mapping = find_mapping_for_cluster(s, begin_of_direntry(direntry));
assert(mapping);
assert(mapping->dir_index == i || is_dot(direntry));
assert(mapping->begin == begin_of_direntry(direntry) || is_dot(direntry));
@ -2305,7 +2305,7 @@ static void check2(BDRVVVFATState* s)
int j, count = 0;
for (j = 0; j < s->mapping.next; j++) {
a_mapping* mapping = array_get(&(s->mapping), j);
mapping_t* mapping = array_get(&(s->mapping), j);
if (mapping->mode & MODE_DELETED)
continue;
if (mapping->mode & MODE_DIRECTORY) {
@ -2318,7 +2318,7 @@ static void check2(BDRVVVFATState* s)
if (mapping->info.dir.parent_mapping_index < 0)
assert(j == 0);
else {
a_mapping* parent = array_get(&(s->mapping), mapping->info.dir.parent_mapping_index);
mapping_t* parent = array_get(&(s->mapping), mapping->info.dir.parent_mapping_index);
assert(parent->mode & MODE_DIRECTORY);
assert(parent->info.dir.first_dir_index < mapping->info.dir.first_dir_index);
}
@ -2339,15 +2339,15 @@ static int handle_renames_and_mkdirs(BDRVVVFATState* s)
#ifdef DEBUG
fprintf(stderr, "handle_renames\n");
for (i = 0; i < s->commits.next; i++) {
a_commit* commit = array_get(&(s->commits), i);
commit_t* commit = array_get(&(s->commits), i);
fprintf(stderr, "%d, %s (%d, %d)\n", i, commit->path ? commit->path : "(null)", commit->param.rename.cluster, commit->action);
}
#endif
for (i = 0; i < s->commits.next;) {
a_commit* commit = array_get(&(s->commits), i);
commit_t* commit = array_get(&(s->commits), i);
if (commit->action == ACTION_RENAME) {
a_mapping* mapping = find_mapping_for_cluster(s,
mapping_t* mapping = find_mapping_for_cluster(s,
commit->param.rename.cluster);
char* old_path = mapping->path;
@ -2360,7 +2360,7 @@ static int handle_renames_and_mkdirs(BDRVVVFATState* s)
int l1 = strlen(mapping->path);
int l2 = strlen(old_path);
int diff = l1 - l2;
a_direntry* direntry = array_get(&(s->directory),
direntry_t* direntry = array_get(&(s->directory),
mapping->info.dir.first_dir_index);
uint32_t c = mapping->begin;
int i = 0;
@ -2368,10 +2368,10 @@ static int handle_renames_and_mkdirs(BDRVVVFATState* s)
/* recurse */
while (!fat_eof(s, c)) {
do {
a_direntry* d = direntry + i;
direntry_t* d = direntry + i;
if (is_file(d) || (is_directory(d) && !is_dot(d))) {
a_mapping* m = find_mapping_for_cluster(s,
mapping_t* m = find_mapping_for_cluster(s,
begin_of_direntry(d));
int l = strlen(m->path);
char* new_path = qemu_malloc(l + diff + 1);
@ -2394,7 +2394,7 @@ static int handle_renames_and_mkdirs(BDRVVVFATState* s)
array_remove(&(s->commits), i);
continue;
} else if (commit->action == ACTION_MKDIR) {
a_mapping* mapping;
mapping_t* mapping;
int j, parent_path_len;
#ifdef __MINGW32__
@ -2422,7 +2422,7 @@ static int handle_renames_and_mkdirs(BDRVVVFATState* s)
parent_path_len = strlen(commit->path)
- strlen(get_basename(commit->path)) - 1;
for (j = 0; j < s->mapping.next; j++) {
a_mapping* m = array_get(&(s->mapping), j);
mapping_t* m = array_get(&(s->mapping), j);
if (m->first_mapping_index < 0 && m != mapping &&
!strncmp(m->path, mapping->path, parent_path_len) &&
strlen(m->path) == parent_path_len)
@ -2450,17 +2450,17 @@ static int handle_commits(BDRVVVFATState* s)
vvfat_close_current_file(s);
for (i = 0; !fail && i < s->commits.next; i++) {
a_commit* commit = array_get(&(s->commits), i);
commit_t* commit = array_get(&(s->commits), i);
switch(commit->action) {
case ACTION_RENAME: case ACTION_MKDIR:
assert(0);
fail = -2;
break;
case ACTION_WRITEOUT: {
a_direntry* entry = array_get(&(s->directory),
direntry_t* entry = array_get(&(s->directory),
commit->param.writeout.dir_index);
uint32_t begin = begin_of_direntry(entry);
a_mapping* mapping = find_mapping_for_cluster(s, begin);
mapping_t* mapping = find_mapping_for_cluster(s, begin);
assert(mapping);
assert(mapping->begin == begin);
@ -2474,8 +2474,8 @@ static int handle_commits(BDRVVVFATState* s)
}
case ACTION_NEW_FILE: {
int begin = commit->param.new_file.first_cluster;
a_mapping* mapping = find_mapping_for_cluster(s, begin);
a_direntry* entry;
mapping_t* mapping = find_mapping_for_cluster(s, begin);
direntry_t* entry;
int i;
/* find direntry */
@ -2530,9 +2530,9 @@ static int handle_deletes(BDRVVVFATState* s)
deleted = 0;
for (i = 1; i < s->mapping.next; i++) {
a_mapping* mapping = array_get(&(s->mapping), i);
mapping_t* mapping = array_get(&(s->mapping), i);
if (mapping->mode & MODE_DELETED) {
a_direntry* entry = array_get(&(s->directory),
direntry_t* entry = array_get(&(s->directory),
mapping->dir_index);
if (is_free(entry)) {
@ -2550,7 +2550,7 @@ static int handle_deletes(BDRVVVFATState* s)
}
for (j = 1; j < s->mapping.next; j++) {
a_mapping* m = array_get(&(s->mapping), j);
mapping_t* m = array_get(&(s->mapping), j);
if (m->mode & MODE_DIRECTORY &&
m->info.dir.first_dir_index >
first_dir_index &&
@ -2666,7 +2666,7 @@ DLOG(checkpoint());
for (i = sector2cluster(s, sector_num);
i <= sector2cluster(s, sector_num + nb_sectors - 1);) {
a_mapping* mapping = find_mapping_for_cluster(s, i);
mapping_t* mapping = find_mapping_for_cluster(s, i);
if (mapping) {
if (mapping->read_only) {
fprintf(stderr, "Tried to write to write-protected file %s\n",
@ -2678,7 +2678,7 @@ DLOG(checkpoint());
int begin = cluster2sector(s, i);
int end = begin + s->sectors_per_cluster, k;
int dir_index;
const a_direntry* direntries;
const direntry_t* direntries;
long_file_name lfn;
lfn_init(&lfn);
@ -2689,7 +2689,7 @@ DLOG(checkpoint());
end = sector_num + nb_sectors;
dir_index = mapping->dir_index +
0x10 * (begin - mapping->begin * s->sectors_per_cluster);
direntries = (a_direntry*)(buf + 0x200 * (begin - sector_num));
direntries = (direntry_t*)(buf + 0x200 * (begin - sector_num));
for (k = 0; k < (end - begin) * 0x10; k++) {
/* do not allow non-ASCII filenames */
@ -2702,7 +2702,7 @@ DLOG(checkpoint());
(direntries[k].attributes & 1)) {
if (memcmp(direntries + k,
array_get(&(s->directory), dir_index + k),
sizeof(a_direntry))) {
sizeof(direntry_t))) {
fprintf(stderr, "Warning: tried to write to write-protected file\n");
return -1;
}
@ -2774,7 +2774,7 @@ static int enable_write_target(BDRVVVFATState *s)
int size = sector2cluster(s, s->sector_count);
s->used_clusters = calloc(size, 1);
array_init(&(s->commits), sizeof(a_commit));
array_init(&(s->commits), sizeof(commit_t));
s->qcow_filename = qemu_malloc(1024);
get_tmp_filename(s->qcow_filename, 1024);
@ -2833,15 +2833,15 @@ block_init(bdrv_vvfat_init);
#ifdef DEBUG
static void checkpoint(void) {
assert(((a_mapping*)array_get(&(vvv->mapping), 0))->end == 2);
assert(((mapping_t*)array_get(&(vvv->mapping), 0))->end == 2);
check1(vvv);
check2(vvv);
assert(!vvv->current_mapping || vvv->current_fd || (vvv->current_mapping->mode & MODE_DIRECTORY));
#if 0
if (((a_direntry*)vvv->directory.pointer)[1].attributes != 0xf)
if (((direntry_t*)vvv->directory.pointer)[1].attributes != 0xf)
fprintf(stderr, "Nonono!\n");
a_mapping* mapping;
a_direntry* direntry;
mapping_t* mapping;
direntry_t* direntry;
assert(vvv->mapping.size >= vvv->mapping.item_size * vvv->mapping.next);
assert(vvv->directory.size >= vvv->directory.item_size * vvv->directory.next);
if (vvv->mapping.next<47)

10
console.c
View File

@ -110,12 +110,12 @@ typedef enum {
GRAPHIC_CONSOLE,
TEXT_CONSOLE,
TEXT_CONSOLE_FIXED_SIZE
} e_console_type;
} console_type_t;
/* ??? This is mis-named.
It is used for both text and graphical consoles. */
struct TextConsole {
e_console_type console_type;
console_type_t console_type;
DisplayState *ds;
/* Graphic console state. */
vga_hw_update_ptr hw_update;
@ -183,7 +183,7 @@ void vga_hw_screen_dump(const char *filename)
active_console = previous_active_console;
}
void vga_hw_text_update(a_console_ch *chardata)
void vga_hw_text_update(console_ch_t *chardata)
{
if (active_console && active_console->hw_text_update)
active_console->hw_text_update(active_console->hw, chardata);
@ -1197,7 +1197,7 @@ static void text_console_invalidate(void *opaque)
console_refresh(s);
}
static void text_console_update(void *opaque, a_console_ch *chardata)
static void text_console_update(void *opaque, console_ch_t *chardata)
{
TextConsole *s = (TextConsole *) opaque;
int i, j, src;
@ -1236,7 +1236,7 @@ static TextConsole *get_graphic_console(DisplayState *ds)
return NULL;
}
static TextConsole *new_console(DisplayState *ds, e_console_type console_type)
static TextConsole *new_console(DisplayState *ds, console_type_t console_type)
{
TextConsole *s;
int i;

8
console.h
View File

@ -279,8 +279,8 @@ static inline int ds_get_bytes_per_pixel(DisplayState *ds)
return ds->surface->pf.bytes_per_pixel;
}
typedef unsigned long a_console_ch;
static inline void console_write_ch(a_console_ch *dest, uint32_t ch)
typedef unsigned long console_ch_t;
static inline void console_write_ch(console_ch_t *dest, uint32_t ch)
{
cpu_to_le32wu((uint32_t *) dest, ch);
}
@ -288,7 +288,7 @@ static inline void console_write_ch(a_console_ch *dest, uint32_t ch)
typedef void (*vga_hw_update_ptr)(void *);
typedef void (*vga_hw_invalidate_ptr)(void *);
typedef void (*vga_hw_screen_dump_ptr)(void *, const char *);
typedef void (*vga_hw_text_update_ptr)(void *, a_console_ch *);
typedef void (*vga_hw_text_update_ptr)(void *, console_ch_t *);
DisplayState *graphic_console_init(vga_hw_update_ptr update,
vga_hw_invalidate_ptr invalidate,
@ -299,7 +299,7 @@ DisplayState *graphic_console_init(vga_hw_update_ptr update,
void vga_hw_update(void);
void vga_hw_invalidate(void);
void vga_hw_screen_dump(const char *filename);
void vga_hw_text_update(a_console_ch *chardata);
void vga_hw_text_update(console_ch_t *chardata);
int is_graphic_console(void);
int is_fixedsize_console(void);

22
cpu-all.h
View File

@ -814,7 +814,7 @@ void cpu_reset(CPUState *s);
/* Return the physical page corresponding to a virtual one. Use it
only for debugging because no protection checks are done. Return -1
if no page found. */
a_target_phys_addr cpu_get_phys_page_debug(CPUState *env, target_ulong addr);
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr);
#define CPU_LOG_TB_OUT_ASM (1 << 0)
#define CPU_LOG_TB_IN_ASM (1 << 1)
@ -847,8 +847,8 @@ int cpu_str_to_log_mask(const char *str);
extern int phys_ram_fd;
extern uint8_t *phys_ram_dirty;
extern a_ram_addr ram_size;
extern a_ram_addr last_ram_offset;
extern ram_addr_t ram_size;
extern ram_addr_t last_ram_offset;
/* physical memory access */
@ -876,23 +876,23 @@ int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
#define MIGRATION_DIRTY_FLAG 0x08
/* read dirty bit (return 0 or 1) */
static inline int cpu_physical_memory_is_dirty(a_ram_addr addr)
static inline int cpu_physical_memory_is_dirty(ram_addr_t addr)
{
return phys_ram_dirty[addr >> TARGET_PAGE_BITS] == 0xff;
}
static inline int cpu_physical_memory_get_dirty(a_ram_addr addr,
static inline int cpu_physical_memory_get_dirty(ram_addr_t addr,
int dirty_flags)
{
return phys_ram_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags;
}
static inline void cpu_physical_memory_set_dirty(a_ram_addr addr)
static inline void cpu_physical_memory_set_dirty(ram_addr_t addr)
{
phys_ram_dirty[addr >> TARGET_PAGE_BITS] = 0xff;
}
void cpu_physical_memory_reset_dirty(a_ram_addr start, a_ram_addr end,
void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
int dirty_flags);
void cpu_tlb_update_dirty(CPUState *env);
@ -900,8 +900,8 @@ int cpu_physical_memory_set_dirty_tracking(int enable);
int cpu_physical_memory_get_dirty_tracking(void);
int cpu_physical_sync_dirty_bitmap(a_target_phys_addr start_addr,
a_target_phys_addr end_addr);
int cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr,
target_phys_addr_t end_addr);
void dump_exec_info(FILE *f,
int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
@ -911,9 +911,9 @@ void dump_exec_info(FILE *f,
* batching which can make a major impact on performance when using
* virtualization.
*/
void qemu_register_coalesced_mmio(a_target_phys_addr addr, a_ram_addr size);
void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
void qemu_unregister_coalesced_mmio(a_target_phys_addr addr, a_ram_addr size);
void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
/*******************************************/
/* host CPU ticks (if available) */

66
cpu-common.h
View File

@ -10,69 +10,69 @@
#include "bswap.h"
/* address in the RAM (different from a physical address) */
typedef unsigned long a_ram_addr;
typedef unsigned long ram_addr_t;
/* memory API */
typedef void CPUWriteMemoryFunc(void *opaque, a_target_phys_addr addr, uint32_t value);
typedef uint32_t CPUReadMemoryFunc(void *opaque, a_target_phys_addr addr);
typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
void cpu_register_physical_memory_offset(a_target_phys_addr start_addr,
a_ram_addr size,
a_ram_addr phys_offset,
a_ram_addr region_offset);
static inline void cpu_register_physical_memory(a_target_phys_addr start_addr,
a_ram_addr size,
a_ram_addr phys_offset)
void cpu_register_physical_memory_offset(target_phys_addr_t start_addr,
ram_addr_t size,
ram_addr_t phys_offset,
ram_addr_t region_offset);
static inline void cpu_register_physical_memory(target_phys_addr_t start_addr,
ram_addr_t size,
ram_addr_t phys_offset)
{
cpu_register_physical_memory_offset(start_addr, size, phys_offset, 0);
}
a_ram_addr cpu_get_physical_page_desc(a_target_phys_addr addr);
a_ram_addr qemu_ram_alloc(a_ram_addr);
void qemu_ram_free(a_ram_addr addr);
ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr);
ram_addr_t qemu_ram_alloc(ram_addr_t);
void qemu_ram_free(ram_addr_t addr);
/* This should only be used for ram local to a device. */
void *qemu_get_ram_ptr(a_ram_addr addr);
void *qemu_get_ram_ptr(ram_addr_t addr);
/* This should not be used by devices. */
a_ram_addr qemu_ram_addr_from_host(void *ptr);
ram_addr_t qemu_ram_addr_from_host(void *ptr);
int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read,
CPUWriteMemoryFunc * const *mem_write,
void *opaque);
void cpu_unregister_io_memory(int table_address);
void cpu_physical_memory_rw(a_target_phys_addr addr, uint8_t *buf,
void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
int len, int is_write);
static inline void cpu_physical_memory_read(a_target_phys_addr addr,
static inline void cpu_physical_memory_read(target_phys_addr_t addr,
uint8_t *buf, int len)
{
cpu_physical_memory_rw(addr, buf, len, 0);
}
static inline void cpu_physical_memory_write(a_target_phys_addr addr,
static inline void cpu_physical_memory_write(target_phys_addr_t addr,
const uint8_t *buf, int len)
{
cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1);
}
void *cpu_physical_memory_map(a_target_phys_addr addr,
a_target_phys_addr *plen,
void *cpu_physical_memory_map(target_phys_addr_t addr,
target_phys_addr_t *plen,
int is_write);
void cpu_physical_memory_unmap(void *buffer, a_target_phys_addr len,
int is_write, a_target_phys_addr access_len);
void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
int is_write, target_phys_addr_t access_len);
void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque));
void cpu_unregister_map_client(void *cookie);
uint32_t ldub_phys(a_target_phys_addr addr);
uint32_t lduw_phys(a_target_phys_addr addr);
uint32_t ldl_phys(a_target_phys_addr addr);
uint64_t ldq_phys(a_target_phys_addr addr);
void stl_phys_notdirty(a_target_phys_addr addr, uint32_t val);
void stq_phys_notdirty(a_target_phys_addr addr, uint64_t val);
void stb_phys(a_target_phys_addr addr, uint32_t val);
void stw_phys(a_target_phys_addr addr, uint32_t val);
void stl_phys(a_target_phys_addr addr, uint32_t val);
void stq_phys(a_target_phys_addr addr, uint64_t val);
uint32_t ldub_phys(target_phys_addr_t addr);
uint32_t lduw_phys(target_phys_addr_t addr);
uint32_t ldl_phys(target_phys_addr_t addr);
uint64_t ldq_phys(target_phys_addr_t addr);
void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val);
void stb_phys(target_phys_addr_t addr, uint32_t val);
void stw_phys(target_phys_addr_t addr, uint32_t val);
void stl_phys(target_phys_addr_t addr, uint32_t val);
void stq_phys(target_phys_addr_t addr, uint64_t val);
void cpu_physical_memory_write_rom(a_target_phys_addr addr,
void cpu_physical_memory_write_rom(target_phys_addr_t addr,
const uint8_t *buf, int len);
#define IO_MEM_SHIFT 3

10
cpu-defs.h
View File

@ -95,15 +95,15 @@ typedef struct CPUTLBEntry {
use the corresponding iotlb value. */
#if TARGET_PHYS_ADDR_BITS == 64
/* on i386 Linux make sure it is aligned */
a_target_phys_addr addend __attribute__((aligned(8)));
target_phys_addr_t addend __attribute__((aligned(8)));
#else
a_target_phys_addr addend;
target_phys_addr_t addend;
#endif
/* padding to get a power of two size */
uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) -
(sizeof(target_ulong) * 3 +
((-sizeof(target_ulong) * 3) & (sizeof(a_target_phys_addr) - 1)) +
sizeof(a_target_phys_addr))];
((-sizeof(target_ulong) * 3) & (sizeof(target_phys_addr_t) - 1)) +
sizeof(target_phys_addr_t))];
} CPUTLBEntry;
#ifdef HOST_WORDS_BIGENDIAN
@ -152,7 +152,7 @@ typedef struct CPUWatchpoint {
volatile sig_atomic_t exit_request; \
/* The meaning of the MMU modes is defined in the target code. */ \
CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
a_target_phys_addr iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \
/* buffer for temporaries in the code generator */ \
long temp_buf[CPU_TEMP_BUF_NLONGS]; \

4
curses.c
View File

@ -40,7 +40,7 @@
#define FONT_HEIGHT 16
#define FONT_WIDTH 8
static a_console_ch screen[160 * 100];
static console_ch_t screen[160 * 100];
static WINDOW *screenpad = NULL;
static int width, height, gwidth, gheight, invalidate;
static int px, py, sminx, sminy, smaxx, smaxy;
@ -158,7 +158,7 @@ static void curses_cursor_position(DisplayState *ds, int x, int y)
#include "curses_keys.h"
static a_kbd_layout *kbd_layout = NULL;
static kbd_layout_t *kbd_layout = NULL;
static int keycode2keysym[CURSES_KEYS];
static void curses_refresh(DisplayState *ds)

2
curses_keys.h
View File

@ -243,7 +243,7 @@ static const int curses2keysym[CURSES_KEYS] = {
};
static const a_name2keysym name2keysym[] = {
static const name2keysym_t name2keysym[] = {
/* Plain ASCII */
{ "space", 0x020 },
{ "exclam", 0x021 },

2
darwin-user/commpage.c
View File

@ -109,7 +109,7 @@ static struct commpage_entry commpage_entries[] =
COMMPAGE_ENTRY(add_atomic_word64, 0, 0x1c0, unimpl_commpage, CALL_INDIRECT | HAS_PTR),
COMMPAGE_ENTRY(mach_absolute_time, 0, 0x200, unimpl_commpage, CALL_INDIRECT),
COMMPAGE_ENTRY(a_spinlockry, 1, 0x220, unimpl_commpage, CALL_INDIRECT),
COMMPAGE_ENTRY(spinlock_try, 1, 0x220, unimpl_commpage, CALL_INDIRECT),
COMMPAGE_ENTRY(spinlock_lock, 1, 0x260, OSSpinLockLock, CALL_DIRECT),
COMMPAGE_ENTRY(spinlock_unlock, 1, 0x2a0, OSSpinLockUnlock, CALL_DIRECT),
COMMPAGE_ENTRY(pthread_getspecific, 0, 0x2c0, unimpl_commpage, CALL_INDIRECT),

2
darwin-user/machload.c
View File

@ -101,7 +101,7 @@ typedef struct mach_i386_thread_state {
unsigned int es;
unsigned int fs;
unsigned int gs;
};
} mach_i386_thread_state_t;
void bswap_i386_thread_state(struct mach_i386_thread_state *ts)
{

2
darwin-user/qemu.h
View File

@ -10,7 +10,7 @@
#include "gdbstub.h"
typedef siginfo_t a_target_siginfo;
typedef siginfo_t target_siginfo_t;
#define target_sigaction sigaction
#ifdef TARGET_I386
struct target_pt_regs {

2
disas.h
View File

@ -22,7 +22,7 @@ struct syminfo;
struct elf32_sym;
struct elf64_sym;
typedef const char *(*lookup_symbol_t)(struct syminfo *s, a_target_phys_addr orig_addr);
typedef const char *(*lookup_symbol_t)(struct syminfo *s, target_phys_addr_t orig_addr);
struct syminfo {
lookup_symbol_t lookup_symbol;

8
dma-helpers.c
View File

@ -18,8 +18,8 @@ void qemu_sglist_init(QEMUSGList *qsg, int alloc_hint)
qsg->size = 0;
}
void qemu_sglist_add(QEMUSGList *qsg, a_target_phys_addr base,
a_target_phys_addr len)
void qemu_sglist_add(QEMUSGList *qsg, target_phys_addr_t base,
target_phys_addr_t len)
{
if (qsg->nsg == qsg->nalloc) {
qsg->nalloc = 2 * qsg->nalloc + 1;
@ -44,7 +44,7 @@ typedef struct {
uint64_t sector_num;
int is_write;
int sg_cur_index;
a_target_phys_addr sg_cur_byte;
target_phys_addr_t sg_cur_byte;
QEMUIOVector iov;
QEMUBH *bh;
} DMAAIOCB;
@ -82,7 +82,7 @@ static void dma_bdrv_unmap(DMAAIOCB *dbs)
static void dma_bdrv_cb(void *opaque, int ret)
{
DMAAIOCB *dbs = (DMAAIOCB *)opaque;
a_target_phys_addr cur_addr, cur_len;
target_phys_addr_t cur_addr, cur_len;
void *mem;
dbs->acb = NULL;

10
dma.h
View File

@ -16,20 +16,20 @@
#include "block.h"
typedef struct {
a_target_phys_addr base;
a_target_phys_addr len;
target_phys_addr_t base;
target_phys_addr_t len;
} ScatterGatherEntry;
typedef struct {
ScatterGatherEntry *sg;
int nsg;
int nalloc;
a_target_phys_addr size;
target_phys_addr_t size;
} QEMUSGList;
void qemu_sglist_init(QEMUSGList *qsg, int alloc_hint);
void qemu_sglist_add(QEMUSGList *qsg, a_target_phys_addr base,
a_target_phys_addr len);
void qemu_sglist_add(QEMUSGList *qsg, target_phys_addr_t base,
target_phys_addr_t len);
void qemu_sglist_destroy(QEMUSGList *qsg);
BlockDriverAIOCB *dma_bdrv_read(BlockDriverState *bs,

2
dyngen-exec.h
View File

@ -37,7 +37,7 @@
#endif
/* XXX: This may be wrong for 64-bit ILP32 hosts. */
typedef void * a_host_reg;
typedef void * host_reg_t;
#ifdef CONFIG_BSD
typedef struct __sFILE FILE;

8
exec-all.h
View File

@ -81,16 +81,16 @@ TranslationBlock *tb_gen_code(CPUState *env,
void cpu_exec_init(CPUState *env);
void QEMU_NORETURN cpu_loop_exit(void);
int page_unprotect(target_ulong address, unsigned long pc, void *puc);
void tb_invalidate_phys_page_range(a_target_phys_addr start, a_target_phys_addr end,
void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
int is_cpu_write_access);
void tb_invalidate_page_range(target_ulong start, target_ulong end);
void tlb_flush_page(CPUState *env, target_ulong addr);
void tlb_flush(CPUState *env, int flush_global);
int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
a_target_phys_addr paddr, int prot,
target_phys_addr_t paddr, int prot,
int mmu_idx, int is_softmmu);
static inline int tlb_set_page(CPUState *env1, target_ulong vaddr,
a_target_phys_addr paddr, int prot,
target_phys_addr_t paddr, int prot,
int mmu_idx, int is_softmmu)
{
if (prot & PAGE_READ)
@ -269,7 +269,7 @@ extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
#include "qemu-lock.h"
extern a_spinlock tb_lock;
extern spinlock_t tb_lock;
extern int tb_invalidated_flag;

218
exec.c
View File

@ -83,7 +83,7 @@ int code_gen_max_blocks;
TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
static int nb_tbs;
/* any access to the tbs or the page table must use this lock */
a_spinlock tb_lock = SPIN_LOCK_UNLOCKED;
spinlock_t tb_lock = SPIN_LOCK_UNLOCKED;
#if defined(__arm__) || defined(__sparc_v9__)
/* The prologue must be reachable with a direct jump. ARM and Sparc64
@ -115,8 +115,8 @@ static int in_migration;
typedef struct RAMBlock {
uint8_t *host;
a_ram_addr offset;
a_ram_addr length;
ram_addr_t offset;
ram_addr_t length;
struct RAMBlock *next;
} RAMBlock;
@ -124,7 +124,7 @@ static RAMBlock *ram_blocks;
/* TODO: When we implement (and use) ram deallocation (e.g. for hotplug)
then we can no longer assume contiguous ram offsets, and external uses
of this variable will break. */
a_ram_addr last_ram_offset;
ram_addr_t last_ram_offset;
#endif
CPUState *first_cpu;
@ -153,8 +153,8 @@ typedef struct PageDesc {
typedef struct PhysPageDesc {
/* offset in host memory of the page + io_index in the low bits */
a_ram_addr phys_offset;
a_ram_addr region_offset;
ram_addr_t phys_offset;
ram_addr_t region_offset;
} PhysPageDesc;
#define L2_BITS 10
@ -203,13 +203,13 @@ static int tb_flush_count;
static int tb_phys_invalidate_count;
#define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
typedef struct subpage {
a_target_phys_addr base;
typedef struct subpage_t {
target_phys_addr_t base;
CPUReadMemoryFunc * const *mem_read[TARGET_PAGE_SIZE][4];
CPUWriteMemoryFunc * const *mem_write[TARGET_PAGE_SIZE][4];
void *opaque[TARGET_PAGE_SIZE][2][4];
a_ram_addr region_offset[TARGET_PAGE_SIZE][2][4];
} a_subpage;
ram_addr_t region_offset[TARGET_PAGE_SIZE][2][4];
} subpage_t;
#ifdef _WIN32
static void map_exec(void *addr, long size)
@ -346,7 +346,7 @@ static inline PageDesc *page_find(target_ulong index)
return p + (index & (L2_SIZE - 1));
}
static PhysPageDesc *phys_page_find_alloc(a_target_phys_addr index, int alloc)
static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc)
{
void **lp, **p;
PhysPageDesc *pd;
@ -385,14 +385,14 @@ static PhysPageDesc *phys_page_find_alloc(a_target_phys_addr index, int alloc)
return ((PhysPageDesc *)pd) + (index & (L2_SIZE - 1));
}
static inline PhysPageDesc *phys_page_find(a_target_phys_addr index)
static inline PhysPageDesc *phys_page_find(target_phys_addr_t index)
{
return phys_page_find_alloc(index, 0);
}
#if !defined(CONFIG_USER_ONLY)
static void tlb_protect_code(a_ram_addr ram_addr);
static void tlb_unprotect_code_phys(CPUState *env, a_ram_addr ram_addr,
static void tlb_protect_code(ram_addr_t ram_addr);
static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
target_ulong vaddr);
#define mmap_lock() do { } while(0)
#define mmap_unlock() do { } while(0)
@ -766,7 +766,7 @@ void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr)
CPUState *env;
PageDesc *p;
unsigned int h, n1;
a_target_phys_addr phys_pc;
target_phys_addr_t phys_pc;
TranslationBlock *tb1, *tb2;
/* remove the TB from the hash list */
@ -914,7 +914,7 @@ TranslationBlock *tb_gen_code(CPUState *env,
the same physical page. 'is_cpu_write_access' should be true if called
from a real cpu write access: the virtual CPU will exit the current
TB if code is modified inside this TB. */
void tb_invalidate_phys_page_range(a_target_phys_addr start, a_target_phys_addr end,
void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
int is_cpu_write_access)
{
TranslationBlock *tb, *tb_next, *saved_tb;
@ -1021,7 +1021,7 @@ void tb_invalidate_phys_page_range(a_target_phys_addr start, a_target_phys_addr
}
/* len must be <= 8 and start must be a multiple of len */
static inline void tb_invalidate_phys_page_fast(a_target_phys_addr start, int len)
static inline void tb_invalidate_phys_page_fast(target_phys_addr_t start, int len)
{
PageDesc *p;
int offset, b;
@ -1048,7 +1048,7 @@ static inline void tb_invalidate_phys_page_fast(a_target_phys_addr start, int le
}
#if !defined(CONFIG_SOFTMMU)
static void tb_invalidate_phys_page(a_target_phys_addr addr,
static void tb_invalidate_phys_page(target_phys_addr_t addr,
unsigned long pc, void *puc)
{
TranslationBlock *tb;
@ -1310,9 +1310,9 @@ static void tb_reset_jump_recursive(TranslationBlock *tb)
#if defined(TARGET_HAS_ICE)
static void breakpoint_invalidate(CPUState *env, target_ulong pc)
{
a_target_phys_addr addr;
target_phys_addr_t addr;
target_ulong pd;
a_ram_addr ram_addr;
ram_addr_t ram_addr;
PhysPageDesc *p;
addr = cpu_get_phys_page_debug(env, pc);
@ -1533,7 +1533,7 @@ static void cpu_unlink_tb(CPUState *env)
signals are used primarily to interrupt blocking syscalls. */
#else
TranslationBlock *tb;
static a_spinlock interrupt_lock = SPIN_LOCK_UNLOCKED;
static spinlock_t interrupt_lock = SPIN_LOCK_UNLOCKED;
tb = env->current_tb;
/* if the cpu is currently executing code, we must unlink it and
@ -1810,7 +1810,7 @@ void tlb_flush_page(CPUState *env, target_ulong addr)
/* update the TLBs so that writes to code in the virtual page 'addr'
can be detected */
static void tlb_protect_code(a_ram_addr ram_addr)
static void tlb_protect_code(ram_addr_t ram_addr)
{
cpu_physical_memory_reset_dirty(ram_addr,
ram_addr + TARGET_PAGE_SIZE,
@ -1819,7 +1819,7 @@ static void tlb_protect_code(a_ram_addr ram_addr)
/* update the TLB so that writes in physical page 'phys_addr' are no longer
tested for self modifying code */
static void tlb_unprotect_code_phys(CPUState *env, a_ram_addr ram_addr,
static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
target_ulong vaddr)
{
phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] |= CODE_DIRTY_FLAG;
@ -1838,7 +1838,7 @@ static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry,
}
/* Note: start and end must be within the same ram block. */
void cpu_physical_memory_reset_dirty(a_ram_addr start, a_ram_addr end,
void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
int dirty_flags)
{
CPUState *env;
@ -1892,8 +1892,8 @@ int cpu_physical_memory_get_dirty_tracking(void)
return in_migration;
}
int cpu_physical_sync_dirty_bitmap(a_target_phys_addr start_addr,
a_target_phys_addr end_addr)
int cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr,
target_phys_addr_t end_addr)
{
int ret = 0;
@ -1904,7 +1904,7 @@ int cpu_physical_sync_dirty_bitmap(a_target_phys_addr start_addr,
static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry)
{
a_ram_addr ram_addr;
ram_addr_t ram_addr;
void *p;
if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) {
@ -1952,7 +1952,7 @@ static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr)
(can only happen in non SOFTMMU mode for I/O pages or pages
conflicting with the host address space). */
int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
a_target_phys_addr paddr, int prot,
target_phys_addr_t paddr, int prot,
int mmu_idx, int is_softmmu)
{
PhysPageDesc *p;
@ -1960,11 +1960,11 @@ int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
unsigned int index;
target_ulong address;
target_ulong code_address;
a_target_phys_addr addend;
target_phys_addr_t addend;
int ret;
CPUTLBEntry *te;
CPUWatchpoint *wp;
a_target_phys_addr iotlb;
target_phys_addr_t iotlb;
p = phys_page_find(paddr >> TARGET_PAGE_BITS);
if (!p) {
@ -2061,7 +2061,7 @@ void tlb_flush_page(CPUState *env, target_ulong addr)
}
int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
a_target_phys_addr paddr, int prot,
target_phys_addr_t paddr, int prot,
int mmu_idx, int is_softmmu)
{
return 0;
@ -2267,10 +2267,10 @@ static inline void tlb_set_dirty(CPUState *env,
#if !defined(CONFIG_USER_ONLY)
static int subpage_register (a_subpage *mmio, uint32_t start, uint32_t end,
a_ram_addr memory, a_ram_addr region_offset);
static void *subpage_init (a_target_phys_addr base, a_ram_addr *phys,
a_ram_addr orig_memory, a_ram_addr region_offset);
static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
ram_addr_t memory, ram_addr_t region_offset);
static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
ram_addr_t orig_memory, ram_addr_t region_offset);
#define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \
need_subpage) \
do { \
@ -2298,15 +2298,15 @@ static void *subpage_init (a_target_phys_addr base, a_ram_addr *phys,
start_addr and region_offset are rounded down to a page boundary
before calculating this offset. This should not be a problem unless
the low bits of start_addr and region_offset differ. */
void cpu_register_physical_memory_offset(a_target_phys_addr start_addr,
a_ram_addr size,
a_ram_addr phys_offset,
a_ram_addr region_offset)
void cpu_register_physical_memory_offset(target_phys_addr_t start_addr,
ram_addr_t size,
ram_addr_t phys_offset,
ram_addr_t region_offset)
{
a_target_phys_addr addr, end_addr;
target_phys_addr_t addr, end_addr;
PhysPageDesc *p;
CPUState *env;
a_ram_addr orig_size = size;
ram_addr_t orig_size = size;
void *subpage;
if (kvm_enabled())
@ -2317,12 +2317,12 @@ void cpu_register_physical_memory_offset(a_target_phys_addr start_addr,
}
region_offset &= TARGET_PAGE_MASK;
size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
end_addr = start_addr + (a_target_phys_addr)size;
end_addr = start_addr + (target_phys_addr_t)size;
for(addr = start_addr; addr != end_addr; addr += TARGET_PAGE_SIZE) {
p = phys_page_find(addr >> TARGET_PAGE_BITS);
if (p && p->phys_offset != IO_MEM_UNASSIGNED) {
a_ram_addr orig_memory = p->phys_offset;
a_target_phys_addr start_addr2, end_addr2;
ram_addr_t orig_memory = p->phys_offset;
target_phys_addr_t start_addr2, end_addr2;
int need_subpage = 0;
CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2,
@ -2353,7 +2353,7 @@ void cpu_register_physical_memory_offset(a_target_phys_addr start_addr,
(phys_offset & IO_MEM_ROMD)) {
phys_offset += TARGET_PAGE_SIZE;
} else {
a_target_phys_addr start_addr2, end_addr2;
target_phys_addr_t start_addr2, end_addr2;
int need_subpage = 0;
CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr,
@ -2381,7 +2381,7 @@ void cpu_register_physical_memory_offset(a_target_phys_addr start_addr,
}
/* XXX: temporary until new memory mapping API */
a_ram_addr cpu_get_physical_page_desc(a_target_phys_addr addr)
ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr)
{
PhysPageDesc *p;
@ -2391,19 +2391,19 @@ a_ram_addr cpu_get_physical_page_desc(a_target_phys_addr addr)
return p->phys_offset;
}
void qemu_register_coalesced_mmio(a_target_phys_addr addr, a_ram_addr size)
void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size)
{
if (kvm_enabled())
kvm_coalesce_mmio_region(addr, size);
}
void qemu_unregister_coalesced_mmio(a_target_phys_addr addr, a_ram_addr size)
void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size)
{
if (kvm_enabled())
kvm_uncoalesce_mmio_region(addr, size);
}
a_ram_addr qemu_ram_alloc(a_ram_addr size)
ram_addr_t qemu_ram_alloc(ram_addr_t size)
{
RAMBlock *new_block;
@ -2430,7 +2430,7 @@ a_ram_addr qemu_ram_alloc(a_ram_addr size)
return new_block->offset;
}
void qemu_ram_free(a_ram_addr addr)
void qemu_ram_free(ram_addr_t addr)
{
/* TODO: implement this. */
}
@ -2443,7 +2443,7 @@ void qemu_ram_free(a_ram_addr addr)
It should not be used for general purpose DMA.
Use cpu_physical_memory_map/cpu_physical_memory_rw instead.
*/
void *qemu_get_ram_ptr(a_ram_addr addr)
void *qemu_get_ram_ptr(ram_addr_t addr)
{
RAMBlock *prev;
RAMBlock **prevp;
@ -2474,7 +2474,7 @@ void *qemu_get_ram_ptr(a_ram_addr addr)
/* Some of the softmmu routines need to translate from a host pointer
(typically a TLB entry) back to a ram offset. */
a_ram_addr qemu_ram_addr_from_host(void *ptr)
ram_addr_t qemu_ram_addr_from_host(void *ptr)
{
RAMBlock *prev;
RAMBlock **prevp;
@ -2498,7 +2498,7 @@ a_ram_addr qemu_ram_addr_from_host(void *ptr)
return block->offset + (host - block->host);
}
static uint32_t unassigned_mem_readb(void *opaque, a_target_phys_addr addr)
static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr)
{
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
@ -2509,7 +2509,7 @@ static uint32_t unassigned_mem_readb(void *opaque, a_target_phys_addr addr)
return 0;
}
static uint32_t unassigned_mem_readw(void *opaque, a_target_phys_addr addr)
static uint32_t unassigned_mem_readw(void *opaque, target_phys_addr_t addr)
{
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
@ -2520,7 +2520,7 @@ static uint32_t unassigned_mem_readw(void *opaque, a_target_phys_addr addr)
return 0;
}
static uint32_t unassigned_mem_readl(void *opaque, a_target_phys_addr addr)
static uint32_t unassigned_mem_readl(void *opaque, target_phys_addr_t addr)
{
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
@ -2531,7 +2531,7 @@ static uint32_t unassigned_mem_readl(void *opaque, a_target_phys_addr addr)
return 0;
}
static void unassigned_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
@ -2541,7 +2541,7 @@ static void unassigned_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_
#endif
}
static void unassigned_mem_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
static void unassigned_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
@ -2551,7 +2551,7 @@ static void unassigned_mem_writew(void *opaque, a_target_phys_addr addr, uint32_
#endif
}
static void unassigned_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
static void unassigned_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
@ -2573,7 +2573,7 @@ static CPUWriteMemoryFunc * const unassigned_mem_write[3] = {
unassigned_mem_writel,
};
static void notdirty_mem_writeb(void *opaque, a_target_phys_addr ram_addr,
static void notdirty_mem_writeb(void *opaque, target_phys_addr_t ram_addr,
uint32_t val)
{
int dirty_flags;
@ -2593,7 +2593,7 @@ static void notdirty_mem_writeb(void *opaque, a_target_phys_addr ram_addr,
tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
}
static void notdirty_mem_writew(void *opaque, a_target_phys_addr ram_addr,
static void notdirty_mem_writew(void *opaque, target_phys_addr_t ram_addr,
uint32_t val)
{
int dirty_flags;
@ -2613,7 +2613,7 @@ static void notdirty_mem_writew(void *opaque, a_target_phys_addr ram_addr,
tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
}
static void notdirty_mem_writel(void *opaque, a_target_phys_addr ram_addr,
static void notdirty_mem_writel(void *opaque, target_phys_addr_t ram_addr,
uint32_t val)
{
int dirty_flags;
@ -2693,39 +2693,39 @@ static void check_watchpoint(int offset, int len_mask, int flags)
/* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
so these check for a hit then pass through to the normal out-of-line
phys routines. */
static uint32_t watch_mem_readb(void *opaque, a_target_phys_addr addr)
static uint32_t watch_mem_readb(void *opaque, target_phys_addr_t addr)
{
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_READ);
return ldub_phys(addr);
}
static uint32_t watch_mem_readw(void *opaque, a_target_phys_addr addr)
static uint32_t watch_mem_readw(void *opaque, target_phys_addr_t addr)
{
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_READ);
return lduw_phys(addr);
}
static uint32_t watch_mem_readl(void *opaque, a_target_phys_addr addr)
static uint32_t watch_mem_readl(void *opaque, target_phys_addr_t addr)
{
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_READ);
return ldl_phys(addr);
}
static void watch_mem_writeb(void *opaque, a_target_phys_addr addr,
static void watch_mem_writeb(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_WRITE);
stb_phys(addr, val);
}
static void watch_mem_writew(void *opaque, a_target_phys_addr addr,
static void watch_mem_writew(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_WRITE);
stw_phys(addr, val);
}
static void watch_mem_writel(void *opaque, a_target_phys_addr addr,
static void watch_mem_writel(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_WRITE);
@ -2744,7 +2744,7 @@ static CPUWriteMemoryFunc * const watch_mem_write[3] = {
watch_mem_writel,
};
static inline uint32_t subpage_readlen (a_subpage *mmio, a_target_phys_addr addr,
static inline uint32_t subpage_readlen (subpage_t *mmio, target_phys_addr_t addr,
unsigned int len)
{
uint32_t ret;
@ -2761,7 +2761,7 @@ static inline uint32_t subpage_readlen (a_subpage *mmio, a_target_phys_addr addr
return ret;
}
static inline void subpage_writelen (a_subpage *mmio, a_target_phys_addr addr,
static inline void subpage_writelen (subpage_t *mmio, target_phys_addr_t addr,
uint32_t value, unsigned int len)
{
unsigned int idx;
@ -2776,7 +2776,7 @@ static inline void subpage_writelen (a_subpage *mmio, a_target_phys_addr addr,
value);
}
static uint32_t subpage_readb (void *opaque, a_target_phys_addr addr)
static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr)
{
#if defined(DEBUG_SUBPAGE)
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
@ -2785,7 +2785,7 @@ static uint32_t subpage_readb (void *opaque, a_target_phys_addr addr)
return subpage_readlen(opaque, addr, 0);
}
static void subpage_writeb (void *opaque, a_target_phys_addr addr,
static void subpage_writeb (void *opaque, target_phys_addr_t addr,
uint32_t value)
{
#if defined(DEBUG_SUBPAGE)
@ -2794,7 +2794,7 @@ static void subpage_writeb (void *opaque, a_target_phys_addr addr,
subpage_writelen(opaque, addr, value, 0);
}
static uint32_t subpage_readw (void *opaque, a_target_phys_addr addr)
static uint32_t subpage_readw (void *opaque, target_phys_addr_t addr)
{
#if defined(DEBUG_SUBPAGE)
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
@ -2803,7 +2803,7 @@ static uint32_t subpage_readw (void *opaque, a_target_phys_addr addr)
return subpage_readlen(opaque, addr, 1);
}
static void subpage_writew (void *opaque, a_target_phys_addr addr,
static void subpage_writew (void *opaque, target_phys_addr_t addr,
uint32_t value)
{
#if defined(DEBUG_SUBPAGE)
@ -2812,7 +2812,7 @@ static void subpage_writew (void *opaque, a_target_phys_addr addr,
subpage_writelen(opaque, addr, value, 1);
}
static uint32_t subpage_readl (void *opaque, a_target_phys_addr addr)
static uint32_t subpage_readl (void *opaque, target_phys_addr_t addr)
{
#if defined(DEBUG_SUBPAGE)
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
@ -2822,7 +2822,7 @@ static uint32_t subpage_readl (void *opaque, a_target_phys_addr addr)
}
static void subpage_writel (void *opaque,
a_target_phys_addr addr, uint32_t value)
target_phys_addr_t addr, uint32_t value)
{
#if defined(DEBUG_SUBPAGE)
printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
@ -2842,8 +2842,8 @@ static CPUWriteMemoryFunc * const subpage_write[] = {
&subpage_writel,
};
static int subpage_register (a_subpage *mmio, uint32_t start, uint32_t end,
a_ram_addr memory, a_ram_addr region_offset)
static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
ram_addr_t memory, ram_addr_t region_offset)
{
int idx, eidx;
unsigned int i;
@ -2875,13 +2875,13 @@ static int subpage_register (a_subpage *mmio, uint32_t start, uint32_t end,
return 0;
}
static void *subpage_init (a_target_phys_addr base, a_ram_addr *phys,
a_ram_addr orig_memory, a_ram_addr region_offset)
static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
ram_addr_t orig_memory, ram_addr_t region_offset)
{
a_subpage *mmio;
subpage_t *mmio;
int subpage_memory;
mmio = qemu_mallocz(sizeof(a_subpage));
mmio = qemu_mallocz(sizeof(subpage_t));
mmio->base = base;
subpage_memory = cpu_register_io_memory(subpage_read, subpage_write, mmio);
@ -2981,7 +2981,7 @@ static void io_mem_init(void)
/* physical memory access (slow version, mainly for debug) */
#if defined(CONFIG_USER_ONLY)
void cpu_physical_memory_rw(a_target_phys_addr addr, uint8_t *buf,
void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
int len, int is_write)
{
int l, flags;
@ -3022,13 +3022,13 @@ void cpu_physical_memory_rw(a_target_phys_addr addr, uint8_t *buf,
}
#else
void cpu_physical_memory_rw(a_target_phys_addr addr, uint8_t *buf,
void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
int len, int is_write)
{
int l, io_index;
uint8_t *ptr;
uint32_t val;
a_target_phys_addr page;
target_phys_addr_t page;
unsigned long pd;
PhysPageDesc *p;
@ -3046,7 +3046,7 @@ void cpu_physical_memory_rw(a_target_phys_addr addr, uint8_t *buf,
if (is_write) {
if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
a_target_phys_addr addr1 = addr;
target_phys_addr_t addr1 = addr;
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
if (p)
addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
@ -3085,7 +3085,7 @@ void cpu_physical_memory_rw(a_target_phys_addr addr, uint8_t *buf,
} else {
if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
!(pd & IO_MEM_ROMD)) {
a_target_phys_addr addr1 = addr;
target_phys_addr_t addr1 = addr;
/* I/O case */
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
if (p)
@ -3120,12 +3120,12 @@ void cpu_physical_memory_rw(a_target_phys_addr addr, uint8_t *buf,
}
/* used for ROM loading : can write in RAM and ROM */
void cpu_physical_memory_write_rom(a_target_phys_addr addr,
void cpu_physical_memory_write_rom(target_phys_addr_t addr,
const uint8_t *buf, int len)
{
int l;
uint8_t *ptr;
a_target_phys_addr page;
target_phys_addr_t page;
unsigned long pd;
PhysPageDesc *p;
@ -3160,8 +3160,8 @@ void cpu_physical_memory_write_rom(a_target_phys_addr addr,
typedef struct {
void *buffer;
a_target_phys_addr addr;
a_target_phys_addr len;
target_phys_addr_t addr;
target_phys_addr_t len;
} BounceBuffer;
static BounceBuffer bounce;
@ -3211,16 +3211,16 @@ static void cpu_notify_map_clients(void)
* Use cpu_register_map_client() to know when retrying the map operation is
* likely to succeed.
*/
void *cpu_physical_memory_map(a_target_phys_addr addr,
a_target_phys_addr *plen,
void *cpu_physical_memory_map(target_phys_addr_t addr,
target_phys_addr_t *plen,
int is_write)
{
a_target_phys_addr len = *plen;
a_target_phys_addr done = 0;
target_phys_addr_t len = *plen;
target_phys_addr_t done = 0;
int l;
uint8_t *ret = NULL;
uint8_t *ptr;
a_target_phys_addr page;
target_phys_addr_t page;
unsigned long pd;
PhysPageDesc *p;
unsigned long addr1;
@ -3270,12 +3270,12 @@ void *cpu_physical_memory_map(a_target_phys_addr addr,
* Will also mark the memory as dirty if is_write == 1. access_len gives
* the amount of memory that was actually read or written by the caller.
*/
void cpu_physical_memory_unmap(void *buffer, a_target_phys_addr len,
int is_write, a_target_phys_addr access_len)
void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
int is_write, target_phys_addr_t access_len)
{
if (buffer != bounce.buffer) {
if (is_write) {
a_ram_addr addr1 = qemu_ram_addr_from_host(buffer);
ram_addr_t addr1 = qemu_ram_addr_from_host(buffer);
while (access_len) {
unsigned l;
l = TARGET_PAGE_SIZE;
@ -3303,7 +3303,7 @@ void cpu_physical_memory_unmap(void *buffer, a_target_phys_addr len,
}
/* warning: addr must be aligned */
uint32_t ldl_phys(a_target_phys_addr addr)
uint32_t ldl_phys(target_phys_addr_t addr)
{
int io_index;
uint8_t *ptr;
@ -3335,7 +3335,7 @@ uint32_t ldl_phys(a_target_phys_addr addr)
}
/* warning: addr must be aligned */
uint64_t ldq_phys(a_target_phys_addr addr)
uint64_t ldq_phys(target_phys_addr_t addr)
{
int io_index;
uint8_t *ptr;
@ -3373,7 +3373,7 @@ uint64_t ldq_phys(a_target_phys_addr addr)
}
/* XXX: optimize */
uint32_t ldub_phys(a_target_phys_addr addr)
uint32_t ldub_phys(target_phys_addr_t addr)
{
uint8_t val;
cpu_physical_memory_read(addr, &val, 1);
@ -3381,7 +3381,7 @@ uint32_t ldub_phys(a_target_phys_addr addr)
}
/* XXX: optimize */
uint32_t lduw_phys(a_target_phys_addr addr)
uint32_t lduw_phys(target_phys_addr_t addr)
{
uint16_t val;
cpu_physical_memory_read(addr, (uint8_t *)&val, 2);
@ -3391,7 +3391,7 @@ uint32_t lduw_phys(a_target_phys_addr addr)
/* warning: addr must be aligned. The ram page is not masked as dirty
and the code inside is not invalidated. It is useful if the dirty
bits are used to track modified PTEs */
void stl_phys_notdirty(a_target_phys_addr addr, uint32_t val)
void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val)
{
int io_index;
uint8_t *ptr;
@ -3427,7 +3427,7 @@ void stl_phys_notdirty(a_target_phys_addr addr, uint32_t val)
}
}
void stq_phys_notdirty(a_target_phys_addr addr, uint64_t val)
void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val)
{
int io_index;
uint8_t *ptr;
@ -3460,7 +3460,7 @@ void stq_phys_notdirty(a_target_phys_addr addr, uint64_t val)
}
/* warning: addr must be aligned */
void stl_phys(a_target_phys_addr addr, uint32_t val)
void stl_phys(target_phys_addr_t addr, uint32_t val)
{
int io_index;
uint8_t *ptr;
@ -3496,21 +3496,21 @@ void stl_phys(a_target_phys_addr addr, uint32_t val)
}
/* XXX: optimize */
void stb_phys(a_target_phys_addr addr, uint32_t val)
void stb_phys(target_phys_addr_t addr, uint32_t val)
{
uint8_t v = val;
cpu_physical_memory_write(addr, &v, 1);
}
/* XXX: optimize */
void stw_phys(a_target_phys_addr addr, uint32_t val)
void stw_phys(target_phys_addr_t addr, uint32_t val)
{
uint16_t v = tswap16(val);
cpu_physical_memory_write(addr, (const uint8_t *)&v, 2);
}
/* XXX: optimize */
void stq_phys(a_target_phys_addr addr, uint64_t val)
void stq_phys(target_phys_addr_t addr, uint64_t val)
{
val = tswap64(val);
cpu_physical_memory_write(addr, (const uint8_t *)&val, 8);
@ -3523,7 +3523,7 @@ int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
uint8_t *buf, int len, int is_write)
{
int l;
a_target_phys_addr phys_addr;
target_phys_addr_t phys_addr;
target_ulong page;
while (len > 0) {

4
hostregs_helper.h
View File

@ -27,8 +27,8 @@
#if defined(DECLARE_HOST_REGS)
#define DO_REG(REG) \
register a_host_reg reg_AREG##REG asm(AREG##REG); \
volatile a_host_reg saved_AREG##REG;
register host_reg_t reg_AREG##REG asm(AREG##REG); \
volatile host_reg_t saved_AREG##REG;
#elif defined(SAVE_HOST_REGS)

4
hw/an5206.c
View File

@ -29,7 +29,7 @@ void irq_info(Monitor *mon)
/* Board init. */
static void an5206_init(a_ram_addr ram_size,
static void an5206_init(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@ -37,7 +37,7 @@ static void an5206_init(a_ram_addr ram_size,
CPUState *env;
int kernel_size;
uint64_t elf_entry;
a_target_phys_addr entry;
target_phys_addr_t entry;
if (!cpu_model)
cpu_model = "m5206";

26
hw/apb_pci.c
View File

@ -39,7 +39,7 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
#define APB_DPRINTF(fmt, ...)
#endif
typedef a_target_phys_addr a_pci_addr;
typedef target_phys_addr_t pci_addr_t;
#include "pci_host.h"
typedef struct APBState {
@ -47,7 +47,7 @@ typedef struct APBState {
PCIHostState host_state;
} APBState;
static void pci_apb_config_writel (void *opaque, a_target_phys_addr addr,
static void pci_apb_config_writel (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
APBState *s = opaque;
@ -61,7 +61,7 @@ static void pci_apb_config_writel (void *opaque, a_target_phys_addr addr,
}
static uint32_t pci_apb_config_readl (void *opaque,
a_target_phys_addr addr)
target_phys_addr_t addr)
{
APBState *s = opaque;
uint32_t val;
@ -87,7 +87,7 @@ static CPUReadMemoryFunc * const pci_apb_config_read[] = {
&pci_apb_config_readl,
};
static void apb_config_writel (void *opaque, a_target_phys_addr addr,
static void apb_config_writel (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
//PCIBus *s = opaque;
@ -105,7 +105,7 @@ static void apb_config_writel (void *opaque, a_target_phys_addr addr,
}
static uint32_t apb_config_readl (void *opaque,
a_target_phys_addr addr)
target_phys_addr_t addr)
{
//PCIBus *s = opaque;
uint32_t val;
@ -148,25 +148,25 @@ static CPUReadMemoryFunc * const pci_apb_read[] = {
&pci_host_data_readl,
};
static void pci_apb_iowriteb (void *opaque, a_target_phys_addr addr,
static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
cpu_outb(addr & IOPORTS_MASK, val);
}
static void pci_apb_iowritew (void *opaque, a_target_phys_addr addr,
static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
cpu_outw(addr & IOPORTS_MASK, val);
}
static void pci_apb_iowritel (void *opaque, a_target_phys_addr addr,
static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
cpu_outl(addr & IOPORTS_MASK, val);
}
static uint32_t pci_apb_ioreadb (void *opaque, a_target_phys_addr addr)
static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
{
uint32_t val;
@ -174,7 +174,7 @@ static uint32_t pci_apb_ioreadb (void *opaque, a_target_phys_addr addr)
return val;
}
static uint32_t pci_apb_ioreadw (void *opaque, a_target_phys_addr addr)
static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
{
uint32_t val;
@ -182,7 +182,7 @@ static uint32_t pci_apb_ioreadw (void *opaque, a_target_phys_addr addr)
return val;
}
static uint32_t pci_apb_ioreadl (void *opaque, a_target_phys_addr addr)
static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
{
uint32_t val;
@ -226,8 +226,8 @@ static void pci_apb_set_irq(void *opaque, int irq_num, int level)
qemu_set_irq(pic[irq_num], level);
}
PCIBus *pci_apb_init(a_target_phys_addr special_base,
a_target_phys_addr mem_base,
PCIBus *pci_apb_init(target_phys_addr_t special_base,
target_phys_addr_t mem_base,
qemu_irq *pic, PCIBus **bus2, PCIBus **bus3)
{
DeviceState *dev;

14
hw/apic.c
View File

@ -661,25 +661,25 @@ static void apic_timer(void *opaque)
apic_timer_update(s, s->next_time);
}
static uint32_t apic_mem_readb(void *opaque, a_target_phys_addr addr)
static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
{
return 0;
}
static uint32_t apic_mem_readw(void *opaque, a_target_phys_addr addr)
static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
{
return 0;
}
static void apic_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
}
static void apic_mem_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
}
static uint32_t apic_mem_readl(void *opaque, a_target_phys_addr addr)
static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
{
CPUState *env;
APICState *s;
@ -760,7 +760,7 @@ static uint32_t apic_mem_readl(void *opaque, a_target_phys_addr addr)
return val;
}
static void apic_send_msi(a_target_phys_addr addr, uint32 data)
static void apic_send_msi(target_phys_addr_t addr, uint32 data)
{
uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
@ -771,7 +771,7 @@ static void apic_send_msi(a_target_phys_addr addr, uint32 data)
apic_deliver_irq(dest, dest_mode, delivery, vector, 0, trigger_mode);
}
static void apic_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
CPUState *env;
APICState *s;

4
hw/arm-misc.h
View File

@ -26,8 +26,8 @@ struct arm_boot_info {
const char *kernel_filename;
const char *kernel_cmdline;
const char *initrd_filename;
a_target_phys_addr loader_start;
a_target_phys_addr smp_loader_start;
target_phys_addr_t loader_start;
target_phys_addr_t smp_loader_start;
int nb_cpus;
int board_id;
int (*atag_board)(struct arm_boot_info *info, void *p);

10
hw/arm_boot.c
View File

@ -61,9 +61,9 @@ static void main_cpu_reset(void *opaque)
} while (0)
static void set_kernel_args(struct arm_boot_info *info,
int initrd_size, a_target_phys_addr base)
int initrd_size, target_phys_addr_t base)
{
a_target_phys_addr p;
target_phys_addr_t p;
p = base + KERNEL_ARGS_ADDR;
/* ATAG_CORE */
@ -114,9 +114,9 @@ static void set_kernel_args(struct arm_boot_info *info,
}
static void set_kernel_args_old(struct arm_boot_info *info,
int initrd_size, a_target_phys_addr base)
int initrd_size, target_phys_addr_t base)
{
a_target_phys_addr p;
target_phys_addr_t p;
const char *s;
@ -193,7 +193,7 @@ void arm_load_kernel(CPUState *env, struct arm_boot_info *info)
int n;
int is_linux = 0;
uint64_t elf_entry;
a_target_phys_addr entry;
target_phys_addr_t entry;
int big_endian;
/* Load the kernel. */

12
hw/arm_gic.c
View File

@ -238,7 +238,7 @@ static void gic_complete_irq(gic_state * s, int cpu, int irq)
}
}
static uint32_t gic_dist_readb(void *opaque, a_target_phys_addr offset)
static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
{
gic_state *s = (gic_state *)opaque;
uint32_t res;
@ -348,7 +348,7 @@ bad_reg:
return 0;
}
static uint32_t gic_dist_readw(void *opaque, a_target_phys_addr offset)
static uint32_t gic_dist_readw(void *opaque, target_phys_addr_t offset)
{
uint32_t val;
val = gic_dist_readb(opaque, offset);
@ -356,7 +356,7 @@ static uint32_t gic_dist_readw(void *opaque, a_target_phys_addr offset)
return val;
}
static uint32_t gic_dist_readl(void *opaque, a_target_phys_addr offset)
static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset)
{
uint32_t val;
#ifdef NVIC
@ -371,7 +371,7 @@ static uint32_t gic_dist_readl(void *opaque, a_target_phys_addr offset)
return val;
}
static void gic_dist_writeb(void *opaque, a_target_phys_addr offset,
static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
gic_state *s = (gic_state *)opaque;
@ -509,14 +509,14 @@ bad_reg:
hw_error("gic_dist_writeb: Bad offset %x\n", (int)offset);
}
static void gic_dist_writew(void *opaque, a_target_phys_addr offset,
static void gic_dist_writew(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
gic_dist_writeb(opaque, offset, value & 0xff);
gic_dist_writeb(opaque, offset + 1, value >> 8);
}
static void gic_dist_writel(void *opaque, a_target_phys_addr offset,
static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
gic_state *s = (gic_state *)opaque;

4
hw/arm_sysctl.c
View File

@ -27,7 +27,7 @@ typedef struct {
uint32_t resetlevel;
} arm_sysctl_state;
static uint32_t arm_sysctl_read(void *opaque, a_target_phys_addr offset)
static uint32_t arm_sysctl_read(void *opaque, target_phys_addr_t offset)
{
arm_sysctl_state *s = (arm_sysctl_state *)opaque;
@ -104,7 +104,7 @@ static uint32_t arm_sysctl_read(void *opaque, a_target_phys_addr offset)
}
}
static void arm_sysctl_write(void *opaque, a_target_phys_addr offset,
static void arm_sysctl_write(void *opaque, target_phys_addr_t offset,
uint32_t val)
{
arm_sysctl_state *s = (arm_sysctl_state *)opaque;

12
hw/arm_timer.c
View File

@ -42,7 +42,7 @@ static void arm_timer_update(arm_timer_state *s)
}
}
static uint32_t arm_timer_read(void *opaque, a_target_phys_addr offset)
static uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset)
{
arm_timer_state *s = (arm_timer_state *)opaque;
@ -84,7 +84,7 @@ static void arm_timer_recalibrate(arm_timer_state *s, int reload)
ptimer_set_limit(s->timer, limit, reload);
}
static void arm_timer_write(void *opaque, a_target_phys_addr offset,
static void arm_timer_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
arm_timer_state *s = (arm_timer_state *)opaque;
@ -199,7 +199,7 @@ static void sp804_set_irq(void *opaque, int irq, int level)
qemu_set_irq(s->irq, s->level[0] || s->level[1]);
}
static uint32_t sp804_read(void *opaque, a_target_phys_addr offset)
static uint32_t sp804_read(void *opaque, target_phys_addr_t offset)
{
sp804_state *s = (sp804_state *)opaque;
@ -211,7 +211,7 @@ static uint32_t sp804_read(void *opaque, a_target_phys_addr offset)
}
}
static void sp804_write(void *opaque, a_target_phys_addr offset,
static void sp804_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
sp804_state *s = (sp804_state *)opaque;
@ -283,7 +283,7 @@ typedef struct {
arm_timer_state *timer[3];
} icp_pit_state;
static uint32_t icp_pit_read(void *opaque, a_target_phys_addr offset)
static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset)
{
icp_pit_state *s = (icp_pit_state *)opaque;
int n;
@ -297,7 +297,7 @@ static uint32_t icp_pit_read(void *opaque, a_target_phys_addr offset)
return arm_timer_read(s->timer[n], offset & 0xff);
}
static void icp_pit_write(void *opaque, a_target_phys_addr offset,
static void icp_pit_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
icp_pit_state *s = (icp_pit_state *)opaque;

12
hw/armv7m.c
View File

@ -26,14 +26,14 @@ static inline uint32_t bitband_addr(void * opaque, uint32_t addr)
}
static uint32_t bitband_readb(void *opaque, a_target_phys_addr offset)
static uint32_t bitband_readb(void *opaque, target_phys_addr_t offset)
{
uint8_t v;
cpu_physical_memory_read(bitband_addr(opaque, offset), &v, 1);
return (v & (1 << ((offset >> 2) & 7))) != 0;
}
static void bitband_writeb(void *opaque, a_target_phys_addr offset,
static void bitband_writeb(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
uint32_t addr;
@ -49,7 +49,7 @@ static void bitband_writeb(void *opaque, a_target_phys_addr offset,
cpu_physical_memory_write(addr, &v, 1);
}
static uint32_t bitband_readw(void *opaque, a_target_phys_addr offset)
static uint32_t bitband_readw(void *opaque, target_phys_addr_t offset)
{
uint32_t addr;
uint16_t mask;
@ -61,7 +61,7 @@ static uint32_t bitband_readw(void *opaque, a_target_phys_addr offset)
return (v & mask) != 0;
}
static void bitband_writew(void *opaque, a_target_phys_addr offset,
static void bitband_writew(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
uint32_t addr;
@ -78,7 +78,7 @@ static void bitband_writew(void *opaque, a_target_phys_addr offset,
cpu_physical_memory_write(addr, (uint8_t *)&v, 2);
}
static uint32_t bitband_readl(void *opaque, a_target_phys_addr offset)
static uint32_t bitband_readl(void *opaque, target_phys_addr_t offset)
{
uint32_t addr;
uint32_t mask;
@ -90,7 +90,7 @@ static uint32_t bitband_readl(void *opaque, a_target_phys_addr offset)
return (v & mask) != 0;
}
static void bitband_writel(void *opaque, a_target_phys_addr offset,
static void bitband_writel(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
uint32_t addr;

14
hw/axis_dev88.c
View File

@ -44,7 +44,7 @@ struct nand_state_t
};
static struct nand_state_t nand_state;
static uint32_t nand_readl (void *opaque, a_target_phys_addr addr)
static uint32_t nand_readl (void *opaque, target_phys_addr_t addr)
{
struct nand_state_t *s = opaque;
uint32_t r;
@ -59,7 +59,7 @@ static uint32_t nand_readl (void *opaque, a_target_phys_addr addr)
}
static void
nand_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
nand_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
struct nand_state_t *s = opaque;
int rdy;
@ -168,7 +168,7 @@ static struct gpio_state_t
uint32_t regs[0x5c / 4];
} gpio_state;
static uint32_t gpio_readl (void *opaque, a_target_phys_addr addr)
static uint32_t gpio_readl (void *opaque, target_phys_addr_t addr)
{
struct gpio_state_t *s = opaque;
uint32_t r = 0;
@ -197,7 +197,7 @@ static uint32_t gpio_readl (void *opaque, a_target_phys_addr addr)
D(printf("%s %x=%x\n", __func__, addr, r));
}
static void gpio_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
static void gpio_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
struct gpio_state_t *s = opaque;
D(printf("%s %x=%x\n", __func__, addr, value));
@ -250,7 +250,7 @@ static void main_cpu_reset(void *opaque)
}
static
void axisdev88_init (a_ram_addr ram_size,
void axisdev88_init (ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@ -265,8 +265,8 @@ void axisdev88_init (a_ram_addr ram_size,
int i;
int nand_regs;
int gpio_regs;
a_ram_addr phys_ram;
a_ram_addr phys_intmem;
ram_addr_t phys_ram;
ram_addr_t phys_intmem;
/* init CPUs */
if (cpu_model == NULL) {

2
hw/boards.h
View File

@ -5,7 +5,7 @@
#include "qdev.h"
typedef void QEMUMachineInitFunc(a_ram_addr ram_size,
typedef void QEMUMachineInitFunc(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,

4
hw/bt-hci-csr.c
View File

@ -44,7 +44,7 @@ struct csrhci_s {
QEMUTimer *out_tm;
int64_t baud_delay;
a_bdaddr bd_addr;
bdaddr_t bd_addr;
struct HCIInfo *hci;
};
@ -398,7 +398,7 @@ static void csrhci_reset(struct csrhci_s *s)
/* After a while... (but sooner than 10ms) */
s->modem_state |= CHR_TIOCM_CTS;
memset(&s->bd_addr, 0, sizeof(a_bdaddr));
memset(&s->bd_addr, 0, sizeof(bdaddr_t));
}
static void csrhci_out_tick(void *opaque)

16
hw/bt-hci.c
View File

@ -62,7 +62,7 @@ struct bt_hci_s {
uint32_t role_bmp;
int last_handle;
int connecting;
a_bdaddr awaiting_bdaddr[HCI_HANDLES_MAX];
bdaddr_t awaiting_bdaddr[HCI_HANDLES_MAX];
} lm;
uint8_t event_mask[8];
@ -672,7 +672,7 @@ static void bt_hci_lmp_link_teardown(struct bt_hci_s *hci, uint16_t handle)
}
}
static int bt_hci_connect(struct bt_hci_s *hci, a_bdaddr *bdaddr)
static int bt_hci_connect(struct bt_hci_s *hci, bdaddr_t *bdaddr)
{
struct bt_device_s *slave;
struct bt_link_s link;
@ -706,7 +706,7 @@ static void bt_hci_connection_reject(struct bt_hci_s *hci,
}
static void bt_hci_connection_reject_event(struct bt_hci_s *hci,
a_bdaddr *bdaddr)
bdaddr_t *bdaddr)
{
evt_conn_complete params;
@ -808,7 +808,7 @@ static void bt_hci_conn_accept_timeout(void *opaque)
* that's been cancelled by the host in the meantime and immediately
* try to detach the link and send a Connection Complete. */
static int bt_hci_lmp_connection_ready(struct bt_hci_s *hci,
a_bdaddr *bdaddr)
bdaddr_t *bdaddr)
{
int i;
@ -939,7 +939,7 @@ static void bt_hci_lmp_disconnect_slave(struct bt_link_s *btlink)
&params, EVT_DISCONN_COMPLETE_SIZE);
}
static int bt_hci_name_req(struct bt_hci_s *hci, a_bdaddr *bdaddr)
static int bt_hci_name_req(struct bt_hci_s *hci, bdaddr_t *bdaddr)
{
struct bt_device_s *slave;
evt_remote_name_req_complete params;
@ -1290,7 +1290,7 @@ static inline void bt_hci_event_complete_status(struct bt_hci_s *hci,
}
static inline void bt_hci_event_complete_conn_cancel(struct bt_hci_s *hci,
uint8_t status, a_bdaddr *bd_addr)
uint8_t status, bdaddr_t *bd_addr)
{
create_conn_cancel_rp params = {
.status = status,
@ -1324,7 +1324,7 @@ static inline void bt_hci_event_encrypt_change(struct bt_hci_s *hci,
}
static inline void bt_hci_event_complete_name_cancel(struct bt_hci_s *hci,
a_bdaddr *bd_addr)
bdaddr_t *bd_addr)
{
remote_name_req_cancel_rp params = {
.status = HCI_INVALID_PARAMETERS,
@ -2134,7 +2134,7 @@ static int bt_hci_bdaddr_set(struct HCIInfo *info, const uint8_t *bd_addr)
{
struct bt_hci_s *hci = hci_from_info(info);
bacpy(&hci->device.bd_addr, (const a_bdaddr *) bd_addr);
bacpy(&hci->device.bd_addr, (const bdaddr_t *) bd_addr);
return 0;
}

78
hw/bt.h
View File

@ -26,20 +26,20 @@
/* BD Address */
typedef struct {
uint8_t b[6];
} __attribute__((packed)) a_bdaddr;
} __attribute__((packed)) bdaddr_t;
#define BDADDR_ANY (&(a_bdaddr) {{0, 0, 0, 0, 0, 0}})
#define BDADDR_ALL (&(a_bdaddr) {{0xff, 0xff, 0xff, 0xff, 0xff, 0xff}})
#define BDADDR_LOCAL (&(a_bdaddr) {{0, 0, 0, 0xff, 0xff, 0xff}})
#define BDADDR_ANY (&(bdaddr_t) {{0, 0, 0, 0, 0, 0}})
#define BDADDR_ALL (&(bdaddr_t) {{0xff, 0xff, 0xff, 0xff, 0xff, 0xff}})
#define BDADDR_LOCAL (&(bdaddr_t) {{0, 0, 0, 0xff, 0xff, 0xff}})
/* Copy, swap, convert BD Address */
static inline int bacmp(const a_bdaddr *ba1, const a_bdaddr *ba2)
static inline int bacmp(const bdaddr_t *ba1, const bdaddr_t *ba2)
{
return memcmp(ba1, ba2, sizeof(a_bdaddr));
return memcmp(ba1, ba2, sizeof(bdaddr_t));
}
static inline void bacpy(a_bdaddr *dst, const a_bdaddr *src)
static inline void bacpy(bdaddr_t *dst, const bdaddr_t *src)
{
memcpy(dst, src, sizeof(a_bdaddr));
memcpy(dst, src, sizeof(bdaddr_t));
}
#define BAINIT(orig) { .b = { \
@ -71,7 +71,7 @@ struct bt_link_s {
struct bt_device_s {
int lt_addr;
a_bdaddr bd_addr;
bdaddr_t bd_addr;
int mtu;
int setup;
struct bt_scatternet_s *net;
@ -451,7 +451,7 @@ typedef struct {
typedef struct {
uint8_t status;
a_bdaddr bdaddr;
bdaddr_t bdaddr;
} __attribute__ ((packed)) status_bdaddr_rp;
#define STATUS_BDADDR_RP_SIZE 7
@ -471,7 +471,7 @@ typedef struct {
#define OCF_CREATE_CONN 0x0005
typedef struct {
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint16_t pkt_type;
uint8_t pscan_rep_mode;
uint8_t pscan_mode;
@ -497,33 +497,33 @@ typedef struct {
#define OCF_CREATE_CONN_CANCEL 0x0008
typedef struct {
uint8_t status;
a_bdaddr bdaddr;
bdaddr_t bdaddr;
} __attribute__ ((packed)) create_conn_cancel_cp;
#define CREATE_CONN_CANCEL_CP_SIZE 6
typedef struct {
uint8_t status;
a_bdaddr bdaddr;
bdaddr_t bdaddr;
} __attribute__ ((packed)) create_conn_cancel_rp;
#define CREATE_CONN_CANCEL_RP_SIZE 7
#define OCF_ACCEPT_CONN_REQ 0x0009
typedef struct {
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint8_t role;
} __attribute__ ((packed)) accept_conn_req_cp;
#define ACCEPT_CONN_REQ_CP_SIZE 7
#define OCF_REJECT_CONN_REQ 0x000A
typedef struct {
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint8_t reason;
} __attribute__ ((packed)) reject_conn_req_cp;
#define REJECT_CONN_REQ_CP_SIZE 7
#define OCF_LINK_KEY_REPLY 0x000B
typedef struct {
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint8_t link_key[16];
} __attribute__ ((packed)) link_key_reply_cp;
#define LINK_KEY_REPLY_CP_SIZE 22
@ -532,7 +532,7 @@ typedef struct {
#define OCF_PIN_CODE_REPLY 0x000D
typedef struct {
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint8_t pin_len;
uint8_t pin_code[16];
} __attribute__ ((packed)) pin_code_reply_cp;
@ -574,7 +574,7 @@ typedef struct {
#define OCF_REMOTE_NAME_REQ 0x0019
typedef struct {
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint8_t pscan_rep_mode;
uint8_t pscan_mode;
uint16_t clock_offset;
@ -583,13 +583,13 @@ typedef struct {
#define OCF_REMOTE_NAME_REQ_CANCEL 0x001A
typedef struct {
a_bdaddr bdaddr;
bdaddr_t bdaddr;
} __attribute__ ((packed)) remote_name_req_cancel_cp;
#define REMOTE_NAME_REQ_CANCEL_CP_SIZE 6
typedef struct {
uint8_t status;
a_bdaddr bdaddr;
bdaddr_t bdaddr;
} __attribute__ ((packed)) remote_name_req_cancel_rp;
#define REMOTE_NAME_REQ_CANCEL_RP_SIZE 7
@ -646,7 +646,7 @@ typedef struct {
#define OCF_ACCEPT_SYNC_CONN_REQ 0x0029
typedef struct {
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint32_t tx_bandwith;
uint32_t rx_bandwith;
uint16_t max_latency;
@ -658,7 +658,7 @@ typedef struct {
#define OCF_REJECT_SYNC_CONN_REQ 0x002A
typedef struct {
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint8_t reason;
} __attribute__ ((packed)) reject_sync_conn_req_cp;
#define REJECT_SYNC_CONN_REQ_CP_SIZE 7
@ -734,7 +734,7 @@ typedef struct {
#define OCF_SWITCH_ROLE 0x000B
typedef struct {
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint8_t role;
} __attribute__ ((packed)) switch_role_cp;
#define SWITCH_ROLE_CP_SIZE 7
@ -847,7 +847,7 @@ typedef struct {
#define OCF_READ_STORED_LINK_KEY 0x000D
typedef struct {
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint8_t read_all;
} __attribute__ ((packed)) read_stored_link_key_cp;
#define READ_STORED_LINK_KEY_CP_SIZE 7
@ -872,7 +872,7 @@ typedef struct {
#define OCF_DELETE_STORED_LINK_KEY 0x0012
typedef struct {
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint8_t delete_all;
} __attribute__ ((packed)) delete_stored_link_key_cp;
#define DELETE_STORED_LINK_KEY_CP_SIZE 7
@ -1238,7 +1238,7 @@ typedef struct {
#define OCF_READ_BD_ADDR 0x0009
typedef struct {
uint8_t status;
a_bdaddr bdaddr;
bdaddr_t bdaddr;
} __attribute__ ((packed)) read_bd_addr_rp;
#define READ_BD_ADDR_RP_SIZE 7
@ -1317,7 +1317,7 @@ typedef struct {
#define EVT_INQUIRY_RESULT 0x02
typedef struct {
uint8_t num_responses;
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint8_t pscan_rep_mode;
uint8_t pscan_period_mode;
uint8_t pscan_mode;
@ -1330,7 +1330,7 @@ typedef struct {
typedef struct {
uint8_t status;
uint16_t handle;
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint8_t link_type;
uint8_t encr_mode;
} __attribute__ ((packed)) evt_conn_complete;
@ -1338,7 +1338,7 @@ typedef struct {
#define EVT_CONN_REQUEST 0x04
typedef struct {
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint8_t dev_class[3];
uint8_t link_type;
} __attribute__ ((packed)) evt_conn_request;
@ -1362,7 +1362,7 @@ typedef struct {
#define EVT_REMOTE_NAME_REQ_COMPLETE 0x07
typedef struct {
uint8_t status;
a_bdaddr bdaddr;
bdaddr_t bdaddr;
char name[248];
} __attribute__ ((packed)) evt_remote_name_req_complete;
#define EVT_REMOTE_NAME_REQ_COMPLETE_SIZE 255
@ -1447,7 +1447,7 @@ typedef struct {
#define EVT_ROLE_CHANGE 0x12
typedef struct {
uint8_t status;
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint8_t role;
} __attribute__ ((packed)) evt_role_change;
#define EVT_ROLE_CHANGE_SIZE 8
@ -1480,19 +1480,19 @@ typedef struct {
#define EVT_PIN_CODE_REQ 0x16
typedef struct {
a_bdaddr bdaddr;
bdaddr_t bdaddr;
} __attribute__ ((packed)) evt_pin_code_req;
#define EVT_PIN_CODE_REQ_SIZE 6
#define EVT_LINK_KEY_REQ 0x17
typedef struct {
a_bdaddr bdaddr;
bdaddr_t bdaddr;
} __attribute__ ((packed)) evt_link_key_req;
#define EVT_LINK_KEY_REQ_SIZE 6
#define EVT_LINK_KEY_NOTIFY 0x18
typedef struct {
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint8_t link_key[16];
uint8_t key_type;
} __attribute__ ((packed)) evt_link_key_notify;
@ -1537,7 +1537,7 @@ typedef struct {
#define EVT_PSCAN_REP_MODE_CHANGE 0x20
typedef struct {
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint8_t pscan_rep_mode;
} __attribute__ ((packed)) evt_pscan_rep_mode_change;
#define EVT_PSCAN_REP_MODE_CHANGE_SIZE 7
@ -1555,7 +1555,7 @@ typedef struct {
#define EVT_INQUIRY_RESULT_WITH_RSSI 0x22
typedef struct {
uint8_t num_responses;
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint8_t pscan_rep_mode;
uint8_t pscan_period_mode;
uint8_t dev_class[3];
@ -1565,7 +1565,7 @@ typedef struct {
#define INQUIRY_INFO_WITH_RSSI_SIZE 15
typedef struct {
uint8_t num_responses;
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint8_t pscan_rep_mode;
uint8_t pscan_period_mode;
uint8_t pscan_mode;
@ -1589,7 +1589,7 @@ typedef struct {
typedef struct {
uint8_t status;
uint16_t handle;
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint8_t link_type;
uint8_t trans_interval;
uint8_t retrans_window;
@ -1623,7 +1623,7 @@ typedef struct {
#define EVT_EXTENDED_INQUIRY_RESULT 0x2F
typedef struct {
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint8_t pscan_rep_mode;
uint8_t pscan_period_mode;
uint8_t dev_class[3];

50
hw/cirrus_vga.c
View File

@ -1214,7 +1214,7 @@ static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
/* Thinking about changing bank base? First, drop the dirty bitmap information
* on the current location, otherwise we lose this pointer forever */
if (s->vga.lfb_vram_mapped) {
a_target_phys_addr base_addr = isa_mem_base + 0xa0000 + bank_index * 0x8000;
target_phys_addr_t base_addr = isa_mem_base + 0xa0000 + bank_index * 0x8000;
cpu_physical_sync_dirty_bitmap(base_addr, base_addr + 0x8000);
}
s->cirrus_bank_base[bank_index] = offset;
@ -1988,7 +1988,7 @@ static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
*
***************************************/
static uint32_t cirrus_vga_mem_readb(void *opaque, a_target_phys_addr addr)
static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
{
CirrusVGAState *s = opaque;
unsigned bank_index;
@ -2032,7 +2032,7 @@ static uint32_t cirrus_vga_mem_readb(void *opaque, a_target_phys_addr addr)
return val;
}
static uint32_t cirrus_vga_mem_readw(void *opaque, a_target_phys_addr addr)
static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
@ -2045,7 +2045,7 @@ static uint32_t cirrus_vga_mem_readw(void *opaque, a_target_phys_addr addr)
return v;
}
static uint32_t cirrus_vga_mem_readl(void *opaque, a_target_phys_addr addr)
static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
@ -2062,7 +2062,7 @@ static uint32_t cirrus_vga_mem_readl(void *opaque, a_target_phys_addr addr)
return v;
}
static void cirrus_vga_mem_writeb(void *opaque, a_target_phys_addr addr,
static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
uint32_t mem_value)
{
CirrusVGAState *s = opaque;
@ -2127,7 +2127,7 @@ static void cirrus_vga_mem_writeb(void *opaque, a_target_phys_addr addr,
}
}
static void cirrus_vga_mem_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
cirrus_vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
@ -2138,7 +2138,7 @@ static void cirrus_vga_mem_writew(void *opaque, a_target_phys_addr addr, uint32_
#endif
}
static void cirrus_vga_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
cirrus_vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
@ -2341,7 +2341,7 @@ static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y)
*
***************************************/
static uint32_t cirrus_linear_readb(void *opaque, a_target_phys_addr addr)
static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)
{
CirrusVGAState *s = opaque;
uint32_t ret;
@ -2369,7 +2369,7 @@ static uint32_t cirrus_linear_readb(void *opaque, a_target_phys_addr addr)
return ret;
}
static uint32_t cirrus_linear_readw(void *opaque, a_target_phys_addr addr)
static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
@ -2382,7 +2382,7 @@ static uint32_t cirrus_linear_readw(void *opaque, a_target_phys_addr addr)
return v;
}
static uint32_t cirrus_linear_readl(void *opaque, a_target_phys_addr addr)
static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
@ -2399,7 +2399,7 @@ static uint32_t cirrus_linear_readl(void *opaque, a_target_phys_addr addr)
return v;
}
static void cirrus_linear_writeb(void *opaque, a_target_phys_addr addr,
static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
CirrusVGAState *s = opaque;
@ -2440,7 +2440,7 @@ static void cirrus_linear_writeb(void *opaque, a_target_phys_addr addr,
}
}
static void cirrus_linear_writew(void *opaque, a_target_phys_addr addr,
static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
@ -2452,7 +2452,7 @@ static void cirrus_linear_writew(void *opaque, a_target_phys_addr addr,
#endif
}
static void cirrus_linear_writel(void *opaque, a_target_phys_addr addr,
static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
@ -2488,7 +2488,7 @@ static CPUWriteMemoryFunc * const cirrus_linear_write[3] = {
***************************************/
static uint32_t cirrus_linear_bitblt_readb(void *opaque, a_target_phys_addr addr)
static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr)
{
uint32_t ret;
@ -2497,7 +2497,7 @@ static uint32_t cirrus_linear_bitblt_readb(void *opaque, a_target_phys_addr addr
return ret;
}
static uint32_t cirrus_linear_bitblt_readw(void *opaque, a_target_phys_addr addr)
static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
@ -2510,7 +2510,7 @@ static uint32_t cirrus_linear_bitblt_readw(void *opaque, a_target_phys_addr addr
return v;
}
static uint32_t cirrus_linear_bitblt_readl(void *opaque, a_target_phys_addr addr)
static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
@ -2527,7 +2527,7 @@ static uint32_t cirrus_linear_bitblt_readl(void *opaque, a_target_phys_addr addr
return v;
}
static void cirrus_linear_bitblt_writeb(void *opaque, a_target_phys_addr addr,
static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
CirrusVGAState *s = opaque;
@ -2541,7 +2541,7 @@ static void cirrus_linear_bitblt_writeb(void *opaque, a_target_phys_addr addr,
}
}
static void cirrus_linear_bitblt_writew(void *opaque, a_target_phys_addr addr,
static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
@ -2553,7 +2553,7 @@ static void cirrus_linear_bitblt_writew(void *opaque, a_target_phys_addr addr,
#endif
}
static void cirrus_linear_bitblt_writel(void *opaque, a_target_phys_addr addr,
static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
@ -2855,7 +2855,7 @@ static void cirrus_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
*
***************************************/
static uint32_t cirrus_mmio_readb(void *opaque, a_target_phys_addr addr)
static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr)
{
CirrusVGAState *s = opaque;
@ -2868,7 +2868,7 @@ static uint32_t cirrus_mmio_readb(void *opaque, a_target_phys_addr addr)
}
}
static uint32_t cirrus_mmio_readw(void *opaque, a_target_phys_addr addr)
static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
@ -2881,7 +2881,7 @@ static uint32_t cirrus_mmio_readw(void *opaque, a_target_phys_addr addr)
return v;
}
static uint32_t cirrus_mmio_readl(void *opaque, a_target_phys_addr addr)
static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
@ -2898,7 +2898,7 @@ static uint32_t cirrus_mmio_readl(void *opaque, a_target_phys_addr addr)
return v;
}
static void cirrus_mmio_writeb(void *opaque, a_target_phys_addr addr,
static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
CirrusVGAState *s = opaque;
@ -2912,7 +2912,7 @@ static void cirrus_mmio_writeb(void *opaque, a_target_phys_addr addr,
}
}
static void cirrus_mmio_writew(void *opaque, a_target_phys_addr addr,
static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
@ -2924,7 +2924,7 @@ static void cirrus_mmio_writew(void *opaque, a_target_phys_addr addr,
#endif
}
static void cirrus_mmio_writel(void *opaque, a_target_phys_addr addr,
static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN

4
hw/cs4231.c
View File

@ -64,7 +64,7 @@ static void cs_reset(void *opaque)
s->dregs[25] = CS_VER;
}
static uint32_t cs_mem_readl(void *opaque, a_target_phys_addr addr)
static uint32_t cs_mem_readl(void *opaque, target_phys_addr_t addr)
{
CSState *s = opaque;
uint32_t saddr, ret;
@ -90,7 +90,7 @@ static uint32_t cs_mem_readl(void *opaque, a_target_phys_addr addr)
return ret;
}
static void cs_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
static void cs_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
CSState *s = opaque;
uint32_t saddr;

12
hw/cuda.c
View File

@ -250,7 +250,7 @@ static void cuda_timer1(void *opaque)
cuda_update_irq(s);
}
static uint32_t cuda_readb(void *opaque, a_target_phys_addr addr)
static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr)
{
CUDAState *s = opaque;
uint32_t val;
@ -321,7 +321,7 @@ static uint32_t cuda_readb(void *opaque, a_target_phys_addr addr)
return val;
}
static void cuda_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
CUDAState *s = opaque;
@ -612,20 +612,20 @@ static void cuda_receive_packet_from_host(CUDAState *s,
}
}
static void cuda_writew (void *opaque, a_target_phys_addr addr, uint32_t value)
static void cuda_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
{
}
static void cuda_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
static void cuda_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
}
static uint32_t cuda_readw (void *opaque, a_target_phys_addr addr)
static uint32_t cuda_readw (void *opaque, target_phys_addr_t addr)
{
return 0;
}
static uint32_t cuda_readl (void *opaque, a_target_phys_addr addr)
static uint32_t cuda_readl (void *opaque, target_phys_addr_t addr)
{
return 0;
}

4
hw/dma.c
View File

@ -401,7 +401,7 @@ void DMA_register_channel (int nchan,
int DMA_read_memory (int nchan, void *buf, int pos, int len)
{
struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
a_target_phys_addr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
if (r->mode & 0x20) {
int i;
@ -423,7 +423,7 @@ int DMA_read_memory (int nchan, void *buf, int pos, int len)
int DMA_write_memory (int nchan, void *buf, int pos, int len)
{
struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
a_target_phys_addr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
if (r->mode & 0x20) {
int i;

18
hw/dp8393x.c
View File

@ -166,7 +166,7 @@ typedef struct dp8393xState {
int loopback_packet;
/* Memory access */
void (*memory_rw)(void *opaque, a_target_phys_addr addr, uint8_t *buf, int len, int is_write);
void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write);
void* mem_opaque;
} dp8393xState;
@ -601,7 +601,7 @@ static void dp8393x_watchdog(void *opaque)
dp8393x_update_irq(s);
}
static uint32_t dp8393x_readw(void *opaque, a_target_phys_addr addr)
static uint32_t dp8393x_readw(void *opaque, target_phys_addr_t addr)
{
dp8393xState *s = opaque;
int reg;
@ -614,13 +614,13 @@ static uint32_t dp8393x_readw(void *opaque, a_target_phys_addr addr)
return read_register(s, reg);
}
static uint32_t dp8393x_readb(void *opaque, a_target_phys_addr addr)
static uint32_t dp8393x_readb(void *opaque, target_phys_addr_t addr)
{
uint16_t v = dp8393x_readw(opaque, addr & ~0x1);
return (v >> (8 * (addr & 0x1))) & 0xff;
}
static uint32_t dp8393x_readl(void *opaque, a_target_phys_addr addr)
static uint32_t dp8393x_readl(void *opaque, target_phys_addr_t addr)
{
uint32_t v;
v = dp8393x_readw(opaque, addr);
@ -628,7 +628,7 @@ static uint32_t dp8393x_readl(void *opaque, a_target_phys_addr addr)
return v;
}
static void dp8393x_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
static void dp8393x_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
dp8393xState *s = opaque;
int reg;
@ -642,7 +642,7 @@ static void dp8393x_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
write_register(s, reg, (uint16_t)val);
}
static void dp8393x_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
static void dp8393x_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
uint16_t old_val = dp8393x_readw(opaque, addr & ~0x1);
@ -657,7 +657,7 @@ static void dp8393x_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
dp8393x_writew(opaque, addr & ~0x1, val);
}
static void dp8393x_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
static void dp8393x_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
dp8393x_writew(opaque, addr, val & 0xffff);
dp8393x_writew(opaque, addr + 2, (val >> 16) & 0xffff);
@ -872,9 +872,9 @@ static void nic_cleanup(VLANClientState *vc)
qemu_free(s);
}
void dp83932_init(NICInfo *nd, a_target_phys_addr base, int it_shift,
void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
qemu_irq irq, void* mem_opaque,
void (*memory_rw)(void *opaque, a_target_phys_addr addr, uint8_t *buf, int len, int is_write))
void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write))
{
dp8393xState *s;

32
hw/ds1225y.c
View File

@ -34,12 +34,12 @@ typedef struct ds1225y_t
QEMUFile *file;
uint8_t *contents;
uint8_t protection;
} a_ds1225y;
} ds1225y_t;
static uint32_t nvram_readb (void *opaque, a_target_phys_addr addr)
static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
{
a_ds1225y *s = opaque;
ds1225y_t *s = opaque;
uint32_t val;
val = s->contents[addr];
@ -50,7 +50,7 @@ static uint32_t nvram_readb (void *opaque, a_target_phys_addr addr)
return val;
}
static uint32_t nvram_readw (void *opaque, a_target_phys_addr addr)
static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
{
uint32_t v;
v = nvram_readb(opaque, addr);
@ -58,7 +58,7 @@ static uint32_t nvram_readw (void *opaque, a_target_phys_addr addr)
return v;
}
static uint32_t nvram_readl (void *opaque, a_target_phys_addr addr)
static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
{
uint32_t v;
v = nvram_readb(opaque, addr);
@ -68,9 +68,9 @@ static uint32_t nvram_readl (void *opaque, a_target_phys_addr addr)
return v;
}
static void nvram_writeb (void *opaque, a_target_phys_addr addr, uint32_t val)
static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
{
a_ds1225y *s = opaque;
ds1225y_t *s = opaque;
#ifdef DEBUG_NVRAM
printf("nvram: write 0x%x at " TARGET_FMT_lx "\n", val, addr);
@ -84,13 +84,13 @@ static void nvram_writeb (void *opaque, a_target_phys_addr addr, uint32_t val)
}
}
static void nvram_writew (void *opaque, a_target_phys_addr addr, uint32_t val)
static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
{
nvram_writeb(opaque, addr, val & 0xff);
nvram_writeb(opaque, addr + 1, (val >> 8) & 0xff);
}
static void nvram_writel (void *opaque, a_target_phys_addr addr, uint32_t val)
static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
{
nvram_writeb(opaque, addr, val & 0xff);
nvram_writeb(opaque, addr + 1, (val >> 8) & 0xff);
@ -98,9 +98,9 @@ static void nvram_writel (void *opaque, a_target_phys_addr addr, uint32_t val)
nvram_writeb(opaque, addr + 3, (val >> 24) & 0xff);
}
static void nvram_writeb_protected (void *opaque, a_target_phys_addr addr, uint32_t val)
static void nvram_writeb_protected (void *opaque, target_phys_addr_t addr, uint32_t val)
{
a_ds1225y *s = opaque;
ds1225y_t *s = opaque;
if (s->protection != 7) {
#ifdef DEBUG_NVRAM
@ -112,13 +112,13 @@ static void nvram_writeb_protected (void *opaque, a_target_phys_addr addr, uint3
nvram_writeb(opaque, addr, val);
}
static void nvram_writew_protected (void *opaque, a_target_phys_addr addr, uint32_t val)
static void nvram_writew_protected (void *opaque, target_phys_addr_t addr, uint32_t val)
{
nvram_writeb_protected(opaque, addr, val & 0xff);
nvram_writeb_protected(opaque, addr + 1, (val >> 8) & 0xff);
}
static void nvram_writel_protected (void *opaque, a_target_phys_addr addr, uint32_t val)
static void nvram_writel_protected (void *opaque, target_phys_addr_t addr, uint32_t val)
{
nvram_writeb_protected(opaque, addr, val & 0xff);
nvram_writeb_protected(opaque, addr + 1, (val >> 8) & 0xff);
@ -145,13 +145,13 @@ static CPUWriteMemoryFunc * const nvram_write_protected[] = {
};
/* Initialisation routine */
void *ds1225y_init(a_target_phys_addr mem_base, const char *filename)
void *ds1225y_init(target_phys_addr_t mem_base, const char *filename)
{
a_ds1225y *s;
ds1225y_t *s;
int mem_indexRW, mem_indexRP;
QEMUFile *file;
s = qemu_mallocz(sizeof(a_ds1225y));
s = qemu_mallocz(sizeof(ds1225y_t));
s->chip_size = 0x2000; /* Fixed for ds1225y chip: 8 KiB */
s->contents = qemu_mallocz(s->chip_size);
s->protection = 7;

4
hw/dummy_m68k.c
View File

@ -16,7 +16,7 @@
/* Board init. */
static void dummy_m68k_init(a_ram_addr ram_size,
static void dummy_m68k_init(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@ -24,7 +24,7 @@ static void dummy_m68k_init(a_ram_addr ram_size,
CPUState *env;
int kernel_size;
uint64_t elf_entry;
a_target_phys_addr entry;
target_phys_addr_t entry;
if (!cpu_model)
cpu_model = "cfv4e";

18
hw/e1000.c
View File

@ -478,7 +478,7 @@ process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
}
static uint32_t
txdesc_writeback(a_target_phys_addr base, struct e1000_tx_desc *dp)
txdesc_writeback(target_phys_addr_t base, struct e1000_tx_desc *dp)
{
uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data);
@ -495,7 +495,7 @@ txdesc_writeback(a_target_phys_addr base, struct e1000_tx_desc *dp)
static void
start_xmit(E1000State *s)
{
a_target_phys_addr base;
target_phys_addr_t base;
struct e1000_tx_desc desc;
uint32_t tdh_start = s->mac_reg[TDH], cause = E1000_ICS_TXQE;
@ -613,7 +613,7 @@ e1000_receive(VLANClientState *vc, const uint8_t *buf, size_t size)
{
E1000State *s = vc->opaque;
struct e1000_rx_desc desc;
a_target_phys_addr base;
target_phys_addr_t base;
unsigned int n, rdt;
uint32_t rdh_start;
uint16_t vlan_special = 0;
@ -814,7 +814,7 @@ static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
static void
e1000_mmio_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
e1000_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
E1000State *s = opaque;
unsigned int index = (addr & 0x1ffff) >> 2;
@ -832,7 +832,7 @@ e1000_mmio_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
}
static void
e1000_mmio_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
e1000_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
// emulate hw without byte enables: no RMW
e1000_mmio_writel(opaque, addr & ~3,
@ -840,7 +840,7 @@ e1000_mmio_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
}
static void
e1000_mmio_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
e1000_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
// emulate hw without byte enables: no RMW
e1000_mmio_writel(opaque, addr & ~3,
@ -848,7 +848,7 @@ e1000_mmio_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
}
static uint32_t
e1000_mmio_readl(void *opaque, a_target_phys_addr addr)
e1000_mmio_readl(void *opaque, target_phys_addr_t addr)
{
E1000State *s = opaque;
unsigned int index = (addr & 0x1ffff) >> 2;
@ -866,14 +866,14 @@ e1000_mmio_readl(void *opaque, a_target_phys_addr addr)
}
static uint32_t
e1000_mmio_readb(void *opaque, a_target_phys_addr addr)
e1000_mmio_readb(void *opaque, target_phys_addr_t addr)
{
return ((e1000_mmio_readl(opaque, addr & ~3)) >>
(8 * (addr & 3))) & 0xff;
}
static uint32_t
e1000_mmio_readw(void *opaque, a_target_phys_addr addr)
e1000_mmio_readw(void *opaque, target_phys_addr_t addr)
{
return ((e1000_mmio_readl(opaque, addr & ~3)) >>
(8 * (addr & 3))) & 0xffff;

8
hw/eccmemctl.c
View File

@ -133,7 +133,7 @@ typedef struct ECCState {
uint32_t version;
} ECCState;
static void ecc_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
ECCState *s = opaque;
@ -175,7 +175,7 @@ static void ecc_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
}
}
static uint32_t ecc_mem_readl(void *opaque, a_target_phys_addr addr)
static uint32_t ecc_mem_readl(void *opaque, target_phys_addr_t addr)
{
ECCState *s = opaque;
uint32_t ret = 0;
@ -233,7 +233,7 @@ static CPUWriteMemoryFunc * const ecc_mem_write[3] = {
ecc_mem_writel,
};
static void ecc_diag_mem_writeb(void *opaque, a_target_phys_addr addr,
static void ecc_diag_mem_writeb(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
ECCState *s = opaque;
@ -242,7 +242,7 @@ static void ecc_diag_mem_writeb(void *opaque, a_target_phys_addr addr,
s->diag[addr & ECC_DIAG_MASK] = val;
}
static uint32_t ecc_diag_mem_readb(void *opaque, a_target_phys_addr addr)
static uint32_t ecc_diag_mem_readb(void *opaque, target_phys_addr_t addr)
{
ECCState *s = opaque;
uint32_t ret = s->diag[(int)addr];

54
hw/eepro100.c
View File

@ -144,7 +144,7 @@ typedef struct {
//~ int32_t tx_buf_size0; /* Length of Tx hdr. */
//~ uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
//~ int32_t tx_buf_size1; /* Length of Tx data. */
} a_eepro100_tx;
} eepro100_tx_t;
/* Receive frame descriptor. */
typedef struct {
@ -155,7 +155,7 @@ typedef struct {
uint16_t count;
uint16_t size;
char packet[MAX_ETH_FRAME_SIZE + 4];
} a_eepro100_rx;
} eepro100_rx_t;
typedef struct {
uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions,
@ -167,7 +167,7 @@ typedef struct {
uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
uint16_t xmt_tco_frames, rcv_tco_frames;
uint32_t complete;
} a_eepro100_stats;
} eepro100_stats_t;
typedef enum {
cu_idle = 0,
@ -175,14 +175,14 @@ typedef enum {
cu_active = 2,
cu_lpq_active = 2,
cu_hqp_active = 3
} a_cu_state;
} cu_state_t;
typedef enum {
ru_idle = 0,
ru_suspended = 1,
ru_no_resources = 2,
ru_ready = 4
} a_ru_state;
} ru_state_t;
typedef struct {
PCIDevice dev;
@ -213,7 +213,7 @@ typedef struct {
uint8_t macaddr[6];
uint32_t statcounter[19];
uint16_t mdimem[32];
a_eeprom *eeprom;
eeprom_t *eeprom;
uint32_t device; /* device variant */
uint32_t pointer;
/* (cu_base + cu_offset) address the next command block in the command block list. */
@ -222,8 +222,8 @@ typedef struct {
/* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
uint32_t ru_base; /* RU base address */
uint32_t ru_offset; /* RU address offset */
uint32_t statsaddr; /* pointer to a_eepro100_stats */
a_eepro100_stats statistics; /* statistical counters */
uint32_t statsaddr; /* pointer to eepro100_stats_t */
eepro100_stats_t statistics; /* statistical counters */
#if 0
uint16_t status;
#endif
@ -600,22 +600,22 @@ enum commands {
CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */
};
static a_cu_state get_cu_state(EEPRO100State * s)
static cu_state_t get_cu_state(EEPRO100State * s)
{
return ((s->mem[SCBStatus] >> 6) & 0x03);
}
static void set_cu_state(EEPRO100State * s, a_cu_state state)
static void set_cu_state(EEPRO100State * s, cu_state_t state)
{
s->mem[SCBStatus] = (s->mem[SCBStatus] & 0x3f) + (state << 6);
}
static a_ru_state get_ru_state(EEPRO100State * s)
static ru_state_t get_ru_state(EEPRO100State * s)
{
return ((s->mem[SCBStatus] >> 2) & 0x0f);
}
static void set_ru_state(EEPRO100State * s, a_ru_state state)
static void set_ru_state(EEPRO100State * s, ru_state_t state)
{
s->mem[SCBStatus] = (s->mem[SCBStatus] & 0xc3) + (state << 2);
}
@ -639,7 +639,7 @@ static void dump_statistics(EEPRO100State * s)
static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
{
a_eepro100_tx tx;
eepro100_tx_t tx;
uint32_t cb_address;
switch (val) {
case CU_NOP:
@ -915,7 +915,7 @@ static uint16_t eepro100_read_eeprom(EEPRO100State * s)
return val;
}
static void eepro100_write_eeprom(a_eeprom * eeprom, uint8_t val)
static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
{
TRACE(EEPROM, logout("val=0x%02x\n", val));
@ -1099,7 +1099,7 @@ static void eepro100_write_mdi(EEPRO100State * s, uint32_t val)
typedef struct {
uint32_t st_sign; /* Self Test Signature */
uint32_t st_result; /* Self Test Results */
} a_eepro100_selftest;
} eepro100_selftest_t;
static uint32_t eepro100_read_port(EEPRO100State * s)
{
@ -1117,7 +1117,7 @@ static void eepro100_write_port(EEPRO100State * s, uint32_t val)
break;
case PORT_SELFTEST:
TRACE(OTHER, logout("selftest address=0x%08x\n", address));
a_eepro100_selftest data;
eepro100_selftest_t data;
cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data));
data.st_sign = 0xffffffff;
data.st_result = 0;
@ -1398,42 +1398,42 @@ static void pci_map(PCIDevice * pci_dev, int region_num,
*
****************************************************************************/
static void pci_mmio_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
EEPRO100State *s = opaque;
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
eepro100_write1(s, addr, val);
}
static void pci_mmio_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
EEPRO100State *s = opaque;
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
eepro100_write2(s, addr, val);
}
static void pci_mmio_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
EEPRO100State *s = opaque;
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
eepro100_write4(s, addr, val);
}
static uint32_t pci_mmio_readb(void *opaque, a_target_phys_addr addr)
static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr)
{
EEPRO100State *s = opaque;
//~ logout("addr=%s\n", regname(addr));
return eepro100_read1(s, addr);
}
static uint32_t pci_mmio_readw(void *opaque, a_target_phys_addr addr)
static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr)
{
EEPRO100State *s = opaque;
//~ logout("addr=%s\n", regname(addr));
return eepro100_read2(s, addr);
}
static uint32_t pci_mmio_readl(void *opaque, a_target_phys_addr addr)
static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr)
{
EEPRO100State *s = opaque;
//~ logout("addr=%s\n", regname(addr));
@ -1541,9 +1541,9 @@ static ssize_t nic_receive(VLANClientState *vc, const uint8_t * buf, size_t size
}
//~ !!!
//~ $3 = {status = 0x0, command = 0xc000, link = 0x2d220, rx_buf_addr = 0x207dc, count = 0x0, size = 0x5f8, packet = {0x0 <repeats 1518 times>}}
a_eepro100_rx rx;
eepro100_rx_t rx;
cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx,
offsetof(a_eepro100_rx, packet));
offsetof(eepro100_rx_t, packet));
uint16_t rfd_command = le16_to_cpu(rx.command);
uint16_t rfd_size = le16_to_cpu(rx.size);
assert(size <= rfd_size);
@ -1552,9 +1552,9 @@ static ssize_t nic_receive(VLANClientState *vc, const uint8_t * buf, size_t size
}
TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
rfd_command, rx.link, rx.rx_buf_addr, rfd_size));
stw_phys(s->ru_base + s->ru_offset + offsetof(a_eepro100_rx, status),
stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status),
rfd_status);
stw_phys(s->ru_base + s->ru_offset + offsetof(a_eepro100_rx, count), size);
stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size);
/* Early receive interrupt not supported. */
//~ eepro100_er_interrupt(s);
/* Receive CRC Transfer not supported. */
@ -1562,7 +1562,7 @@ static ssize_t nic_receive(VLANClientState *vc, const uint8_t * buf, size_t size
/* TODO: check stripping enable bit. */
//~ assert(!(s->configuration[17] & 1));
cpu_physical_memory_write(s->ru_base + s->ru_offset +
offsetof(a_eepro100_rx, packet), buf, size);
offsetof(eepro100_rx_t, packet), buf, size);
s->statistics.rx_good_frames++;
eepro100_fr_interrupt(s);
s->ru_offset = le32_to_cpu(rx.link);

20
hw/eeprom93xx.c
View File

@ -71,7 +71,7 @@ static const char *opstring[] = {
};
#endif
struct eeprom {
struct _eeprom_t {
uint8_t tick;
uint8_t address;
uint8_t command;
@ -93,7 +93,7 @@ static void eeprom_save(QEMUFile *f, void *opaque)
{
/* Save EEPROM data. */
unsigned address;
a_eeprom *eeprom = (a_eeprom *)opaque;
eeprom_t *eeprom = (eeprom_t *)opaque;
qemu_put_byte(f, eeprom->tick);
qemu_put_byte(f, eeprom->address);
@ -116,7 +116,7 @@ static int eeprom_load(QEMUFile *f, void *opaque, int version_id)
{
/* Load EEPROM data from saved data if version and EEPROM size
of data and current EEPROM are identical. */
a_eeprom *eeprom = (a_eeprom *)opaque;
eeprom_t *eeprom = (eeprom_t *)opaque;
int result = -EINVAL;
if (version_id >= OLD_EEPROM_VERSION) {
unsigned address;
@ -150,7 +150,7 @@ static int eeprom_load(QEMUFile *f, void *opaque, int version_id)
return result;
}
void eeprom93xx_write(a_eeprom *eeprom, int eecs, int eesk, int eedi)
void eeprom93xx_write(eeprom_t *eeprom, int eecs, int eesk, int eedi)
{
uint8_t tick = eeprom->tick;
uint8_t eedo = eeprom->eedo;
@ -275,7 +275,7 @@ void eeprom93xx_write(a_eeprom *eeprom, int eecs, int eesk, int eedi)
eeprom->command = command;
}
uint16_t eeprom93xx_read(a_eeprom *eeprom)
uint16_t eeprom93xx_read(eeprom_t *eeprom)
{
/* Return status of pin DO (0 or 1). */
logout("CS=%u DO=%u\n", eeprom->eecs, eeprom->eedo);
@ -292,10 +292,10 @@ void eeprom93xx_reset(eeprom_t *eeprom)
}
#endif
a_eeprom *eeprom93xx_new(uint16_t nwords)
eeprom_t *eeprom93xx_new(uint16_t nwords)
{
/* Add a new EEPROM (with 16, 64 or 256 words). */
a_eeprom *eeprom;
eeprom_t *eeprom;
uint8_t addrbits;
switch (nwords) {
@ -313,7 +313,7 @@ a_eeprom *eeprom93xx_new(uint16_t nwords)
addrbits = 6;
}
eeprom = (a_eeprom *)qemu_mallocz(sizeof(*eeprom) + nwords * 2);
eeprom = (eeprom_t *)qemu_mallocz(sizeof(*eeprom) + nwords * 2);
eeprom->size = nwords;
eeprom->addrbits = addrbits;
/* Output DO is tristate, read results in 1. */
@ -324,7 +324,7 @@ a_eeprom *eeprom93xx_new(uint16_t nwords)
return eeprom;
}
void eeprom93xx_free(a_eeprom *eeprom)
void eeprom93xx_free(eeprom_t *eeprom)
{
/* Destroy EEPROM. */
logout("eeprom = 0x%p\n", eeprom);
@ -332,7 +332,7 @@ void eeprom93xx_free(a_eeprom *eeprom)
qemu_free(eeprom);
}
uint16_t *eeprom93xx_data(a_eeprom *eeprom)
uint16_t *eeprom93xx_data(eeprom_t *eeprom)
{
/* Get EEPROM data array. */
return &eeprom->contents[0];

12
hw/eeprom93xx.h
View File

@ -20,21 +20,21 @@
#ifndef EEPROM93XX_H
#define EEPROM93XX_H
typedef struct eeprom a_eeprom;
typedef struct _eeprom_t eeprom_t;
/* Create a new EEPROM with (nwords * 2) bytes. */
a_eeprom *eeprom93xx_new(uint16_t nwords);
eeprom_t *eeprom93xx_new(uint16_t nwords);
/* Destroy an existing EEPROM. */
void eeprom93xx_free(a_eeprom *eeprom);
void eeprom93xx_free(eeprom_t *eeprom);
/* Read from the EEPROM. */
uint16_t eeprom93xx_read(a_eeprom *eeprom);
uint16_t eeprom93xx_read(eeprom_t *eeprom);
/* Write to the EEPROM. */
void eeprom93xx_write(a_eeprom *eeprom, int eecs, int eesk, int eedi);
void eeprom93xx_write(eeprom_t *eeprom, int eecs, int eesk, int eedi);
/* Get EEPROM data array. */
uint16_t *eeprom93xx_data(a_eeprom *eeprom);
uint16_t *eeprom93xx_data(eeprom_t *eeprom);
#endif /* EEPROM93XX_H */

2
hw/elf_ops.h
View File

@ -74,7 +74,7 @@ static int glue(symfind, SZ)(const void *s0, const void *s1)
}
static const char *glue(lookup_symbol, SZ)(struct syminfo *s,
a_target_phys_addr orig_addr)
target_phys_addr_t orig_addr)
{
struct elf_sym *syms = glue(s->disas_symtab.elf, SZ);
struct elf_sym key;

16
hw/escc.c
View File

@ -84,13 +84,13 @@
typedef enum {
chn_a, chn_b,
} e_chn_id;
} chn_id_t;
#define CHN_C(s) ((s)->chn == chn_b? 'b' : 'a')
typedef enum {
ser, kbd, mouse,
} e_chn_type;
} chn_type_t;
#define SERIO_QUEUE_SIZE 256
@ -104,8 +104,8 @@ typedef struct ChannelState {
qemu_irq irq;
uint32_t reg;
uint32_t rxint, txint, rxint_under_svc, txint_under_svc;
e_chn_id chn; // this channel, A (base+4) or B (base+0)
e_chn_type type;
chn_id_t chn; // this channel, A (base+4) or B (base+0)
chn_type_t type;
struct ChannelState *otherchn;
uint8_t rx, tx, wregs[SERIAL_REGS], rregs[SERIAL_REGS];
SERIOQueue queue;
@ -481,7 +481,7 @@ static void escc_update_parameters(ChannelState *s)
qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
}
static void escc_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
static void escc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
SerialState *serial = opaque;
ChannelState *s;
@ -578,7 +578,7 @@ static void escc_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
}
}
static uint32_t escc_mem_readb(void *opaque, a_target_phys_addr addr)
static uint32_t escc_mem_readb(void *opaque, target_phys_addr_t addr)
{
SerialState *serial = opaque;
ChannelState *s;
@ -725,7 +725,7 @@ static int escc_load(QEMUFile *f, void *opaque, int version_id)
}
int escc_init(a_target_phys_addr base, qemu_irq irqA, qemu_irq irqB,
int escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB,
CharDriverState *chrA, CharDriverState *chrB,
int clock, int it_shift)
{
@ -890,7 +890,7 @@ static void sunmouse_event(void *opaque,
put_queue(s, 0);
}
void slavio_serial_ms_kbd_init(a_target_phys_addr base, qemu_irq irq,
void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq,
int disabled, int clock, int it_shift)
{
DeviceState *dev;

4
hw/escc.h
View File

@ -1,8 +1,8 @@
/* escc.c */
#define ESCC_SIZE 4
int escc_init(a_target_phys_addr base, qemu_irq irqA, qemu_irq irqB,
int escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB,
CharDriverState *chrA, CharDriverState *chrB,
int clock, int it_shift);
void slavio_serial_ms_kbd_init(a_target_phys_addr base, qemu_irq irq,
void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq,
int disabled, int clock, int it_shift);

6
hw/esp.c
View File

@ -439,7 +439,7 @@ static void parent_esp_reset(void *opaque, int irq, int level)
esp_reset(opaque);
}
static uint32_t esp_mem_readb(void *opaque, a_target_phys_addr addr)
static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
{
ESPState *s = opaque;
uint32_t saddr, old_val;
@ -480,7 +480,7 @@ static uint32_t esp_mem_readb(void *opaque, a_target_phys_addr addr)
return s->rregs[saddr];
}
static void esp_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
ESPState *s = opaque;
uint32_t saddr;
@ -632,7 +632,7 @@ static const VMStateDescription vmstate_esp = {
}
};
void esp_init(a_target_phys_addr espaddr, int it_shift,
void esp_init(target_phys_addr_t espaddr, int it_shift,
espdma_memory_read_write dma_memory_read,
espdma_memory_read_write dma_memory_write,
void *dma_opaque, qemu_irq irq, qemu_irq *reset)

8
hw/etraxfs.c
View File

@ -45,7 +45,7 @@ static void main_cpu_reset(void *opaque)
}
static
void bareetraxfs_init (a_ram_addr ram_size,
void bareetraxfs_init (ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@ -59,9 +59,9 @@ void bareetraxfs_init (a_ram_addr ram_size,
int kernel_size;
DriveInfo *dinfo;
int i;
a_ram_addr phys_ram;
a_ram_addr phys_flash;
a_ram_addr phys_intmem;
ram_addr_t phys_ram;
ram_addr_t phys_flash;
ram_addr_t phys_intmem;
/* init CPUs */
if (cpu_model == NULL) {

2
hw/etraxfs.h
View File

@ -25,4 +25,4 @@
#include "etraxfs_dma.h"
qemu_irq *cris_pic_init_cpu(CPUState *env);
void *etraxfs_eth_init(NICInfo *nd, a_target_phys_addr base, int phyaddr);
void *etraxfs_eth_init(NICInfo *nd, target_phys_addr_t base, int phyaddr);

22
hw/etraxfs_dma.c
View File

@ -211,7 +211,7 @@ static inline int channel_en(struct fs_dma_ctrl *ctrl, int c)
&& ctrl->channels[c].client;
}
static inline int fs_channel(a_target_phys_addr addr)
static inline int fs_channel(target_phys_addr_t addr)
{
/* Every channel has a 0x2000 ctrl register map. */
return addr >> 13;
@ -220,7 +220,7 @@ static inline int fs_channel(a_target_phys_addr addr)
#ifdef USE_THIS_DEAD_CODE
static void channel_load_g(struct fs_dma_ctrl *ctrl, int c)
{
a_target_phys_addr addr = channel_reg(ctrl, c, RW_GROUP);
target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP);
/* Load and decode. FIXME: handle endianness. */
cpu_physical_memory_read (addr,
@ -252,7 +252,7 @@ static void dump_d(int ch, struct dma_descr_data *d)
static void channel_load_c(struct fs_dma_ctrl *ctrl, int c)
{
a_target_phys_addr addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
/* Load and decode. FIXME: handle endianness. */
cpu_physical_memory_read (addr,
@ -269,7 +269,7 @@ static void channel_load_c(struct fs_dma_ctrl *ctrl, int c)
static void channel_load_d(struct fs_dma_ctrl *ctrl, int c)
{
a_target_phys_addr addr = channel_reg(ctrl, c, RW_SAVED_DATA);
target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
/* Load and decode. FIXME: handle endianness. */
D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
@ -283,7 +283,7 @@ static void channel_load_d(struct fs_dma_ctrl *ctrl, int c)
static void channel_store_c(struct fs_dma_ctrl *ctrl, int c)
{
a_target_phys_addr addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
/* Encode and store. FIXME: handle endianness. */
D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
@ -295,7 +295,7 @@ static void channel_store_c(struct fs_dma_ctrl *ctrl, int c)
static void channel_store_d(struct fs_dma_ctrl *ctrl, int c)
{
a_target_phys_addr addr = channel_reg(ctrl, c, RW_SAVED_DATA);
target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
/* Encode and store. FIXME: handle endianness. */
D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
@ -556,14 +556,14 @@ static inline int channel_in_run(struct fs_dma_ctrl *ctrl, int c)
return 0;
}
static uint32_t dma_rinvalid (void *opaque, a_target_phys_addr addr)
static uint32_t dma_rinvalid (void *opaque, target_phys_addr_t addr)
{
hw_error("Unsupported short raccess. reg=" TARGET_FMT_plx "\n", addr);
return 0;
}
static uint32_t
dma_readl (void *opaque, a_target_phys_addr addr)
dma_readl (void *opaque, target_phys_addr_t addr)
{
struct fs_dma_ctrl *ctrl = opaque;
int c;
@ -591,7 +591,7 @@ dma_readl (void *opaque, a_target_phys_addr addr)
}
static void
dma_winvalid (void *opaque, a_target_phys_addr addr, uint32_t value)
dma_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
{
hw_error("Unsupported short waccess. reg=" TARGET_FMT_plx "\n", addr);
}
@ -608,7 +608,7 @@ dma_update_state(struct fs_dma_ctrl *ctrl, int c)
}
static void
dma_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
dma_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
struct fs_dma_ctrl *ctrl = opaque;
int c;
@ -739,7 +739,7 @@ static void DMA_run(void *opaque)
qemu_bh_schedule_idle(etraxfs_dmac->bh);
}
void *etraxfs_dmac_init(a_target_phys_addr base, int nr_channels)
void *etraxfs_dmac_init(target_phys_addr_t base, int nr_channels)
{
struct fs_dma_ctrl *ctrl = NULL;

2
hw/etraxfs_dma.h
View File

@ -13,7 +13,7 @@ struct etraxfs_dma_client
} client;
};
void *etraxfs_dmac_init(a_target_phys_addr base, int nr_channels);
void *etraxfs_dmac_init(target_phys_addr_t base, int nr_channels);
void etraxfs_dmac_connect(void *opaque, int channel, qemu_irq *line,
int input);
void etraxfs_dmac_connect_client(void *opaque, int c,

6
hw/etraxfs_eth.c
View File

@ -365,7 +365,7 @@ static void eth_validate_duplex(struct fs_eth *eth)
}
}
static uint32_t eth_readl (void *opaque, a_target_phys_addr addr)
static uint32_t eth_readl (void *opaque, target_phys_addr_t addr)
{
struct fs_eth *eth = opaque;
uint32_t r = 0;
@ -409,7 +409,7 @@ static void eth_update_ma(struct fs_eth *eth, int ma)
}
static void
eth_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
eth_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
struct fs_eth *eth = opaque;
@ -564,7 +564,7 @@ static void eth_cleanup(VLANClientState *vc)
qemu_free(eth);
}
void *etraxfs_eth_init(NICInfo *nd, a_target_phys_addr base, int phyaddr)
void *etraxfs_eth_init(NICInfo *nd, target_phys_addr_t base, int phyaddr)
{
struct etraxfs_dma_client *dma = NULL;
struct fs_eth *eth = NULL;

4
hw/etraxfs_pic.c
View File

@ -77,7 +77,7 @@ static void pic_update(struct etrax_pic *fs)
qemu_set_irq(fs->parent_irq, !!vector);
}
static uint32_t pic_readl (void *opaque, a_target_phys_addr addr)
static uint32_t pic_readl (void *opaque, target_phys_addr_t addr)
{
struct etrax_pic *fs = opaque;
uint32_t rval;
@ -88,7 +88,7 @@ static uint32_t pic_readl (void *opaque, a_target_phys_addr addr)
}
static void
pic_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
struct etrax_pic *fs = opaque;
D(printf("%s addr=%x val=%x\n", __func__, addr, value));

4
hw/etraxfs_ser.c
View File

@ -65,7 +65,7 @@ static void ser_update_irq(struct etrax_serial *s)
s->regs[RW_ACK_INTR] = 0;
}
static uint32_t ser_readl (void *opaque, a_target_phys_addr addr)
static uint32_t ser_readl (void *opaque, target_phys_addr_t addr)
{
struct etrax_serial *s = opaque;
D(CPUState *env = s->env);
@ -91,7 +91,7 @@ static uint32_t ser_readl (void *opaque, a_target_phys_addr addr)
}
static void
ser_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
ser_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
struct etrax_serial *s = opaque;
unsigned char ch = value;

4
hw/etraxfs_timer.c
View File

@ -72,7 +72,7 @@ struct etrax_timer {
uint32_t r_masked_intr;
};
static uint32_t timer_readl (void *opaque, a_target_phys_addr addr)
static uint32_t timer_readl (void *opaque, target_phys_addr_t addr)
{
struct etrax_timer *t = opaque;
uint32_t r = 0;
@ -243,7 +243,7 @@ static inline void timer_watchdog_update(struct etrax_timer *t, uint32_t value)
}
static void
timer_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
struct etrax_timer *t = opaque;

344
hw/fdc.c
View File

@ -61,43 +61,43 @@
#define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
/* Floppy disk drive emulation */
typedef enum fdisk_type {
typedef enum fdisk_type_t {
FDRIVE_DISK_288 = 0x01, /* 2.88 MB disk */
FDRIVE_DISK_144 = 0x02, /* 1.44 MB disk */
FDRIVE_DISK_720 = 0x03, /* 720 kB disk */
FDRIVE_DISK_USER = 0x04, /* User defined geometry */
FDRIVE_DISK_NONE = 0x05, /* No disk */
} e_fdisk_type;
} fdisk_type_t;
typedef enum fdrive_type {
typedef enum fdrive_type_t {
FDRIVE_DRV_144 = 0x00, /* 1.44 MB 3"5 drive */
FDRIVE_DRV_288 = 0x01, /* 2.88 MB 3"5 drive */
FDRIVE_DRV_120 = 0x02, /* 1.2 MB 5"25 drive */
FDRIVE_DRV_NONE = 0x03, /* No drive connected */
} e_fdrive_type;
} fdrive_type_t;
typedef enum fdisk_flags {
typedef enum fdisk_flags_t {
FDISK_DBL_SIDES = 0x01,
} e_fdisk_flags;
} fdisk_flags_t;
typedef struct fdrive {
typedef struct fdrive_t {
BlockDriverState *bs;
/* Drive status */
e_fdrive_type drive;
fdrive_type_t drive;
uint8_t perpendicular; /* 2.88 MB access mode */
/* Position */
uint8_t head;
uint8_t track;
uint8_t sect;
/* Media */
e_fdisk_flags flags;
fdisk_flags_t flags;
uint8_t last_sect; /* Nb sector per track */
uint8_t max_track; /* Nb of tracks */
uint16_t bps; /* Bytes per sector */
uint8_t ro; /* Is read-only */
} a_fdrive;
} fdrive_t;
static void fd_init (a_fdrive *drv, BlockDriverState *bs)
static void fd_init (fdrive_t *drv, BlockDriverState *bs)
{
/* Drive */
drv->bs = bs;
@ -115,7 +115,7 @@ static int _fd_sector (uint8_t head, uint8_t track,
}
/* Returns current position, in sectors, for given drive */
static int fd_sector (a_fdrive *drv)
static int fd_sector (fdrive_t *drv)
{
return _fd_sector(drv->head, drv->track, drv->sect, drv->last_sect);
}
@ -127,7 +127,7 @@ static int fd_sector (a_fdrive *drv)
* returns 3 if sector is invalid
* returns 4 if seek is disabled
*/
static int fd_seek (a_fdrive *drv, uint8_t head, uint8_t track, uint8_t sect,
static int fd_seek (fdrive_t *drv, uint8_t head, uint8_t track, uint8_t sect,
int enable_seek)
{
uint32_t sector;
@ -169,7 +169,7 @@ static int fd_seek (a_fdrive *drv, uint8_t head, uint8_t track, uint8_t sect,
}
/* Set drive back to track 0 */
static void fd_recalibrate (a_fdrive *drv)
static void fd_recalibrate (fdrive_t *drv)
{
FLOPPY_DPRINTF("recalibrate\n");
drv->head = 0;
@ -178,16 +178,16 @@ static void fd_recalibrate (a_fdrive *drv)
}
/* Recognize floppy formats */
typedef struct fd_format {
e_fdrive_type drive;
e_fdisk_type disk;
typedef struct fd_format_t {
fdrive_type_t drive;
fdisk_type_t disk;
uint8_t last_sect;
uint8_t max_track;
uint8_t max_head;
const char *str;
} a_fd_format;
} fd_format_t;
static const a_fd_format fd_formats[] = {
static const fd_format_t fd_formats[] = {
/* First entry is default format */
/* 1.44 MB 3"1/2 floppy disks */
{ FDRIVE_DRV_144, FDRIVE_DISK_144, 18, 80, 1, "1.44 MB 3\"1/2", },
@ -235,9 +235,9 @@ static const a_fd_format fd_formats[] = {
};
/* Revalidate a disk drive after a disk change */
static void fd_revalidate (a_fdrive *drv)
static void fd_revalidate (fdrive_t *drv)
{
const a_fd_format *parse;
const fd_format_t *parse;
uint64_t nb_sectors, size;
int i, first_match, match;
int nb_heads, max_track, last_sect, ro;
@ -302,23 +302,23 @@ static void fd_revalidate (a_fdrive *drv)
/********************************************************/
/* Intel 82078 floppy disk controller emulation */
static void fdctrl_reset (a_fdctrl *fdctrl, int do_irq);
static void fdctrl_reset_fifo (a_fdctrl *fdctrl);
static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq);
static void fdctrl_reset_fifo (fdctrl_t *fdctrl);
static int fdctrl_transfer_handler (void *opaque, int nchan,
int dma_pos, int dma_len);
static void fdctrl_raise_irq (a_fdctrl *fdctrl, uint8_t status0);
int dma_pos, int dma_len);
static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0);
static uint32_t fdctrl_read_statusA (a_fdctrl *fdctrl);
static uint32_t fdctrl_read_statusB (a_fdctrl *fdctrl);
static uint32_t fdctrl_read_dor (a_fdctrl *fdctrl);
static void fdctrl_write_dor (a_fdctrl *fdctrl, uint32_t value);
static uint32_t fdctrl_read_tape (a_fdctrl *fdctrl);
static void fdctrl_write_tape (a_fdctrl *fdctrl, uint32_t value);
static uint32_t fdctrl_read_main_status (a_fdctrl *fdctrl);
static void fdctrl_write_rate (a_fdctrl *fdctrl, uint32_t value);
static uint32_t fdctrl_read_data (a_fdctrl *fdctrl);
static void fdctrl_write_data (a_fdctrl *fdctrl, uint32_t value);
static uint32_t fdctrl_read_dir (a_fdctrl *fdctrl);
static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl);
static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl);
static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl);
static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value);
static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl);
static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value);
static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl);
static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value);
static uint32_t fdctrl_read_data (fdctrl_t *fdctrl);
static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value);
static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl);
enum {
FD_DIR_WRITE = 0,
@ -470,7 +470,7 @@ enum {
#define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
#define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
struct fdctrl {
struct fdctrl_t {
/* Controller's identification */
uint8_t version;
/* HW */
@ -511,23 +511,23 @@ struct fdctrl {
int sun4m;
/* Floppy drives */
uint8_t num_floppies;
a_fdrive drives[MAX_FD];
fdrive_t drives[MAX_FD];
int reset_sensei;
};
typedef struct fdctrl_sysbus {
typedef struct fdctrl_sysbus_t {
SysBusDevice busdev;
struct fdctrl state;
} a_fdctrl_sysbus;
struct fdctrl_t state;
} fdctrl_sysbus_t;
typedef struct fdctrl_isabus {
typedef struct fdctrl_isabus_t {
ISADevice busdev;
struct fdctrl state;
} a_fdctrl_isabus;
struct fdctrl_t state;
} fdctrl_isabus_t;
static uint32_t fdctrl_read (void *opaque, uint32_t reg)
{
a_fdctrl *fdctrl = opaque;
fdctrl_t *fdctrl = opaque;
uint32_t retval;
switch (reg) {
@ -563,7 +563,7 @@ static uint32_t fdctrl_read (void *opaque, uint32_t reg)
static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
{
a_fdctrl *fdctrl = opaque;
fdctrl_t *fdctrl = opaque;
FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
@ -595,13 +595,13 @@ static void fdctrl_write_port (void *opaque, uint32_t reg, uint32_t value)
fdctrl_write(opaque, reg & 7, value);
}
static uint32_t fdctrl_read_mem (void *opaque, a_target_phys_addr reg)
static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)
{
return fdctrl_read(opaque, (uint32_t)reg);
}
static void fdctrl_write_mem (void *opaque,
a_target_phys_addr reg, uint32_t value)
target_phys_addr_t reg, uint32_t value)
{
fdctrl_write(opaque, (uint32_t)reg, value);
}
@ -636,23 +636,23 @@ static const VMStateDescription vmstate_fdrive = {
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField []) {
VMSTATE_UINT8(head, a_fdrive),
VMSTATE_UINT8(track, a_fdrive),
VMSTATE_UINT8(sect, a_fdrive),
VMSTATE_UINT8(head, fdrive_t),
VMSTATE_UINT8(track, fdrive_t),
VMSTATE_UINT8(sect, fdrive_t),
VMSTATE_END_OF_LIST()
}
};
static void fdc_pre_save(const void *opaque)
{
a_fdctrl *s = (void *)opaque;
fdctrl_t *s = (void *)opaque;
s->dor_vmstate = s->dor | GET_CUR_DRV(s);
}
static int fdc_post_load(void *opaque)
{
a_fdctrl *s = opaque;
fdctrl_t *s = opaque;
SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
@ -668,46 +668,46 @@ static const VMStateDescription vmstate_fdc = {
.post_load = fdc_post_load,
.fields = (VMStateField []) {
/* Controller State */
VMSTATE_UINT8(sra, a_fdctrl),
VMSTATE_UINT8(srb, a_fdctrl),
VMSTATE_UINT8(dor_vmstate, a_fdctrl),
VMSTATE_UINT8(tdr, a_fdctrl),
VMSTATE_UINT8(dsr, a_fdctrl),
VMSTATE_UINT8(msr, a_fdctrl),
VMSTATE_UINT8(status0, a_fdctrl),
VMSTATE_UINT8(status1, a_fdctrl),
VMSTATE_UINT8(status2, a_fdctrl),
VMSTATE_UINT8(sra, fdctrl_t),
VMSTATE_UINT8(srb, fdctrl_t),
VMSTATE_UINT8(dor_vmstate, fdctrl_t),
VMSTATE_UINT8(tdr, fdctrl_t),
VMSTATE_UINT8(dsr, fdctrl_t),
VMSTATE_UINT8(msr, fdctrl_t),
VMSTATE_UINT8(status0, fdctrl_t),
VMSTATE_UINT8(status1, fdctrl_t),
VMSTATE_UINT8(status2, fdctrl_t),
/* Command FIFO */
VMSTATE_VARRAY(fifo, a_fdctrl, fifo_size, 0, vmstate_info_uint8, uint8),
VMSTATE_UINT32(data_pos, a_fdctrl),
VMSTATE_UINT32(data_len, a_fdctrl),
VMSTATE_UINT8(data_state, a_fdctrl),
VMSTATE_UINT8(data_dir, a_fdctrl),
VMSTATE_UINT8(eot, a_fdctrl),
VMSTATE_VARRAY(fifo, fdctrl_t, fifo_size, 0, vmstate_info_uint8, uint8),
VMSTATE_UINT32(data_pos, fdctrl_t),
VMSTATE_UINT32(data_len, fdctrl_t),
VMSTATE_UINT8(data_state, fdctrl_t),
VMSTATE_UINT8(data_dir, fdctrl_t),
VMSTATE_UINT8(eot, fdctrl_t),
/* States kept only to be returned back */
VMSTATE_UINT8(timer0, a_fdctrl),
VMSTATE_UINT8(timer1, a_fdctrl),
VMSTATE_UINT8(precomp_trk, a_fdctrl),
VMSTATE_UINT8(config, a_fdctrl),
VMSTATE_UINT8(lock, a_fdctrl),
VMSTATE_UINT8(pwrd, a_fdctrl),
VMSTATE_UINT8_EQUAL(num_floppies, a_fdctrl),
VMSTATE_STRUCT_ARRAY(drives, a_fdctrl, MAX_FD, 1,
vmstate_fdrive, a_fdrive),
VMSTATE_UINT8(timer0, fdctrl_t),
VMSTATE_UINT8(timer1, fdctrl_t),
VMSTATE_UINT8(precomp_trk, fdctrl_t),
VMSTATE_UINT8(config, fdctrl_t),
VMSTATE_UINT8(lock, fdctrl_t),
VMSTATE_UINT8(pwrd, fdctrl_t),
VMSTATE_UINT8_EQUAL(num_floppies, fdctrl_t),
VMSTATE_STRUCT_ARRAY(drives, fdctrl_t, MAX_FD, 1,
vmstate_fdrive, fdrive_t),
VMSTATE_END_OF_LIST()
}
};
static void fdctrl_external_reset(void *opaque)
{
a_fdctrl *s = opaque;
fdctrl_t *s = opaque;
fdctrl_reset(s, 0);
}
static void fdctrl_handle_tc(void *opaque, int irq, int level)
{
//a_fdctrl *s = opaque;
//fdctrl_t *s = opaque;
if (level) {
// XXX
@ -716,13 +716,13 @@ static void fdctrl_handle_tc(void *opaque, int irq, int level)
}
/* XXX: may change if moved to bdrv */
int fdctrl_get_drive_type(a_fdctrl *fdctrl, int drive_num)
int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num)
{
return fdctrl->drives[drive_num].drive;
}
/* Change IRQ state */
static void fdctrl_reset_irq (a_fdctrl *fdctrl)
static void fdctrl_reset_irq (fdctrl_t *fdctrl)
{
if (!(fdctrl->sra & FD_SRA_INTPEND))
return;
@ -731,7 +731,7 @@ static void fdctrl_reset_irq (a_fdctrl *fdctrl)
fdctrl->sra &= ~FD_SRA_INTPEND;
}
static void fdctrl_raise_irq (a_fdctrl *fdctrl, uint8_t status0)
static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0)
{
/* Sparc mutation */
if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
@ -751,7 +751,7 @@ static void fdctrl_raise_irq (a_fdctrl *fdctrl, uint8_t status0)
}
/* Reset controller */
static void fdctrl_reset (a_fdctrl *fdctrl, int do_irq)
static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq)
{
int i;
@ -780,12 +780,12 @@ static void fdctrl_reset (a_fdctrl *fdctrl, int do_irq)
}
}
static inline a_fdrive *drv0 (a_fdctrl *fdctrl)
static inline fdrive_t *drv0 (fdctrl_t *fdctrl)
{
return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
}
static inline a_fdrive *drv1 (a_fdctrl *fdctrl)
static inline fdrive_t *drv1 (fdctrl_t *fdctrl)
{
if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
return &fdctrl->drives[1];
@ -794,7 +794,7 @@ static inline a_fdrive *drv1 (a_fdctrl *fdctrl)
}
#if MAX_FD == 4
static inline a_fdrive *drv2 (a_fdctrl *fdctrl)
static inline fdrive_t *drv2 (fdctrl_t *fdctrl)
{
if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
return &fdctrl->drives[2];
@ -802,7 +802,7 @@ static inline a_fdrive *drv2 (a_fdctrl *fdctrl)
return &fdctrl->drives[1];
}
static inline a_fdrive *drv3 (a_fdctrl *fdctrl)
static inline fdrive_t *drv3 (fdctrl_t *fdctrl)
{
if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
return &fdctrl->drives[3];
@ -811,7 +811,7 @@ static inline a_fdrive *drv3 (a_fdctrl *fdctrl)
}
#endif
static a_fdrive *get_cur_drv (a_fdctrl *fdctrl)
static fdrive_t *get_cur_drv (fdctrl_t *fdctrl)
{
switch (fdctrl->cur_drv) {
case 0: return drv0(fdctrl);
@ -825,7 +825,7 @@ static a_fdrive *get_cur_drv (a_fdctrl *fdctrl)
}
/* Status A register : 0x00 (read-only) */
static uint32_t fdctrl_read_statusA (a_fdctrl *fdctrl)
static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl)
{
uint32_t retval = fdctrl->sra;
@ -835,7 +835,7 @@ static uint32_t fdctrl_read_statusA (a_fdctrl *fdctrl)
}
/* Status B register : 0x01 (read-only) */
static uint32_t fdctrl_read_statusB (a_fdctrl *fdctrl)
static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl)
{
uint32_t retval = fdctrl->srb;
@ -845,7 +845,7 @@ static uint32_t fdctrl_read_statusB (a_fdctrl *fdctrl)
}
/* Digital output register : 0x02 */
static uint32_t fdctrl_read_dor (a_fdctrl *fdctrl)
static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl)
{
uint32_t retval = fdctrl->dor;
@ -856,7 +856,7 @@ static uint32_t fdctrl_read_dor (a_fdctrl *fdctrl)
return retval;
}
static void fdctrl_write_dor (a_fdctrl *fdctrl, uint32_t value)
static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value)
{
FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
@ -895,7 +895,7 @@ static void fdctrl_write_dor (a_fdctrl *fdctrl, uint32_t value)
}
/* Tape drive register : 0x03 */
static uint32_t fdctrl_read_tape (a_fdctrl *fdctrl)
static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl)
{
uint32_t retval = fdctrl->tdr;
@ -904,7 +904,7 @@ static uint32_t fdctrl_read_tape (a_fdctrl *fdctrl)
return retval;
}
static void fdctrl_write_tape (a_fdctrl *fdctrl, uint32_t value)
static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value)
{
/* Reset mode */
if (!(fdctrl->dor & FD_DOR_nRESET)) {
@ -918,7 +918,7 @@ static void fdctrl_write_tape (a_fdctrl *fdctrl, uint32_t value)
}
/* Main status register : 0x04 (read) */
static uint32_t fdctrl_read_main_status (a_fdctrl *fdctrl)
static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl)
{
uint32_t retval = fdctrl->msr;
@ -931,7 +931,7 @@ static uint32_t fdctrl_read_main_status (a_fdctrl *fdctrl)
}
/* Data select rate register : 0x04 (write) */
static void fdctrl_write_rate (a_fdctrl *fdctrl, uint32_t value)
static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value)
{
/* Reset mode */
if (!(fdctrl->dor & FD_DOR_nRESET)) {
@ -951,7 +951,7 @@ static void fdctrl_write_rate (a_fdctrl *fdctrl, uint32_t value)
fdctrl->dsr = value;
}
static int fdctrl_media_changed(a_fdrive *drv)
static int fdctrl_media_changed(fdrive_t *drv)
{
int ret;
@ -965,7 +965,7 @@ static int fdctrl_media_changed(a_fdrive *drv)
}
/* Digital input register : 0x07 (read-only) */
static uint32_t fdctrl_read_dir (a_fdctrl *fdctrl)
static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl)
{
uint32_t retval = 0;
@ -984,7 +984,7 @@ static uint32_t fdctrl_read_dir (a_fdctrl *fdctrl)
}
/* FIFO state control */
static void fdctrl_reset_fifo (a_fdctrl *fdctrl)
static void fdctrl_reset_fifo (fdctrl_t *fdctrl)
{
fdctrl->data_dir = FD_DIR_WRITE;
fdctrl->data_pos = 0;
@ -992,7 +992,7 @@ static void fdctrl_reset_fifo (a_fdctrl *fdctrl)
}
/* Set FIFO status for the host to read */
static void fdctrl_set_fifo (a_fdctrl *fdctrl, int fifo_len, int do_irq)
static void fdctrl_set_fifo (fdctrl_t *fdctrl, int fifo_len, int do_irq)
{
fdctrl->data_dir = FD_DIR_READ;
fdctrl->data_len = fifo_len;
@ -1003,7 +1003,7 @@ static void fdctrl_set_fifo (a_fdctrl *fdctrl, int fifo_len, int do_irq)
}
/* Set an error: unimplemented/unknown command */
static void fdctrl_unimplemented (a_fdctrl *fdctrl, int direction)
static void fdctrl_unimplemented (fdctrl_t *fdctrl, int direction)
{
FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]);
fdctrl->fifo[0] = FD_SR0_INVCMD;
@ -1011,7 +1011,7 @@ static void fdctrl_unimplemented (a_fdctrl *fdctrl, int direction)
}
/* Seek to next sector */
static int fdctrl_seek_to_next_sect (a_fdctrl *fdctrl, a_fdrive *cur_drv)
static int fdctrl_seek_to_next_sect (fdctrl_t *fdctrl, fdrive_t *cur_drv)
{
FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
cur_drv->head, cur_drv->track, cur_drv->sect,
@ -1045,10 +1045,10 @@ static int fdctrl_seek_to_next_sect (a_fdctrl *fdctrl, a_fdrive *cur_drv)
}
/* Callback for transfer end (stop or abort) */
static void fdctrl_stop_transfer (a_fdctrl *fdctrl, uint8_t status0,
static void fdctrl_stop_transfer (fdctrl_t *fdctrl, uint8_t status0,
uint8_t status1, uint8_t status2)
{
a_fdrive *cur_drv;
fdrive_t *cur_drv;
cur_drv = get_cur_drv(fdctrl);
FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
@ -1071,9 +1071,9 @@ static void fdctrl_stop_transfer (a_fdctrl *fdctrl, uint8_t status0,
}
/* Prepare a data transfer (either DMA or FIFO) */
static void fdctrl_start_transfer (a_fdctrl *fdctrl, int direction)
static void fdctrl_start_transfer (fdctrl_t *fdctrl, int direction)
{
a_fdrive *cur_drv;
fdrive_t *cur_drv;
uint8_t kh, kt, ks;
int did_seek = 0;
@ -1173,7 +1173,7 @@ static void fdctrl_start_transfer (a_fdctrl *fdctrl, int direction)
}
/* Prepare a transfer of deleted data */
static void fdctrl_start_transfer_del (a_fdctrl *fdctrl, int direction)
static void fdctrl_start_transfer_del (fdctrl_t *fdctrl, int direction)
{
FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n");
@ -1187,8 +1187,8 @@ static void fdctrl_start_transfer_del (a_fdctrl *fdctrl, int direction)
static int fdctrl_transfer_handler (void *opaque, int nchan,
int dma_pos, int dma_len)
{
a_fdctrl *fdctrl;
a_fdrive *cur_drv;
fdctrl_t *fdctrl;
fdrive_t *cur_drv;
int len, start_pos, rel_pos;
uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
@ -1294,9 +1294,9 @@ static int fdctrl_transfer_handler (void *opaque, int nchan,
}
/* Data register : 0x05 */
static uint32_t fdctrl_read_data (a_fdctrl *fdctrl)
static uint32_t fdctrl_read_data (fdctrl_t *fdctrl)
{
a_fdrive *cur_drv;
fdrive_t *cur_drv;
uint32_t retval = 0;
int pos;
@ -1342,9 +1342,9 @@ static uint32_t fdctrl_read_data (a_fdctrl *fdctrl)
return retval;
}
static void fdctrl_format_sector (a_fdctrl *fdctrl)
static void fdctrl_format_sector (fdctrl_t *fdctrl)
{
a_fdrive *cur_drv;
fdrive_t *cur_drv;
uint8_t kh, kt, ks;
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
@ -1404,16 +1404,16 @@ static void fdctrl_format_sector (a_fdctrl *fdctrl)
}
}
static void fdctrl_handle_lock (a_fdctrl *fdctrl, int direction)
static void fdctrl_handle_lock (fdctrl_t *fdctrl, int direction)
{
fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
fdctrl->fifo[0] = fdctrl->lock << 4;
fdctrl_set_fifo(fdctrl, 1, fdctrl->lock);
}
static void fdctrl_handle_dumpreg (a_fdctrl *fdctrl, int direction)
static void fdctrl_handle_dumpreg (fdctrl_t *fdctrl, int direction)
{
a_fdrive *cur_drv = get_cur_drv(fdctrl);
fdrive_t *cur_drv = get_cur_drv(fdctrl);
/* Drives position */
fdctrl->fifo[0] = drv0(fdctrl)->track;
@ -1436,22 +1436,22 @@ static void fdctrl_handle_dumpreg (a_fdctrl *fdctrl, int direction)
fdctrl_set_fifo(fdctrl, 10, 0);
}
static void fdctrl_handle_version (a_fdctrl *fdctrl, int direction)
static void fdctrl_handle_version (fdctrl_t *fdctrl, int direction)
{
/* Controller's version */
fdctrl->fifo[0] = fdctrl->version;
fdctrl_set_fifo(fdctrl, 1, 1);
}
static void fdctrl_handle_partid (a_fdctrl *fdctrl, int direction)
static void fdctrl_handle_partid (fdctrl_t *fdctrl, int direction)
{
fdctrl->fifo[0] = 0x41; /* Stepping 1 */
fdctrl_set_fifo(fdctrl, 1, 0);
}
static void fdctrl_handle_restore (a_fdctrl *fdctrl, int direction)
static void fdctrl_handle_restore (fdctrl_t *fdctrl, int direction)
{
a_fdrive *cur_drv = get_cur_drv(fdctrl);
fdrive_t *cur_drv = get_cur_drv(fdctrl);
/* Drives position */
drv0(fdctrl)->track = fdctrl->fifo[3];
@ -1472,9 +1472,9 @@ static void fdctrl_handle_restore (a_fdctrl *fdctrl, int direction)
fdctrl_reset_fifo(fdctrl);
}
static void fdctrl_handle_save (a_fdctrl *fdctrl, int direction)
static void fdctrl_handle_save (fdctrl_t *fdctrl, int direction)
{
a_fdrive *cur_drv = get_cur_drv(fdctrl);
fdrive_t *cur_drv = get_cur_drv(fdctrl);
fdctrl->fifo[0] = 0;
fdctrl->fifo[1] = 0;
@ -1502,9 +1502,9 @@ static void fdctrl_handle_save (a_fdctrl *fdctrl, int direction)
fdctrl_set_fifo(fdctrl, 15, 1);
}
static void fdctrl_handle_readid (a_fdctrl *fdctrl, int direction)
static void fdctrl_handle_readid (fdctrl_t *fdctrl, int direction)
{
a_fdrive *cur_drv = get_cur_drv(fdctrl);
fdrive_t *cur_drv = get_cur_drv(fdctrl);
/* XXX: should set main status register to busy */
cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
@ -1512,9 +1512,9 @@ static void fdctrl_handle_readid (a_fdctrl *fdctrl, int direction)
qemu_get_clock(vm_clock) + (get_ticks_per_sec() / 50));
}
static void fdctrl_handle_format_track (a_fdctrl *fdctrl, int direction)
static void fdctrl_handle_format_track (fdctrl_t *fdctrl, int direction)
{
a_fdrive *cur_drv;
fdrive_t *cur_drv;
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
@ -1541,7 +1541,7 @@ static void fdctrl_handle_format_track (a_fdctrl *fdctrl, int direction)
fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
}
static void fdctrl_handle_specify (a_fdctrl *fdctrl, int direction)
static void fdctrl_handle_specify (fdctrl_t *fdctrl, int direction)
{
fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
fdctrl->timer1 = fdctrl->fifo[2] >> 1;
@ -1553,9 +1553,9 @@ static void fdctrl_handle_specify (a_fdctrl *fdctrl, int direction)
fdctrl_reset_fifo(fdctrl);
}
static void fdctrl_handle_sense_drive_status (a_fdctrl *fdctrl, int direction)
static void fdctrl_handle_sense_drive_status (fdctrl_t *fdctrl, int direction)
{
a_fdrive *cur_drv;
fdrive_t *cur_drv;
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
@ -1569,9 +1569,9 @@ static void fdctrl_handle_sense_drive_status (a_fdctrl *fdctrl, int direction)
fdctrl_set_fifo(fdctrl, 1, 0);
}
static void fdctrl_handle_recalibrate (a_fdctrl *fdctrl, int direction)
static void fdctrl_handle_recalibrate (fdctrl_t *fdctrl, int direction)
{
a_fdrive *cur_drv;
fdrive_t *cur_drv;
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
@ -1581,9 +1581,9 @@ static void fdctrl_handle_recalibrate (a_fdctrl *fdctrl, int direction)
fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
}
static void fdctrl_handle_sense_interrupt_status (a_fdctrl *fdctrl, int direction)
static void fdctrl_handle_sense_interrupt_status (fdctrl_t *fdctrl, int direction)
{
a_fdrive *cur_drv = get_cur_drv(fdctrl);
fdrive_t *cur_drv = get_cur_drv(fdctrl);
if(fdctrl->reset_sensei > 0) {
fdctrl->fifo[0] =
@ -1603,9 +1603,9 @@ static void fdctrl_handle_sense_interrupt_status (a_fdctrl *fdctrl, int directio
fdctrl->status0 = FD_SR0_RDYCHG;
}
static void fdctrl_handle_seek (a_fdctrl *fdctrl, int direction)
static void fdctrl_handle_seek (fdctrl_t *fdctrl, int direction)
{
a_fdrive *cur_drv;
fdrive_t *cur_drv;
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
@ -1619,9 +1619,9 @@ static void fdctrl_handle_seek (a_fdctrl *fdctrl, int direction)
}
}
static void fdctrl_handle_perpendicular_mode (a_fdctrl *fdctrl, int direction)
static void fdctrl_handle_perpendicular_mode (fdctrl_t *fdctrl, int direction)
{
a_fdrive *cur_drv = get_cur_drv(fdctrl);
fdrive_t *cur_drv = get_cur_drv(fdctrl);
if (fdctrl->fifo[1] & 0x80)
cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
@ -1629,7 +1629,7 @@ static void fdctrl_handle_perpendicular_mode (a_fdctrl *fdctrl, int direction)
fdctrl_reset_fifo(fdctrl);
}
static void fdctrl_handle_configure (a_fdctrl *fdctrl, int direction)
static void fdctrl_handle_configure (fdctrl_t *fdctrl, int direction)
{
fdctrl->config = fdctrl->fifo[2];
fdctrl->precomp_trk = fdctrl->fifo[3];
@ -1637,22 +1637,22 @@ static void fdctrl_handle_configure (a_fdctrl *fdctrl, int direction)
fdctrl_reset_fifo(fdctrl);
}
static void fdctrl_handle_powerdown_mode (a_fdctrl *fdctrl, int direction)
static void fdctrl_handle_powerdown_mode (fdctrl_t *fdctrl, int direction)
{
fdctrl->pwrd = fdctrl->fifo[1];
fdctrl->fifo[0] = fdctrl->fifo[1];
fdctrl_set_fifo(fdctrl, 1, 1);
}
static void fdctrl_handle_option (a_fdctrl *fdctrl, int direction)
static void fdctrl_handle_option (fdctrl_t *fdctrl, int direction)
{
/* No result back */
fdctrl_reset_fifo(fdctrl);
}
static void fdctrl_handle_drive_specification_command (a_fdctrl *fdctrl, int direction)
static void fdctrl_handle_drive_specification_command (fdctrl_t *fdctrl, int direction)
{
a_fdrive *cur_drv = get_cur_drv(fdctrl);
fdrive_t *cur_drv = get_cur_drv(fdctrl);
if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
/* Command parameters done */
@ -1672,9 +1672,9 @@ static void fdctrl_handle_drive_specification_command (a_fdctrl *fdctrl, int dir
}
}
static void fdctrl_handle_relative_seek_out (a_fdctrl *fdctrl, int direction)
static void fdctrl_handle_relative_seek_out (fdctrl_t *fdctrl, int direction)
{
a_fdrive *cur_drv;
fdrive_t *cur_drv;
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
@ -1688,9 +1688,9 @@ static void fdctrl_handle_relative_seek_out (a_fdctrl *fdctrl, int direction)
fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
}
static void fdctrl_handle_relative_seek_in (a_fdctrl *fdctrl, int direction)
static void fdctrl_handle_relative_seek_in (fdctrl_t *fdctrl, int direction)
{
a_fdrive *cur_drv;
fdrive_t *cur_drv;
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
@ -1709,7 +1709,7 @@ static const struct {
uint8_t mask;
const char* name;
int parameters;
void (*handler)(a_fdctrl *fdctrl, int direction);
void (*handler)(fdctrl_t *fdctrl, int direction);
int direction;
} handlers[] = {
{ FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
@ -1748,9 +1748,9 @@ static const struct {
/* Associate command to an index in the 'handlers' array */
static uint8_t command_to_handler[256];
static void fdctrl_write_data (a_fdctrl *fdctrl, uint32_t value)
static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value)
{
a_fdrive *cur_drv;
fdrive_t *cur_drv;
int pos;
/* Reset mode */
@ -1815,8 +1815,8 @@ static void fdctrl_write_data (a_fdctrl *fdctrl, uint32_t value)
static void fdctrl_result_timer(void *opaque)
{
a_fdctrl *fdctrl = opaque;
a_fdrive *cur_drv = get_cur_drv(fdctrl);
fdctrl_t *fdctrl = opaque;
fdrive_t *cur_drv = get_cur_drv(fdctrl);
/* Pretend we are spinning.
* This is needed for Coherent, which uses READ ID to check for
@ -1829,7 +1829,7 @@ static void fdctrl_result_timer(void *opaque)
}
/* Init functions */
static void fdctrl_connect_drives(a_fdctrl *fdctrl, BlockDriverState **fds)
static void fdctrl_connect_drives(fdctrl_t *fdctrl, BlockDriverState **fds)
{
unsigned int i;
@ -1839,14 +1839,14 @@ static void fdctrl_connect_drives(a_fdctrl *fdctrl, BlockDriverState **fds)
}
}
a_fdctrl *fdctrl_init_isa(BlockDriverState **fds)
fdctrl_t *fdctrl_init_isa(BlockDriverState **fds)
{
a_fdctrl *fdctrl;
fdctrl_t *fdctrl;
ISADevice *dev;
int dma_chann = 2;
dev = isa_create_simple("isa-fdc");
fdctrl = &(DO_UPCAST(a_fdctrl_isabus, busdev, dev)->state);
fdctrl = &(DO_UPCAST(fdctrl_isabus_t, busdev, dev)->state);
fdctrl->dma_chann = dma_chann;
DMA_register_channel(dma_chann, &fdctrl_transfer_handler, fdctrl);
@ -1856,17 +1856,17 @@ a_fdctrl *fdctrl_init_isa(BlockDriverState **fds)
return fdctrl;
}
a_fdctrl *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
a_target_phys_addr mmio_base,
fdctrl_t *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
target_phys_addr_t mmio_base,
BlockDriverState **fds)
{
a_fdctrl *fdctrl;
fdctrl_t *fdctrl;
DeviceState *dev;
a_fdctrl_sysbus *sys;
fdctrl_sysbus_t *sys;
dev = qdev_create(NULL, "sysbus-fdc");
qdev_init(dev);
sys = DO_UPCAST(a_fdctrl_sysbus, busdev.qdev, dev);
sys = DO_UPCAST(fdctrl_sysbus_t, busdev.qdev, dev);
fdctrl = &sys->state;
sysbus_connect_irq(&sys->busdev, 0, irq);
sysbus_mmio_map(&sys->busdev, 0, mmio_base);
@ -1878,16 +1878,16 @@ a_fdctrl *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
return fdctrl;
}
a_fdctrl *sun4m_fdctrl_init (qemu_irq irq, a_target_phys_addr io_base,
fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
BlockDriverState **fds, qemu_irq *fdc_tc)
{
DeviceState *dev;
a_fdctrl_sysbus *sys;
a_fdctrl *fdctrl;
fdctrl_sysbus_t *sys;
fdctrl_t *fdctrl;
dev = qdev_create(NULL, "SUNW,fdtwo");
qdev_init(dev);
sys = DO_UPCAST(a_fdctrl_sysbus, busdev.qdev, dev);
sys = DO_UPCAST(fdctrl_sysbus_t, busdev.qdev, dev);
fdctrl = &sys->state;
sysbus_connect_irq(&sys->busdev, 0, irq);
sysbus_mmio_map(&sys->busdev, 0, io_base);
@ -1900,7 +1900,7 @@ a_fdctrl *sun4m_fdctrl_init (qemu_irq irq, a_target_phys_addr io_base,
return fdctrl;
}
static int fdctrl_init_common(a_fdctrl *fdctrl)
static int fdctrl_init_common(fdctrl_t *fdctrl)
{
int i, j;
static int command_tables_inited = 0;
@ -1935,8 +1935,8 @@ static int fdctrl_init_common(a_fdctrl *fdctrl)
static int isabus_fdc_init1(ISADevice *dev)
{
a_fdctrl_isabus *isa = DO_UPCAST(a_fdctrl_isabus, busdev, dev);
a_fdctrl *fdctrl = &isa->state;
fdctrl_isabus_t *isa = DO_UPCAST(fdctrl_isabus_t, busdev, dev);
fdctrl_t *fdctrl = &isa->state;
int iobase = 0x3f0;
int isairq = 6;
@ -1955,7 +1955,7 @@ static int isabus_fdc_init1(ISADevice *dev)
static int sysbus_fdc_init1(SysBusDevice *dev)
{
a_fdctrl *fdctrl = &(FROM_SYSBUS(a_fdctrl_sysbus, dev)->state);
fdctrl_t *fdctrl = &(FROM_SYSBUS(fdctrl_sysbus_t, dev)->state);
int io;
io = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write, fdctrl);
@ -1968,7 +1968,7 @@ static int sysbus_fdc_init1(SysBusDevice *dev)
static int sun4m_fdc_init1(SysBusDevice *dev)
{
a_fdctrl *fdctrl = &(FROM_SYSBUS(a_fdctrl_sysbus, dev)->state);
fdctrl_t *fdctrl = &(FROM_SYSBUS(fdctrl_sysbus_t, dev)->state);
int io;
io = cpu_register_io_memory(fdctrl_mem_read_strict,
@ -1984,19 +1984,19 @@ static int sun4m_fdc_init1(SysBusDevice *dev)
static ISADeviceInfo isa_fdc_info = {
.init = isabus_fdc_init1,
.qdev.name = "isa-fdc",
.qdev.size = sizeof(a_fdctrl_isabus),
.qdev.size = sizeof(fdctrl_isabus_t),
};
static SysBusDeviceInfo sysbus_fdc_info = {
.init = sysbus_fdc_init1,
.qdev.name = "sysbus-fdc",
.qdev.size = sizeof(a_fdctrl_sysbus),
.qdev.size = sizeof(fdctrl_sysbus_t),
};
static SysBusDeviceInfo sun4m_fdc_info = {
.init = sun4m_fdc_init1,
.qdev.name = "SUNW,fdtwo",
.qdev.size = sizeof(a_fdctrl_sysbus),
.qdev.size = sizeof(fdctrl_sysbus_t),
};
static void fdc_register_devices(void)

12
hw/fdc.h
View File

@ -1,12 +1,12 @@
/* fdc.c */
#define MAX_FD 2
typedef struct fdctrl a_fdctrl;
typedef struct fdctrl_t fdctrl_t;
a_fdctrl *fdctrl_init_isa(BlockDriverState **fds);
a_fdctrl *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
a_target_phys_addr mmio_base,
fdctrl_t *fdctrl_init_isa(BlockDriverState **fds);
fdctrl_t *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
target_phys_addr_t mmio_base,
BlockDriverState **fds);
a_fdctrl *sun4m_fdctrl_init (qemu_irq irq, a_target_phys_addr io_base,
fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
BlockDriverState **fds, qemu_irq *fdc_tc);
int fdctrl_get_drive_type(a_fdctrl *fdctrl, int drive_num);
int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);

8
hw/flash.h
View File

@ -1,15 +1,15 @@
/* NOR flash devices */
typedef struct pflash a_pflash;
typedef struct pflash_t pflash_t;
/* pflash_cfi01.c */
a_pflash *pflash_cfi01_register(a_target_phys_addr base, a_ram_addr off,
pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off,
BlockDriverState *bs,
uint32_t sector_len, int nb_blocs, int width,
uint16_t id0, uint16_t id1,
uint16_t id2, uint16_t id3);
/* pflash_cfi02.c */
a_pflash *pflash_cfi02_register(a_target_phys_addr base, a_ram_addr off,
pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
BlockDriverState *bs, uint32_t sector_len,
int nb_blocs, int nb_mappings, int width,
uint16_t id0, uint16_t id1,
@ -36,7 +36,7 @@ uint8_t nand_getio(NANDFlashState *s);
#define NAND_MFR_MICRON 0x2c
/* onenand.c */
void onenand_base_update(void *opaque, a_target_phys_addr new);
void onenand_base_update(void *opaque, target_phys_addr_t new);
void onenand_base_unmap(void *opaque);
void *onenand_init(uint32_t id, int regshift, qemu_irq irq);
void *onenand_raw_otp(void *opaque);

12
hw/framebuffer.c
View File

@ -22,7 +22,7 @@
void framebuffer_update_display(
DisplayState *ds,
a_target_phys_addr base,
target_phys_addr_t base,
int cols, /* Width in pixels. */
int rows, /* Leight in pixels. */
int src_width, /* Length of source line, in bytes. */
@ -34,16 +34,16 @@ void framebuffer_update_display(
int *first_row, /* Input and output. */
int *last_row /* Output only */)
{
a_target_phys_addr src_len;
target_phys_addr_t src_len;
uint8_t *dest;
uint8_t *src;
uint8_t *src_base;
int first, last = 0;
int dirty;
int i;
a_ram_addr addr;
a_ram_addr pd;
a_ram_addr pd2;
ram_addr_t addr;
ram_addr_t pd;
ram_addr_t pd2;
i = *first_row;
*first_row = -1;
@ -86,7 +86,7 @@ void framebuffer_update_display(
dest += i * dest_row_pitch;
for (; i < rows; i++) {
a_target_phys_addr dirty_offset;
target_phys_addr_t dirty_offset;
dirty = 0;
dirty_offset = 0;
while (addr + dirty_offset < TARGET_PAGE_ALIGN(addr + src_width)) {

2
hw/framebuffer.h
View File

@ -7,7 +7,7 @@ typedef void (*drawfn)(void *, uint8_t *, const uint8_t *, int, int);
void framebuffer_update_display(
DisplayState *ds,
a_target_phys_addr base,
target_phys_addr_t base,
int cols,
int rows,
int src_width,

8
hw/fw_cfg.c
View File

@ -116,18 +116,18 @@ static void fw_cfg_io_writew(void *opaque, uint32_t addr, uint32_t value)
fw_cfg_select(opaque, (uint16_t)value);
}
static uint32_t fw_cfg_mem_readb(void *opaque, a_target_phys_addr addr)
static uint32_t fw_cfg_mem_readb(void *opaque, target_phys_addr_t addr)
{
return fw_cfg_read(opaque);
}
static void fw_cfg_mem_writeb(void *opaque, a_target_phys_addr addr,
static void fw_cfg_mem_writeb(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
fw_cfg_write(opaque, (uint8_t)value);
}
static void fw_cfg_mem_writew(void *opaque, a_target_phys_addr addr,
static void fw_cfg_mem_writew(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
fw_cfg_select(opaque, (uint16_t)value);
@ -242,7 +242,7 @@ int fw_cfg_add_callback(void *opaque, uint16_t key, FWCfgCallback callback,
}
void *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
a_target_phys_addr ctl_addr, a_target_phys_addr data_addr)
target_phys_addr_t ctl_addr, target_phys_addr_t data_addr)
{
FWCfgState *s;
int io_ctl_memory, io_data_memory;

2
hw/fw_cfg.h
View File

@ -35,7 +35,7 @@ int fw_cfg_add_i64(void *opaque, uint16_t key, uint64_t value);
int fw_cfg_add_callback(void *opaque, uint16_t key, FWCfgCallback callback,
void *callback_opaque, uint8_t *data, size_t len);
void *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
a_target_phys_addr crl_addr, a_target_phys_addr data_addr);
target_phys_addr_t crl_addr, target_phys_addr_t data_addr);
#endif /* NO_QEMU_PROTOS */

34
hw/g364fb.c
View File

@ -36,7 +36,7 @@ do { fprintf(stderr, "g364 ERROR: " fmt , ## __VA_ARGS__);} while (0)
typedef struct G364State {
/* hardware */
uint8_t *vram;
a_ram_addr vram_offset;
ram_addr_t vram_offset;
int vram_size;
qemu_irq irq;
/* registers */
@ -68,13 +68,13 @@ typedef struct G364State {
#define CTLA_FORCE_BLANK 0x00000400
#define CTLA_NO_CURSOR 0x00800000
static inline int check_dirty(a_ram_addr page)
static inline int check_dirty(ram_addr_t page)
{
return cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG);
}
static inline void reset_dirty(G364State *s,
a_ram_addr page_min, a_ram_addr page_max)
ram_addr_t page_min, ram_addr_t page_max)
{
cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE - 1,
VGA_DIRTY_FLAG);
@ -85,7 +85,7 @@ static void g364fb_draw_graphic8(G364State *s)
int i, w;
uint8_t *vram;
uint8_t *data_display, *dd;
a_ram_addr page, page_min, page_max;
ram_addr_t page, page_min, page_max;
int x, y;
int xmin, xmax;
int ymin, ymax;
@ -115,7 +115,7 @@ static void g364fb_draw_graphic8(G364State *s)
}
page = s->vram_offset;
page_min = (a_ram_addr)-1;
page_min = (ram_addr_t)-1;
page_max = 0;
x = y = 0;
@ -138,7 +138,7 @@ static void g364fb_draw_graphic8(G364State *s)
if (check_dirty(page)) {
if (y < ymin)
ymin = ymax = y;
if (page_min == (a_ram_addr)-1)
if (page_min == (ram_addr_t)-1)
page_min = page;
page_max = page;
if (x < xmin)
@ -197,9 +197,9 @@ static void g364fb_draw_graphic8(G364State *s)
ymax = y;
} else {
int dy;
if (page_min != (a_ram_addr)-1) {
if (page_min != (ram_addr_t)-1) {
reset_dirty(s, page_min, page_max);
page_min = (a_ram_addr)-1;
page_min = (ram_addr_t)-1;
page_max = 0;
dpy_update(s->ds, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1);
xmin = s->width;
@ -219,7 +219,7 @@ static void g364fb_draw_graphic8(G364State *s)
}
done:
if (page_min != (a_ram_addr)-1) {
if (page_min != (ram_addr_t)-1) {
dpy_update(s->ds, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1);
reset_dirty(s, page_min, page_max);
}
@ -336,7 +336,7 @@ static void g364fb_screen_dump(void *opaque, const char *filename)
}
/* called for accesses to io ports */
static uint32_t g364fb_ctrl_readl(void *opaque, a_target_phys_addr addr)
static uint32_t g364fb_ctrl_readl(void *opaque, target_phys_addr_t addr)
{
G364State *s = opaque;
uint32_t val;
@ -379,7 +379,7 @@ static uint32_t g364fb_ctrl_readl(void *opaque, a_target_phys_addr addr)
return val;
}
static uint32_t g364fb_ctrl_readw(void *opaque, a_target_phys_addr addr)
static uint32_t g364fb_ctrl_readw(void *opaque, target_phys_addr_t addr)
{
uint32_t v = g364fb_ctrl_readl(opaque, addr & ~0x3);
if (addr & 0x2)
@ -388,7 +388,7 @@ static uint32_t g364fb_ctrl_readw(void *opaque, a_target_phys_addr addr)
return v & 0xffff;
}
static uint32_t g364fb_ctrl_readb(void *opaque, a_target_phys_addr addr)
static uint32_t g364fb_ctrl_readb(void *opaque, target_phys_addr_t addr)
{
uint32_t v = g364fb_ctrl_readl(opaque, addr & ~0x3);
return (v >> (8 * (addr & 0x3))) & 0xff;
@ -415,7 +415,7 @@ static void g364_invalidate_cursor_position(G364State *s)
}
}
static void g364fb_ctrl_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
static void g364fb_ctrl_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
G364State *s = opaque;
@ -490,7 +490,7 @@ static void g364fb_ctrl_writel(void *opaque, a_target_phys_addr addr, uint32_t v
qemu_irq_lower(s->irq);
}
static void g364fb_ctrl_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
static void g364fb_ctrl_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
uint32_t old_val = g364fb_ctrl_readl(opaque, addr & ~0x3);
@ -501,7 +501,7 @@ static void g364fb_ctrl_writew(void *opaque, a_target_phys_addr addr, uint32_t v
g364fb_ctrl_writel(opaque, addr & ~0x3, val);
}
static void g364fb_ctrl_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
static void g364fb_ctrl_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
uint32_t old_val = g364fb_ctrl_readl(opaque, addr & ~0x3);
@ -583,8 +583,8 @@ static void g364fb_save(QEMUFile *f, void *opaque)
qemu_put_be32(f, s->height);
}
int g364fb_mm_init(a_target_phys_addr vram_base,
a_target_phys_addr ctrl_base, int it_shift,
int g364fb_mm_init(target_phys_addr_t vram_base,
target_phys_addr_t ctrl_base, int it_shift,
qemu_irq irq)
{
G364State *s;

6
hw/grackle_pci.c
View File

@ -37,7 +37,7 @@
#define GRACKLE_DPRINTF(fmt, ...)
#endif
typedef a_target_phys_addr a_pci_addr;
typedef target_phys_addr_t pci_addr_t;
#include "pci_host.h"
typedef struct GrackleState {
@ -45,7 +45,7 @@ typedef struct GrackleState {
PCIHostState host_state;
} GrackleState;
static void pci_grackle_config_writel (void *opaque, a_target_phys_addr addr,
static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
GrackleState *s = opaque;
@ -58,7 +58,7 @@ static void pci_grackle_config_writel (void *opaque, a_target_phys_addr addr,
s->host_state.config_reg = val;
}
static uint32_t pci_grackle_config_readl (void *opaque, a_target_phys_addr addr)
static uint32_t pci_grackle_config_readl (void *opaque, target_phys_addr_t addr)
{
GrackleState *s = opaque;
uint32_t val;

22
hw/gt64xxx.c
View File

@ -27,7 +27,7 @@
#include "pci.h"
#include "pc.h"
typedef a_target_phys_addr a_pci_addr;
typedef target_phys_addr_t pci_addr_t;
#include "pci_host.h"
//#define DEBUG
@ -229,8 +229,8 @@ typedef a_target_phys_addr a_pci_addr;
typedef PCIHostState GT64120PCIState;
#define PCI_MAPPING_ENTRY(regname) \
a_target_phys_addr regname ##_start; \
a_target_phys_addr regname ##_length; \
target_phys_addr_t regname ##_start; \
target_phys_addr_t regname ##_length; \
int regname ##_handle
typedef struct GT64120State {
@ -243,11 +243,11 @@ typedef struct GT64120State {
/* Adjust range to avoid touching space which isn't mappable via PCI */
/* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
0x1fc00000 - 0x1fd00000 */
static void check_reserved_space (a_target_phys_addr *start,
a_target_phys_addr *length)
static void check_reserved_space (target_phys_addr_t *start,
target_phys_addr_t *length)
{
a_target_phys_addr begin = *start;
a_target_phys_addr end = *start + *length;
target_phys_addr_t begin = *start;
target_phys_addr_t end = *start + *length;
if (end >= 0x1e000000LL && end < 0x1f100000LL)
end = 0x1e000000LL;
@ -269,8 +269,8 @@ static void check_reserved_space (a_target_phys_addr *start,
static void gt64120_isd_mapping(GT64120State *s)
{
a_target_phys_addr start = s->regs[GT_ISD] << 21;
a_target_phys_addr length = 0x1000;
target_phys_addr_t start = s->regs[GT_ISD] << 21;
target_phys_addr_t length = 0x1000;
if (s->ISD_length)
cpu_register_physical_memory(s->ISD_start, s->ISD_length,
@ -303,7 +303,7 @@ static void gt64120_pci_mapping(GT64120State *s)
}
}
static void gt64120_writel (void *opaque, a_target_phys_addr addr,
static void gt64120_writel (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
GT64120State *s = opaque;
@ -583,7 +583,7 @@ static void gt64120_writel (void *opaque, a_target_phys_addr addr,
}
static uint32_t gt64120_readl (void *opaque,
a_target_phys_addr addr)
target_phys_addr_t addr)
{
GT64120State *s = opaque;
uint32_t val;

4
hw/gumstix.c
View File

@ -41,7 +41,7 @@
static const int sector_len = 128 * 1024;
static void connex_init(a_ram_addr ram_size,
static void connex_init(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@ -75,7 +75,7 @@ static void connex_init(a_ram_addr ram_size,
pxa2xx_gpio_in_get(cpu->gpio)[36]);
}
static void verdex_init(a_ram_addr ram_size,
static void verdex_init(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)

4
hw/heathrow_pic.c
View File

@ -62,7 +62,7 @@ static void heathrow_pic_update(HeathrowPICS *s)
}
}
static void pic_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
static void pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
HeathrowPICS *s = opaque;
HeathrowPIC *pic;
@ -92,7 +92,7 @@ static void pic_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
}
}
static uint32_t pic_readl (void *opaque, a_target_phys_addr addr)
static uint32_t pic_readl (void *opaque, target_phys_addr_t addr)
{
HeathrowPICS *s = opaque;
HeathrowPIC *pic;

12
hw/hpet.c
View File

@ -270,20 +270,20 @@ static void hpet_del_timer(HPETTimer *t)
}
#ifdef HPET_DEBUG
static uint32_t hpet_ram_readb(void *opaque, a_target_phys_addr addr)
static uint32_t hpet_ram_readb(void *opaque, target_phys_addr_t addr)
{
printf("qemu: hpet_read b at %" PRIx64 "\n", addr);
return 0;
}
static uint32_t hpet_ram_readw(void *opaque, a_target_phys_addr addr)
static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr)
{
printf("qemu: hpet_read w at %" PRIx64 "\n", addr);
return 0;
}
#endif
static uint32_t hpet_ram_readl(void *opaque, a_target_phys_addr addr)
static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr)
{
HPETState *s = (HPETState *)opaque;
uint64_t cur_tick, index;
@ -350,14 +350,14 @@ static uint32_t hpet_ram_readl(void *opaque, a_target_phys_addr addr)
}
#ifdef HPET_DEBUG
static void hpet_ram_writeb(void *opaque, a_target_phys_addr addr,
static void hpet_ram_writeb(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
printf("qemu: invalid hpet_write b at %" PRIx64 " = %#x\n",
addr, value);
}
static void hpet_ram_writew(void *opaque, a_target_phys_addr addr,
static void hpet_ram_writew(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
printf("qemu: invalid hpet_write w at %" PRIx64 " = %#x\n",
@ -365,7 +365,7 @@ static void hpet_ram_writew(void *opaque, a_target_phys_addr addr,
}
#endif
static void hpet_ram_writel(void *opaque, a_target_phys_addr addr,
static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
int i;

2
hw/ide.h
View File

@ -18,7 +18,7 @@ int pmac_ide_init (DriveInfo **hd_table, qemu_irq irq,
void *dbdma, int channel, qemu_irq dma_irq);
/* ide-mmio.c */
void mmio_ide_init (a_target_phys_addr membase, a_target_phys_addr membase2,
void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
qemu_irq irq, int shift,
DriveInfo *hd0, DriveInfo *hd1);

12
hw/ide/macio.c
View File

@ -178,7 +178,7 @@ static void pmac_ide_flush(DBDMA_io *io)
/* PowerMac IDE memory IO */
static void pmac_ide_writeb (void *opaque,
a_target_phys_addr addr, uint32_t val)
target_phys_addr_t addr, uint32_t val)
{
MACIOIDEState *d = opaque;
@ -196,7 +196,7 @@ static void pmac_ide_writeb (void *opaque,
}
}
static uint32_t pmac_ide_readb (void *opaque,a_target_phys_addr addr)
static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr)
{
uint8_t retval;
MACIOIDEState *d = opaque;
@ -218,7 +218,7 @@ static uint32_t pmac_ide_readb (void *opaque,a_target_phys_addr addr)
}
static void pmac_ide_writew (void *opaque,
a_target_phys_addr addr, uint32_t val)
target_phys_addr_t addr, uint32_t val)
{
MACIOIDEState *d = opaque;
@ -231,7 +231,7 @@ static void pmac_ide_writew (void *opaque,
}
}
static uint32_t pmac_ide_readw (void *opaque,a_target_phys_addr addr)
static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr)
{
uint16_t retval;
MACIOIDEState *d = opaque;
@ -249,7 +249,7 @@ static uint32_t pmac_ide_readw (void *opaque,a_target_phys_addr addr)
}
static void pmac_ide_writel (void *opaque,
a_target_phys_addr addr, uint32_t val)
target_phys_addr_t addr, uint32_t val)
{
MACIOIDEState *d = opaque;
@ -262,7 +262,7 @@ static void pmac_ide_writel (void *opaque,
}
}
static uint32_t pmac_ide_readl (void *opaque,a_target_phys_addr addr)
static uint32_t pmac_ide_readl (void *opaque,target_phys_addr_t addr)
{
uint32_t retval;
MACIOIDEState *d = opaque;

10
hw/ide/mmio.c
View File

@ -41,7 +41,7 @@ typedef struct {
int shift;
} MMIOState;
static uint32_t mmio_ide_read (void *opaque, a_target_phys_addr addr)
static uint32_t mmio_ide_read (void *opaque, target_phys_addr_t addr)
{
MMIOState *s = (MMIOState*)opaque;
IDEBus *bus = s->bus;
@ -52,7 +52,7 @@ static uint32_t mmio_ide_read (void *opaque, a_target_phys_addr addr)
return ide_data_readw(bus, 0);
}
static void mmio_ide_write (void *opaque, a_target_phys_addr addr,
static void mmio_ide_write (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
MMIOState *s = (MMIOState*)opaque;
@ -76,14 +76,14 @@ static CPUWriteMemoryFunc * const mmio_ide_writes[] = {
mmio_ide_write,
};
static uint32_t mmio_ide_status_read (void *opaque, a_target_phys_addr addr)
static uint32_t mmio_ide_status_read (void *opaque, target_phys_addr_t addr)
{
MMIOState *s= (MMIOState*)opaque;
IDEBus *bus = s->bus;
return ide_status_read(bus, 0);
}
static void mmio_ide_cmd_write (void *opaque, a_target_phys_addr addr,
static void mmio_ide_cmd_write (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
MMIOState *s = (MMIOState*)opaque;
@ -122,7 +122,7 @@ static int mmio_ide_load(QEMUFile* f, void *opaque, int version_id)
return 0;
}
void mmio_ide_init (a_target_phys_addr membase, a_target_phys_addr membase2,
void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
qemu_irq irq, int shift,
DriveInfo *hd0, DriveInfo *hd1)
{

16
hw/integratorcp.c
View File

@ -37,7 +37,7 @@ static uint8_t integrator_spd[128] = {
0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
};
static uint32_t integratorcm_read(void *opaque, a_target_phys_addr offset)
static uint32_t integratorcm_read(void *opaque, target_phys_addr_t offset)
{
integratorcm_state *s = (integratorcm_state *)opaque;
if (offset >= 0x100 && offset < 0x200) {
@ -138,7 +138,7 @@ static void integratorcm_update(integratorcm_state *s)
hw_error("Core module interrupt\n");
}
static void integratorcm_write(void *opaque, a_target_phys_addr offset,
static void integratorcm_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
integratorcm_state *s = (integratorcm_state *)opaque;
@ -296,7 +296,7 @@ static void icp_pic_set_irq(void *opaque, int irq, int level)
icp_pic_update(s);
}
static uint32_t icp_pic_read(void *opaque, a_target_phys_addr offset)
static uint32_t icp_pic_read(void *opaque, target_phys_addr_t offset)
{
icp_pic_state *s = (icp_pic_state *)opaque;
@ -324,7 +324,7 @@ static uint32_t icp_pic_read(void *opaque, a_target_phys_addr offset)
}
}
static void icp_pic_write(void *opaque, a_target_phys_addr offset,
static void icp_pic_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
icp_pic_state *s = (icp_pic_state *)opaque;
@ -388,7 +388,7 @@ static int icp_pic_init(SysBusDevice *dev)
}
/* CP control registers. */
static uint32_t icp_control_read(void *opaque, a_target_phys_addr offset)
static uint32_t icp_control_read(void *opaque, target_phys_addr_t offset)
{
switch (offset >> 2) {
case 0: /* CP_IDFIELD */
@ -405,7 +405,7 @@ static uint32_t icp_control_read(void *opaque, a_target_phys_addr offset)
}
}
static void icp_control_write(void *opaque, a_target_phys_addr offset,
static void icp_control_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
switch (offset >> 2) {
@ -448,13 +448,13 @@ static struct arm_boot_info integrator_binfo = {
.board_id = 0x113,
};
static void integratorcp_init(a_ram_addr ram_size,
static void integratorcp_init(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
CPUState *env;
a_ram_addr ram_offset;
ram_addr_t ram_offset;
qemu_irq pic[32];
qemu_irq *cpu_pic;
DeviceState *dev;

4
hw/ioapic.c
View File

@ -119,7 +119,7 @@ void ioapic_set_irq(void *opaque, int vector, int level)
}
}
static uint32_t ioapic_mem_readl(void *opaque, a_target_phys_addr addr)
static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
{
IOAPICState *s = opaque;
int index;
@ -155,7 +155,7 @@ static uint32_t ioapic_mem_readl(void *opaque, a_target_phys_addr addr)
return val;
}
static void ioapic_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
IOAPICState *s = opaque;
int index;

26
hw/iommu.c
View File

@ -130,15 +130,15 @@
typedef struct IOMMUState {
SysBusDevice busdev;
uint32_t regs[IOMMU_NREGS];
a_target_phys_addr iostart;
target_phys_addr_t iostart;
uint32_t version;
qemu_irq irq;
} IOMMUState;
static uint32_t iommu_mem_readl(void *opaque, a_target_phys_addr addr)
static uint32_t iommu_mem_readl(void *opaque, target_phys_addr_t addr)
{
IOMMUState *s = opaque;
a_target_phys_addr saddr;
target_phys_addr_t saddr;
uint32_t ret;
saddr = addr >> 2;
@ -156,11 +156,11 @@ static uint32_t iommu_mem_readl(void *opaque, a_target_phys_addr addr)
return ret;
}
static void iommu_mem_writel(void *opaque, a_target_phys_addr addr,
static void iommu_mem_writel(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
IOMMUState *s = opaque;
a_target_phys_addr saddr;
target_phys_addr_t saddr;
saddr = addr >> 2;
DPRINTF("write reg[%d] = %x\n", (int)saddr, val);
@ -250,12 +250,12 @@ static CPUWriteMemoryFunc * const iommu_mem_write[3] = {
iommu_mem_writel,
};
static uint32_t iommu_page_get_flags(IOMMUState *s, a_target_phys_addr addr)
static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
{
uint32_t ret;
a_target_phys_addr iopte;
target_phys_addr_t iopte;
#ifdef DEBUG_IOMMU
a_target_phys_addr pa = addr;
target_phys_addr_t pa = addr;
#endif
iopte = s->regs[IOMMU_BASE] << 4;
@ -269,11 +269,11 @@ static uint32_t iommu_page_get_flags(IOMMUState *s, a_target_phys_addr addr)
return ret;
}
static a_target_phys_addr iommu_translate_pa(a_target_phys_addr addr,
static target_phys_addr_t iommu_translate_pa(target_phys_addr_t addr,
uint32_t pte)
{
uint32_t tmppte;
a_target_phys_addr pa;
target_phys_addr_t pa;
tmppte = pte;
pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK);
@ -283,7 +283,7 @@ static a_target_phys_addr iommu_translate_pa(a_target_phys_addr addr,
return pa;
}
static void iommu_bad_addr(IOMMUState *s, a_target_phys_addr addr,
static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr,
int is_write)
{
DPRINTF("bad addr " TARGET_FMT_plx "\n", addr);
@ -295,12 +295,12 @@ static void iommu_bad_addr(IOMMUState *s, a_target_phys_addr addr,
qemu_irq_raise(s->irq);
}
void sparc_iommu_memory_rw(void *opaque, a_target_phys_addr addr,
void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
uint8_t *buf, int len, int is_write)
{
int l;
uint32_t flags;
a_target_phys_addr page, phys_addr;
target_phys_addr_t page, phys_addr;
while (len > 0) {
page = addr & IOMMU_PAGE_MASK;

4
hw/isa.h
View File

@ -30,9 +30,9 @@ void isa_qdev_register(ISADeviceInfo *info);
ISADevice *isa_create(const char *name);
ISADevice *isa_create_simple(const char *name);
extern a_target_phys_addr isa_mem_base;
extern target_phys_addr_t isa_mem_base;
void isa_mmio_init(a_target_phys_addr base, a_target_phys_addr size);
void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
/* dma.c */
int DMA_get_channel_mode (int nchan);

14
hw/isa_mmio.c
View File

@ -25,13 +25,13 @@
#include "hw.h"
#include "isa.h"
static void isa_mmio_writeb (void *opaque, a_target_phys_addr addr,
static void isa_mmio_writeb (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
cpu_outb(addr & IOPORTS_MASK, val);
}
static void isa_mmio_writew (void *opaque, a_target_phys_addr addr,
static void isa_mmio_writew (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
@ -40,7 +40,7 @@ static void isa_mmio_writew (void *opaque, a_target_phys_addr addr,
cpu_outw(addr & IOPORTS_MASK, val);
}
static void isa_mmio_writel (void *opaque, a_target_phys_addr addr,
static void isa_mmio_writel (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
@ -49,7 +49,7 @@ static void isa_mmio_writel (void *opaque, a_target_phys_addr addr,
cpu_outl(addr & IOPORTS_MASK, val);
}
static uint32_t isa_mmio_readb (void *opaque, a_target_phys_addr addr)
static uint32_t isa_mmio_readb (void *opaque, target_phys_addr_t addr)
{
uint32_t val;
@ -57,7 +57,7 @@ static uint32_t isa_mmio_readb (void *opaque, a_target_phys_addr addr)
return val;
}
static uint32_t isa_mmio_readw (void *opaque, a_target_phys_addr addr)
static uint32_t isa_mmio_readw (void *opaque, target_phys_addr_t addr)
{
uint32_t val;
@ -68,7 +68,7 @@ static uint32_t isa_mmio_readw (void *opaque, a_target_phys_addr addr)
return val;
}
static uint32_t isa_mmio_readl (void *opaque, a_target_phys_addr addr)
static uint32_t isa_mmio_readl (void *opaque, target_phys_addr_t addr)
{
uint32_t val;
@ -93,7 +93,7 @@ static CPUReadMemoryFunc * const isa_mmio_read[] = {
static int isa_mmio_iomemtype = 0;
void isa_mmio_init(a_target_phys_addr base, a_target_phys_addr size)
void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size)
{
if (!isa_mmio_iomemtype) {
isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read,

20
hw/jazz_led.c
View File

@ -31,15 +31,15 @@
typedef enum {
REDRAW_NONE = 0, REDRAW_SEGMENTS = 1, REDRAW_BACKGROUND = 2,
} e_screen_state;
} screen_state_t;
typedef struct LedState {
uint8_t segments;
DisplayState *ds;
e_screen_state state;
screen_state_t state;
} LedState;
static uint32_t led_readb(void *opaque, a_target_phys_addr addr)
static uint32_t led_readb(void *opaque, target_phys_addr_t addr)
{
LedState *s = opaque;
uint32_t val;
@ -58,7 +58,7 @@ static uint32_t led_readb(void *opaque, a_target_phys_addr addr)
return val;
}
static uint32_t led_readw(void *opaque, a_target_phys_addr addr)
static uint32_t led_readw(void *opaque, target_phys_addr_t addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
@ -71,7 +71,7 @@ static uint32_t led_readw(void *opaque, a_target_phys_addr addr)
return v;
}
static uint32_t led_readl(void *opaque, a_target_phys_addr addr)
static uint32_t led_readl(void *opaque, target_phys_addr_t addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
@ -88,7 +88,7 @@ static uint32_t led_readl(void *opaque, a_target_phys_addr addr)
return v;
}
static void led_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
static void led_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
LedState *s = opaque;
@ -105,7 +105,7 @@ static void led_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
}
}
static void led_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
static void led_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
led_writeb(opaque, addr, (val >> 8) & 0xff);
@ -116,7 +116,7 @@ static void led_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
#endif
}
static void led_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
static void led_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
led_writeb(opaque, addr, (val >> 24) & 0xff);
@ -282,7 +282,7 @@ static void jazz_led_screen_dump(void *opaque, const char *filename)
printf("jazz_led_screen_dump() not implemented\n");
}
static void jazz_led_text_update(void *opaque, a_console_ch *chardata)
static void jazz_led_text_update(void *opaque, console_ch_t *chardata)
{
LedState *s = opaque;
char buf[2];
@ -298,7 +298,7 @@ static void jazz_led_text_update(void *opaque, a_console_ch *chardata)
dpy_update(s->ds, 0, 0, 2, 1);
}
void jazz_led_init(a_target_phys_addr base)
void jazz_led_init(target_phys_addr_t base)
{
LedState *s;
int io;

30
hw/loader.c
View File

@ -81,10 +81,10 @@ int load_image(const char *filename, uint8_t *addr)
}
/* return the amount read, just like fread. 0 may mean error or eof */
int fread_targphys(a_target_phys_addr dst_addr, size_t nbytes, FILE *f)
int fread_targphys(target_phys_addr_t dst_addr, size_t nbytes, FILE *f)
{
uint8_t buf[4096];
a_target_phys_addr dst_begin = dst_addr;
target_phys_addr_t dst_begin = dst_addr;
size_t want, did;
while (nbytes) {
@ -101,16 +101,16 @@ int fread_targphys(a_target_phys_addr dst_addr, size_t nbytes, FILE *f)
}
/* returns 0 on error, 1 if ok */
int fread_targphys_ok(a_target_phys_addr dst_addr, size_t nbytes, FILE *f)
int fread_targphys_ok(target_phys_addr_t dst_addr, size_t nbytes, FILE *f)
{
return fread_targphys(dst_addr, nbytes, f) == nbytes;
}
/* read()-like version */
int read_targphys(int fd, a_target_phys_addr dst_addr, size_t nbytes)
int read_targphys(int fd, target_phys_addr_t dst_addr, size_t nbytes)
{
uint8_t buf[4096];
a_target_phys_addr dst_begin = dst_addr;
target_phys_addr_t dst_begin = dst_addr;
size_t want, did;
while (nbytes) {
@ -127,7 +127,7 @@ int read_targphys(int fd, a_target_phys_addr dst_addr, size_t nbytes)
/* return the size or -1 if error */
int load_image_targphys(const char *filename,
a_target_phys_addr addr, int max_sz)
target_phys_addr_t addr, int max_sz)
{
FILE *f;
size_t got;
@ -142,7 +142,7 @@ int load_image_targphys(const char *filename,
return got;
}
void pstrcpy_targphys(a_target_phys_addr dest, int buf_size,
void pstrcpy_targphys(target_phys_addr_t dest, int buf_size,
const char *source)
{
static const uint8_t nul_byte = 0;
@ -204,8 +204,8 @@ static void bswap_ahdr(struct exec *e)
: (_N_SEGMENT_ROUND (_N_TXTENDADDR(x, target_page_size), target_page_size)))
int load_aout(const char *filename, a_target_phys_addr addr, int max_sz,
int bswap_needed, a_target_phys_addr target_page_size)
int load_aout(const char *filename, target_phys_addr_t addr, int max_sz,
int bswap_needed, target_phys_addr_t target_page_size)
{
int fd, size, ret;
struct exec e;
@ -358,7 +358,7 @@ int load_elf(const char *filename, int64_t address_offset,
return -1;
}
static void bswap_uboot_header(an_uboot_image_header *hdr)
static void bswap_uboot_header(uboot_image_header_t *hdr)
{
#ifndef HOST_WORDS_BIGENDIAN
bswap32s(&hdr->ih_magic);
@ -457,13 +457,13 @@ static ssize_t gunzip(void *dst, size_t dstlen, uint8_t *src,
}
/* Load a U-Boot image. */
int load_uimage(const char *filename, a_target_phys_addr *ep,
a_target_phys_addr *loadaddr, int *is_linux)
int load_uimage(const char *filename, target_phys_addr_t *ep,
target_phys_addr_t *loadaddr, int *is_linux)
{
int fd;
int size;
an_uboot_image_header h;
an_uboot_image_header *hdr = &h;
uboot_image_header_t h;
uboot_image_header_t *hdr = &h;
uint8_t *data = NULL;
int ret = -1;
@ -471,7 +471,7 @@ int load_uimage(const char *filename, a_target_phys_addr *ep,
if (fd < 0)
return -1;
size = read(fd, hdr, sizeof(an_uboot_image_header));
size = read(fd, hdr, sizeof(uboot_image_header_t));
if (size < 0)
goto out;

18
hw/loader.h
View File

@ -4,18 +4,18 @@
/* loader.c */
int get_image_size(const char *filename);
int load_image(const char *filename, uint8_t *addr); /* deprecated */
int load_image_targphys(const char *filename, a_target_phys_addr, int max_sz);
int load_image_targphys(const char *filename, target_phys_addr_t, int max_sz);
int load_elf(const char *filename, int64_t address_offset,
uint64_t *pentry, uint64_t *lowaddr, uint64_t *highaddr,
int big_endian, int elf_machine, int clear_lsb);
int load_aout(const char *filename, a_target_phys_addr addr, int max_sz,
int bswap_needed, a_target_phys_addr target_page_size);
int load_uimage(const char *filename, a_target_phys_addr *ep,
a_target_phys_addr *loadaddr, int *is_linux);
int load_aout(const char *filename, target_phys_addr_t addr, int max_sz,
int bswap_needed, target_phys_addr_t target_page_size);
int load_uimage(const char *filename, target_phys_addr_t *ep,
target_phys_addr_t *loadaddr, int *is_linux);
int fread_targphys(a_target_phys_addr dst_addr, size_t nbytes, FILE *f);
int fread_targphys_ok(a_target_phys_addr dst_addr, size_t nbytes, FILE *f);
int read_targphys(int fd, a_target_phys_addr dst_addr, size_t nbytes);
void pstrcpy_targphys(a_target_phys_addr dest, int buf_size,
int fread_targphys(target_phys_addr_t dst_addr, size_t nbytes, FILE *f);
int fread_targphys_ok(target_phys_addr_t dst_addr, size_t nbytes, FILE *f);
int read_targphys(int fd, target_phys_addr_t dst_addr, size_t nbytes);
void pstrcpy_targphys(target_phys_addr_t dest, int buf_size,
const char *source);
#endif

26
hw/lsi53c895a.c
View File

@ -484,7 +484,7 @@ static void lsi_resume_script(LSIState *s)
static void lsi_do_dma(LSIState *s, int out)
{
uint32_t count;
a_target_phys_addr addr;
target_phys_addr_t addr;
if (!s->current_dma_len) {
/* Wait until data is available. */
@ -1723,14 +1723,14 @@ static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val)
#undef CASE_SET_REG32
}
static void lsi_mmio_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
static void lsi_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
LSIState *s = opaque;
lsi_reg_writeb(s, addr & 0xff, val);
}
static void lsi_mmio_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
static void lsi_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
LSIState *s = opaque;
@ -1739,7 +1739,7 @@ static void lsi_mmio_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
}
static void lsi_mmio_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
static void lsi_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
LSIState *s = opaque;
@ -1750,14 +1750,14 @@ static void lsi_mmio_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
lsi_reg_writeb(s, addr + 3, (val >> 24) & 0xff);
}
static uint32_t lsi_mmio_readb(void *opaque, a_target_phys_addr addr)
static uint32_t lsi_mmio_readb(void *opaque, target_phys_addr_t addr)
{
LSIState *s = opaque;
return lsi_reg_readb(s, addr & 0xff);
}
static uint32_t lsi_mmio_readw(void *opaque, a_target_phys_addr addr)
static uint32_t lsi_mmio_readw(void *opaque, target_phys_addr_t addr)
{
LSIState *s = opaque;
uint32_t val;
@ -1768,7 +1768,7 @@ static uint32_t lsi_mmio_readw(void *opaque, a_target_phys_addr addr)
return val;
}
static uint32_t lsi_mmio_readl(void *opaque, a_target_phys_addr addr)
static uint32_t lsi_mmio_readl(void *opaque, target_phys_addr_t addr)
{
LSIState *s = opaque;
uint32_t val;
@ -1792,7 +1792,7 @@ static CPUWriteMemoryFunc * const lsi_mmio_writefn[3] = {
lsi_mmio_writel,
};
static void lsi_ram_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
static void lsi_ram_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
LSIState *s = opaque;
uint32_t newval;
@ -1806,7 +1806,7 @@ static void lsi_ram_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
s->script_ram[addr >> 2] = newval;
}
static void lsi_ram_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
static void lsi_ram_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
LSIState *s = opaque;
uint32_t newval;
@ -1822,7 +1822,7 @@ static void lsi_ram_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
}
static void lsi_ram_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
static void lsi_ram_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
LSIState *s = opaque;
@ -1830,7 +1830,7 @@ static void lsi_ram_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
s->script_ram[addr >> 2] = val;
}
static uint32_t lsi_ram_readb(void *opaque, a_target_phys_addr addr)
static uint32_t lsi_ram_readb(void *opaque, target_phys_addr_t addr)
{
LSIState *s = opaque;
uint32_t val;
@ -1841,7 +1841,7 @@ static uint32_t lsi_ram_readb(void *opaque, a_target_phys_addr addr)
return val & 0xff;
}
static uint32_t lsi_ram_readw(void *opaque, a_target_phys_addr addr)
static uint32_t lsi_ram_readw(void *opaque, target_phys_addr_t addr)
{
LSIState *s = opaque;
uint32_t val;
@ -1853,7 +1853,7 @@ static uint32_t lsi_ram_readw(void *opaque, a_target_phys_addr addr)
return le16_to_cpu(val);
}
static uint32_t lsi_ram_readl(void *opaque, a_target_phys_addr addr)
static uint32_t lsi_ram_readl(void *opaque, target_phys_addr_t addr)
{
LSIState *s = opaque;

72
hw/m48t59.c
View File

@ -41,7 +41,7 @@
* alarm and a watchdog timer and related control registers. In the
* PPC platform there is also a nvram lock function.
*/
struct m48t59 {
struct m48t59_t {
/* Model parameters */
uint32_t type; // 2 = m48t02, 8 = m48t08, 59 = m48t59
/* Hardware parameters */
@ -63,12 +63,12 @@ struct m48t59 {
typedef struct M48t59ISAState {
ISADevice busdev;
a_m48t59 state;
m48t59_t state;
} M48t59ISAState;
typedef struct M48t59SysBusState {
SysBusDevice busdev;
a_m48t59 state;
m48t59_t state;
} M48t59SysBusState;
/* Fake timer functions */
@ -88,7 +88,7 @@ static void alarm_cb (void *opaque)
{
struct tm tm;
uint64_t next_time;
a_m48t59 *NVRAM = opaque;
m48t59_t *NVRAM = opaque;
qemu_set_irq(NVRAM->IRQ, 1);
if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
@ -130,7 +130,7 @@ static void alarm_cb (void *opaque)
qemu_set_irq(NVRAM->IRQ, 0);
}
static void set_alarm (a_m48t59 *NVRAM)
static void set_alarm (m48t59_t *NVRAM)
{
int diff;
if (NVRAM->alrm_timer != NULL) {
@ -142,12 +142,12 @@ static void set_alarm (a_m48t59 *NVRAM)
}
/* RTC management helpers */
static inline void get_time (a_m48t59 *NVRAM, struct tm *tm)
static inline void get_time (m48t59_t *NVRAM, struct tm *tm)
{
qemu_get_timedate(tm, NVRAM->time_offset);
}
static void set_time (a_m48t59 *NVRAM, struct tm *tm)
static void set_time (m48t59_t *NVRAM, struct tm *tm)
{
NVRAM->time_offset = qemu_timedate_diff(tm);
set_alarm(NVRAM);
@ -156,7 +156,7 @@ static void set_time (a_m48t59 *NVRAM, struct tm *tm)
/* Watchdog management */
static void watchdog_cb (void *opaque)
{
a_m48t59 *NVRAM = opaque;
m48t59_t *NVRAM = opaque;
NVRAM->buffer[0x1FF0] |= 0x80;
if (NVRAM->buffer[0x1FF7] & 0x80) {
@ -170,7 +170,7 @@ static void watchdog_cb (void *opaque)
}
}
static void set_up_watchdog (a_m48t59 *NVRAM, uint8_t value)
static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value)
{
uint64_t interval; /* in 1/16 seconds */
@ -188,7 +188,7 @@ static void set_up_watchdog (a_m48t59 *NVRAM, uint8_t value)
/* Direct access to NVRAM */
void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
{
a_m48t59 *NVRAM = opaque;
m48t59_t *NVRAM = opaque;
struct tm tm;
int tmp;
@ -356,7 +356,7 @@ void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
uint32_t m48t59_read (void *opaque, uint32_t addr)
{
a_m48t59 *NVRAM = opaque;
m48t59_t *NVRAM = opaque;
struct tm tm;
uint32_t retval = 0xFF;
@ -463,14 +463,14 @@ uint32_t m48t59_read (void *opaque, uint32_t addr)
void m48t59_set_addr (void *opaque, uint32_t addr)
{
a_m48t59 *NVRAM = opaque;
m48t59_t *NVRAM = opaque;
NVRAM->addr = addr;
}
void m48t59_toggle_lock (void *opaque, int lock)
{
a_m48t59 *NVRAM = opaque;
m48t59_t *NVRAM = opaque;
NVRAM->lock ^= 1 << lock;
}
@ -478,7 +478,7 @@ void m48t59_toggle_lock (void *opaque, int lock)
/* IO access to NVRAM */
static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val)
{
a_m48t59 *NVRAM = opaque;
m48t59_t *NVRAM = opaque;
addr -= NVRAM->io_base;
NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
@ -502,7 +502,7 @@ static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val)
static uint32_t NVRAM_readb (void *opaque, uint32_t addr)
{
a_m48t59 *NVRAM = opaque;
m48t59_t *NVRAM = opaque;
uint32_t retval;
addr -= NVRAM->io_base;
@ -519,24 +519,24 @@ static uint32_t NVRAM_readb (void *opaque, uint32_t addr)
return retval;
}
static void nvram_writeb (void *opaque, a_target_phys_addr addr, uint32_t value)
static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
{
a_m48t59 *NVRAM = opaque;
m48t59_t *NVRAM = opaque;
m48t59_write(NVRAM, addr, value & 0xff);
}
static void nvram_writew (void *opaque, a_target_phys_addr addr, uint32_t value)
static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
{
a_m48t59 *NVRAM = opaque;
m48t59_t *NVRAM = opaque;
m48t59_write(NVRAM, addr, (value >> 8) & 0xff);
m48t59_write(NVRAM, addr + 1, value & 0xff);
}
static void nvram_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
a_m48t59 *NVRAM = opaque;
m48t59_t *NVRAM = opaque;
m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
@ -544,18 +544,18 @@ static void nvram_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
m48t59_write(NVRAM, addr + 3, value & 0xff);
}
static uint32_t nvram_readb (void *opaque, a_target_phys_addr addr)
static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
{
a_m48t59 *NVRAM = opaque;
m48t59_t *NVRAM = opaque;
uint32_t retval;
retval = m48t59_read(NVRAM, addr);
return retval;
}
static uint32_t nvram_readw (void *opaque, a_target_phys_addr addr)
static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
{
a_m48t59 *NVRAM = opaque;
m48t59_t *NVRAM = opaque;
uint32_t retval;
retval = m48t59_read(NVRAM, addr) << 8;
@ -563,9 +563,9 @@ static uint32_t nvram_readw (void *opaque, a_target_phys_addr addr)
return retval;
}
static uint32_t nvram_readl (void *opaque, a_target_phys_addr addr)
static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
{
a_m48t59 *NVRAM = opaque;
m48t59_t *NVRAM = opaque;
uint32_t retval;
retval = m48t59_read(NVRAM, addr) << 24;
@ -589,7 +589,7 @@ static CPUReadMemoryFunc * const nvram_read[] = {
static void m48t59_save(QEMUFile *f, void *opaque)
{
a_m48t59 *s = opaque;
m48t59_t *s = opaque;
qemu_put_8s(f, &s->lock);
qemu_put_be16s(f, &s->addr);
@ -598,7 +598,7 @@ static void m48t59_save(QEMUFile *f, void *opaque)
static int m48t59_load(QEMUFile *f, void *opaque, int version_id)
{
a_m48t59 *s = opaque;
m48t59_t *s = opaque;
if (version_id != 1)
return -EINVAL;
@ -612,7 +612,7 @@ static int m48t59_load(QEMUFile *f, void *opaque, int version_id)
static void m48t59_reset(void *opaque)
{
a_m48t59 *NVRAM = opaque;
m48t59_t *NVRAM = opaque;
NVRAM->addr = 0;
NVRAM->lock = 0;
@ -624,7 +624,7 @@ static void m48t59_reset(void *opaque)
}
/* Initialisation routine */
a_m48t59 *m48t59_init (qemu_irq IRQ, a_target_phys_addr mem_base,
m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
uint32_t io_base, uint16_t size,
int type)
{
@ -652,11 +652,11 @@ a_m48t59 *m48t59_init (qemu_irq IRQ, a_target_phys_addr mem_base,
return &d->state;
}
a_m48t59 *m48t59_init_isa(uint32_t io_base, uint16_t size, int type)
m48t59_t *m48t59_init_isa(uint32_t io_base, uint16_t size, int type)
{
M48t59ISAState *d;
ISADevice *dev;
a_m48t59 *s;
m48t59_t *s;
dev = isa_create("m48t59_isa");
qdev_prop_set_uint32(&dev->qdev, "type", type);
@ -674,7 +674,7 @@ a_m48t59 *m48t59_init_isa(uint32_t io_base, uint16_t size, int type)
return s;
}
static void m48t59_init_common(a_m48t59 *s)
static void m48t59_init_common(m48t59_t *s)
{
s->buffer = qemu_mallocz(s->size);
if (s->type == 59) {
@ -690,7 +690,7 @@ static void m48t59_init_common(a_m48t59 *s)
static int m48t59_init_isa1(ISADevice *dev)
{
M48t59ISAState *d = DO_UPCAST(M48t59ISAState, busdev, dev);
a_m48t59 *s = &d->state;
m48t59_t *s = &d->state;
isa_init_irq(dev, &s->IRQ, 8);
m48t59_init_common(s);
@ -701,7 +701,7 @@ static int m48t59_init_isa1(ISADevice *dev)
static int m48t59_init1(SysBusDevice *dev)
{
M48t59SysBusState *d = FROM_SYSBUS(M48t59SysBusState, dev);
a_m48t59 *s = &d->state;
m48t59_t *s = &d->state;
int mem_index;
sysbus_init_irq(dev, &s->IRQ);

4
hw/mac_dbdma.c
View File

@ -693,7 +693,7 @@ dbdma_control_write(DBDMA_channel *ch)
}
static void dbdma_writel (void *opaque,
a_target_phys_addr addr, uint32_t value)
target_phys_addr_t addr, uint32_t value)
{
int channel = addr >> DBDMA_CHANNEL_SHIFT;
DBDMA_channel *ch = (DBDMA_channel *)opaque + channel;
@ -741,7 +741,7 @@ static void dbdma_writel (void *opaque,
}
}
static uint32_t dbdma_readl (void *opaque, a_target_phys_addr addr)
static uint32_t dbdma_readl (void *opaque, target_phys_addr_t addr)
{
uint32_t value;
int channel = addr >> DBDMA_CHANNEL_SHIFT;

2
hw/mac_dbdma.h
View File

@ -28,7 +28,7 @@ typedef void (*DBDMA_end)(DBDMA_io *io);
struct DBDMA_io {
void *opaque;
void *channel;
a_target_phys_addr addr;
target_phys_addr_t addr;
int len;
int is_last;
int is_dma_out;

10
hw/mac_nvram.c
View File

@ -38,7 +38,7 @@
#endif
struct MacIONVRAMState {
a_target_phys_addr size;
target_phys_addr_t size;
int mem_index;
unsigned int it_shift;
uint8_t *data;
@ -72,7 +72,7 @@ void macio_nvram_write (void *opaque, uint32_t addr, uint32_t val)
/* macio style NVRAM device */
static void macio_nvram_writeb (void *opaque,
a_target_phys_addr addr, uint32_t value)
target_phys_addr_t addr, uint32_t value)
{
MacIONVRAMState *s = opaque;
@ -81,7 +81,7 @@ static void macio_nvram_writeb (void *opaque,
NVR_DPRINTF("writeb addr %04x val %x\n", (int)addr, value);
}
static uint32_t macio_nvram_readb (void *opaque, a_target_phys_addr addr)
static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr)
{
MacIONVRAMState *s = opaque;
uint32_t value;
@ -128,7 +128,7 @@ static void macio_nvram_reset(void *opaque)
{
}
MacIONVRAMState *macio_nvram_init (int *mem_index, a_target_phys_addr size,
MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size,
unsigned int it_shift)
{
MacIONVRAMState *s;
@ -148,7 +148,7 @@ MacIONVRAMState *macio_nvram_init (int *mem_index, a_target_phys_addr size,
return s;
}
void macio_nvram_map (void *opaque, a_target_phys_addr mem_base)
void macio_nvram_map (void *opaque, target_phys_addr_t mem_base)
{
MacIONVRAMState *s;

14
hw/macio.c
View File

@ -27,8 +27,8 @@
#include "pci.h"
#include "escc.h"
typedef struct macio_state a_macio_state;
struct macio_state {
typedef struct macio_state_t macio_state_t;
struct macio_state_t {
int is_oldworld;
int pic_mem_index;
int dbdma_mem_index;
@ -42,10 +42,10 @@ struct macio_state {
static void macio_map (PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
{
a_macio_state *macio_state;
macio_state_t *macio_state;
int i;
macio_state = (a_macio_state *)(pci_dev + 1);
macio_state = (macio_state_t *)(pci_dev + 1);
if (macio_state->pic_mem_index >= 0) {
if (macio_state->is_oldworld) {
/* Heathrow PIC */
@ -84,13 +84,13 @@ void macio_init (PCIBus *bus, int device_id, int is_oldworld, int pic_mem_index,
int nb_ide, int *ide_mem_index, int escc_mem_index)
{
PCIDevice *d;
a_macio_state *macio_state;
macio_state_t *macio_state;
int i;
d = pci_register_device(bus, "macio",
sizeof(PCIDevice) + sizeof(a_macio_state),
sizeof(PCIDevice) + sizeof(macio_state_t),
-1, NULL, NULL);
macio_state = (a_macio_state *)(d + 1);
macio_state = (macio_state_t *)(d + 1);
macio_state->is_oldworld = is_oldworld;
macio_state->pic_mem_index = pic_mem_index;
macio_state->dbdma_mem_index = dbdma_mem_index;

6
hw/mainstone.c
View File

@ -68,13 +68,13 @@ static struct arm_boot_info mainstone_binfo = {
.ram_size = 0x04000000,
};
static void mainstone_common_init(a_ram_addr ram_size,
static void mainstone_common_init(ram_addr_t ram_size,
const char *kernel_filename,
const char *kernel_cmdline, const char *initrd_filename,
const char *cpu_model, enum mainstone_model_e model, int arm_id)
{
uint32_t sector_len = 256 * 1024;
a_target_phys_addr mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };
target_phys_addr_t mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };
PXA2xxState *cpu;
qemu_irq *mst_irq;
DriveInfo *dinfo;
@ -127,7 +127,7 @@ static void mainstone_common_init(a_ram_addr ram_size,
arm_load_kernel(cpu->env, &mainstone_binfo);
}
static void mainstone_init(a_ram_addr ram_size,
static void mainstone_init(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)

4
hw/marvell_88w8618_audio.c
View File

@ -133,7 +133,7 @@ static void mv88w8618_audio_clock_update(mv88w8618_audio_state *s)
wm8750_set_bclk_in(s->wm, rate);
}
static uint32_t mv88w8618_audio_read(void *opaque, a_target_phys_addr offset)
static uint32_t mv88w8618_audio_read(void *opaque, target_phys_addr_t offset)
{
mv88w8618_audio_state *s = opaque;
@ -158,7 +158,7 @@ static uint32_t mv88w8618_audio_read(void *opaque, a_target_phys_addr offset)
}
}
static void mv88w8618_audio_write(void *opaque, a_target_phys_addr offset,
static void mv88w8618_audio_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
mv88w8618_audio_state *s = opaque;

14
hw/mc146818rtc.c
View File

@ -659,7 +659,7 @@ static void mc146818rtc_register(void)
device_init(mc146818rtc_register)
/* Memory mapped interface */
static uint32_t cmos_mm_readb (void *opaque, a_target_phys_addr addr)
static uint32_t cmos_mm_readb (void *opaque, target_phys_addr_t addr)
{
RTCState *s = opaque;
@ -667,14 +667,14 @@ static uint32_t cmos_mm_readb (void *opaque, a_target_phys_addr addr)
}
static void cmos_mm_writeb (void *opaque,
a_target_phys_addr addr, uint32_t value)
target_phys_addr_t addr, uint32_t value)
{
RTCState *s = opaque;
cmos_ioport_write(s, addr >> s->it_shift, value & 0xFF);
}
static uint32_t cmos_mm_readw (void *opaque, a_target_phys_addr addr)
static uint32_t cmos_mm_readw (void *opaque, target_phys_addr_t addr)
{
RTCState *s = opaque;
uint32_t val;
@ -687,7 +687,7 @@ static uint32_t cmos_mm_readw (void *opaque, a_target_phys_addr addr)
}
static void cmos_mm_writew (void *opaque,
a_target_phys_addr addr, uint32_t value)
target_phys_addr_t addr, uint32_t value)
{
RTCState *s = opaque;
#ifdef TARGET_WORDS_BIGENDIAN
@ -696,7 +696,7 @@ static void cmos_mm_writew (void *opaque,
cmos_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
}
static uint32_t cmos_mm_readl (void *opaque, a_target_phys_addr addr)
static uint32_t cmos_mm_readl (void *opaque, target_phys_addr_t addr)
{
RTCState *s = opaque;
uint32_t val;
@ -709,7 +709,7 @@ static uint32_t cmos_mm_readl (void *opaque, a_target_phys_addr addr)
}
static void cmos_mm_writel (void *opaque,
a_target_phys_addr addr, uint32_t value)
target_phys_addr_t addr, uint32_t value)
{
RTCState *s = opaque;
#ifdef TARGET_WORDS_BIGENDIAN
@ -730,7 +730,7 @@ static CPUWriteMemoryFunc * const rtc_mm_write[] = {
&cmos_mm_writel,
};
RTCState *rtc_mm_init(a_target_phys_addr base, int it_shift, qemu_irq irq,
RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
int base_year)
{
RTCState *s;

10
hw/mcf.h
View File

@ -3,17 +3,17 @@
/* Motorola ColdFire device prototypes. */
/* mcf_uart.c */
uint32_t mcf_uart_read(void *opaque, a_target_phys_addr addr);
void mcf_uart_write(void *opaque, a_target_phys_addr addr, uint32_t val);
uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr);
void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val);
void *mcf_uart_init(qemu_irq irq, CharDriverState *chr);
void mcf_uart_mm_init(a_target_phys_addr base, qemu_irq irq,
void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
CharDriverState *chr);
/* mcf_intc.c */
qemu_irq *mcf_intc_init(a_target_phys_addr base, CPUState *env);
qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env);
/* mcf_fec.c */
void mcf_fec_init(NICInfo *nd, a_target_phys_addr base, qemu_irq *irq);
void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq);
/* mcf5206.c */
qemu_irq *mcf5206_init(uint32_t base, CPUState *env);

20
hw/mcf5206.c
View File

@ -367,10 +367,10 @@ static const int m5206_mbar_width[] =
/* 1c0-200 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
};
static uint32_t m5206_mbar_readw(void *opaque, a_target_phys_addr offset);
static uint32_t m5206_mbar_readl(void *opaque, a_target_phys_addr offset);
static uint32_t m5206_mbar_readw(void *opaque, target_phys_addr_t offset);
static uint32_t m5206_mbar_readl(void *opaque, target_phys_addr_t offset);
static uint32_t m5206_mbar_readb(void *opaque, a_target_phys_addr offset)
static uint32_t m5206_mbar_readb(void *opaque, target_phys_addr_t offset)
{
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
offset &= 0x3ff;
@ -388,7 +388,7 @@ static uint32_t m5206_mbar_readb(void *opaque, a_target_phys_addr offset)
return m5206_mbar_read(s, offset);
}
static uint32_t m5206_mbar_readw(void *opaque, a_target_phys_addr offset)
static uint32_t m5206_mbar_readw(void *opaque, target_phys_addr_t offset)
{
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
int width;
@ -412,7 +412,7 @@ static uint32_t m5206_mbar_readw(void *opaque, a_target_phys_addr offset)
return m5206_mbar_read(s, offset);
}
static uint32_t m5206_mbar_readl(void *opaque, a_target_phys_addr offset)
static uint32_t m5206_mbar_readl(void *opaque, target_phys_addr_t offset)
{
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
int width;
@ -430,12 +430,12 @@ static uint32_t m5206_mbar_readl(void *opaque, a_target_phys_addr offset)
return m5206_mbar_read(s, offset);
}
static void m5206_mbar_writew(void *opaque, a_target_phys_addr offset,
static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset,
uint32_t value);
static void m5206_mbar_writel(void *opaque, a_target_phys_addr offset,
static void m5206_mbar_writel(void *opaque, target_phys_addr_t offset,
uint32_t value);
static void m5206_mbar_writeb(void *opaque, a_target_phys_addr offset,
static void m5206_mbar_writeb(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
@ -459,7 +459,7 @@ static void m5206_mbar_writeb(void *opaque, a_target_phys_addr offset,
m5206_mbar_write(s, offset, value);
}
static void m5206_mbar_writew(void *opaque, a_target_phys_addr offset,
static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
@ -487,7 +487,7 @@ static void m5206_mbar_writew(void *opaque, a_target_phys_addr offset,
m5206_mbar_write(s, offset, value);
}
static void m5206_mbar_writel(void *opaque, a_target_phys_addr offset,
static void m5206_mbar_writel(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
m5206_mbar_state *s = (m5206_mbar_state *)opaque;

12
hw/mcf5208.c
View File

@ -42,7 +42,7 @@ static void m5208_timer_update(m5208_timer_state *s)
qemu_irq_lower(s->irq);
}
static void m5208_timer_write(void *opaque, a_target_phys_addr offset,
static void m5208_timer_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
m5208_timer_state *s = (m5208_timer_state *)opaque;
@ -104,7 +104,7 @@ static void m5208_timer_trigger(void *opaque)
m5208_timer_update(s);
}
static uint32_t m5208_timer_read(void *opaque, a_target_phys_addr addr)
static uint32_t m5208_timer_read(void *opaque, target_phys_addr_t addr)
{
m5208_timer_state *s = (m5208_timer_state *)opaque;
switch (addr) {
@ -132,7 +132,7 @@ static CPUWriteMemoryFunc * const m5208_timer_writefn[] = {
m5208_timer_write
};
static uint32_t m5208_sys_read(void *opaque, a_target_phys_addr addr)
static uint32_t m5208_sys_read(void *opaque, target_phys_addr_t addr)
{
switch (addr) {
case 0x110: /* SDCS0 */
@ -153,7 +153,7 @@ static uint32_t m5208_sys_read(void *opaque, a_target_phys_addr addr)
}
}
static void m5208_sys_write(void *opaque, a_target_phys_addr addr,
static void m5208_sys_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
hw_error("m5208_sys_write: Bad offset 0x%x\n", (int)addr);
@ -195,7 +195,7 @@ static void mcf5208_sys_init(qemu_irq *pic)
}
}
static void mcf5208evb_init(a_ram_addr ram_size,
static void mcf5208evb_init(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@ -203,7 +203,7 @@ static void mcf5208evb_init(a_ram_addr ram_size,
CPUState *env;
int kernel_size;
uint64_t elf_entry;
a_target_phys_addr entry;
target_phys_addr_t entry;
qemu_irq *pic;
if (!cpu_model)

6
hw/mcf_fec.c
View File

@ -214,7 +214,7 @@ static void mcf_fec_reset(mcf_fec_state *s)
s->rfsr = 0x500;
}
static uint32_t mcf_fec_read(void *opaque, a_target_phys_addr addr)
static uint32_t mcf_fec_read(void *opaque, target_phys_addr_t addr)
{
mcf_fec_state *s = (mcf_fec_state *)opaque;
switch (addr & 0x3ff) {
@ -251,7 +251,7 @@ static uint32_t mcf_fec_read(void *opaque, a_target_phys_addr addr)
}
}
static void mcf_fec_write(void *opaque, a_target_phys_addr addr, uint32_t value)
static void mcf_fec_write(void *opaque, target_phys_addr_t addr, uint32_t value)
{
mcf_fec_state *s = (mcf_fec_state *)opaque;
switch (addr & 0x3ff) {
@ -450,7 +450,7 @@ static void mcf_fec_cleanup(VLANClientState *vc)
qemu_free(s);
}
void mcf_fec_init(NICInfo *nd, a_target_phys_addr base, qemu_irq *irq)
void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq)
{
mcf_fec_state *s;

6
hw/mcf_intc.c
View File

@ -41,7 +41,7 @@ static void mcf_intc_update(mcf_intc_state *s)
m68k_set_irq_level(s->env, best_level, s->active_vector);
}
static uint32_t mcf_intc_read(void *opaque, a_target_phys_addr addr)
static uint32_t mcf_intc_read(void *opaque, target_phys_addr_t addr)
{
int offset;
mcf_intc_state *s = (mcf_intc_state *)opaque;
@ -73,7 +73,7 @@ static uint32_t mcf_intc_read(void *opaque, a_target_phys_addr addr)
}
}
static void mcf_intc_write(void *opaque, a_target_phys_addr addr, uint32_t val)
static void mcf_intc_write(void *opaque, target_phys_addr_t addr, uint32_t val)
{
int offset;
mcf_intc_state *s = (mcf_intc_state *)opaque;
@ -139,7 +139,7 @@ static CPUWriteMemoryFunc * const mcf_intc_writefn[] = {
mcf_intc_write
};
qemu_irq *mcf_intc_init(a_target_phys_addr base, CPUState *env)
qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env)
{
mcf_intc_state *s;
int iomemtype;

6
hw/mcf_uart.c
View File

@ -64,7 +64,7 @@ static void mcf_uart_update(mcf_uart_state *s)
qemu_set_irq(s->irq, (s->isr & s->imr) != 0);
}
uint32_t mcf_uart_read(void *opaque, a_target_phys_addr addr)
uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr)
{
mcf_uart_state *s = (mcf_uart_state *)opaque;
switch (addr & 0x3f) {
@ -182,7 +182,7 @@ static void mcf_do_command(mcf_uart_state *s, uint8_t cmd)
}
}
void mcf_uart_write(void *opaque, a_target_phys_addr addr, uint32_t val)
void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val)
{
mcf_uart_state *s = (mcf_uart_state *)opaque;
switch (addr & 0x3f) {
@ -296,7 +296,7 @@ static CPUWriteMemoryFunc * const mcf_uart_writefn[] = {
mcf_uart_write
};
void mcf_uart_mm_init(a_target_phys_addr base, qemu_irq irq,
void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
CharDriverState *chr)
{
mcf_uart_state *s;

14
hw/mips.h
View File

@ -6,19 +6,19 @@
PCIBus *pci_gt64120_init(qemu_irq *pic);
/* ds1225y.c */
void *ds1225y_init(a_target_phys_addr mem_base, const char *filename);
void *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
void ds1225y_set_protection(void *opaque, int protection);
/* g364fb.c */
int g364fb_mm_init(a_target_phys_addr vram_base,
a_target_phys_addr ctrl_base, int it_shift,
int g364fb_mm_init(target_phys_addr_t vram_base,
target_phys_addr_t ctrl_base, int it_shift,
qemu_irq irq);
/* mipsnet.c */
void mipsnet_init(int base, qemu_irq irq, NICInfo *nd);
/* jazz_led.c */
extern void jazz_led_init(a_target_phys_addr base);
extern void jazz_led_init(target_phys_addr_t base);
/* mips_int.c */
extern void cpu_mips_irq_init_cpu(CPUState *env);
@ -28,7 +28,7 @@ extern void cpu_mips_clock_init(CPUState *);
/* rc4030.c */
typedef struct rc4030DMAState *rc4030_dma;
void rc4030_dma_memory_rw(void *opaque, a_target_phys_addr addr, uint8_t *buf, int len, int is_write);
void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write);
void rc4030_dma_read(void *dma, uint8_t *buf, int len);
void rc4030_dma_write(void *dma, uint8_t *buf, int len);
@ -36,8 +36,8 @@ void *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
qemu_irq **irqs, rc4030_dma **dmas);
/* dp8393x.c */
void dp83932_init(NICInfo *nd, a_target_phys_addr base, int it_shift,
void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
qemu_irq irq, void* mem_opaque,
void (*memory_rw)(void *opaque, a_target_phys_addr addr, uint8_t *buf, int len, int is_write));
void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write));
#endif

16
hw/mips_jazz.c
View File

@ -47,12 +47,12 @@ static void main_cpu_reset(void *opaque)
cpu_reset(env);
}
static uint32_t rtc_readb(void *opaque, a_target_phys_addr addr)
static uint32_t rtc_readb(void *opaque, target_phys_addr_t addr)
{
return cpu_inw(0x71);
}
static void rtc_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
static void rtc_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
cpu_outw(0x71, val & 0xff);
}
@ -69,7 +69,7 @@ static CPUWriteMemoryFunc * const rtc_write[3] = {
rtc_writeb,
};
static void dma_dummy_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
static void dma_dummy_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
/* Nothing to do. That is only to ensure that
* the current DMA acknowledge cycle is completed. */
@ -113,7 +113,7 @@ static void audio_init(qemu_irq *pic)
#define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
static
void mips_jazz_init (a_ram_addr ram_size,
void mips_jazz_init (ram_addr_t ram_size,
const char *cpu_model,
enum jazz_model_e jazz_model)
{
@ -128,8 +128,8 @@ void mips_jazz_init (a_ram_addr ram_size,
PITState *pit;
BlockDriverState *fds[MAX_FD];
qemu_irq esp_reset;
a_ram_addr ram_offset;
a_ram_addr bios_offset;
ram_addr_t ram_offset;
ram_addr_t bios_offset;
/* init CPUs */
if (cpu_model == NULL) {
@ -271,7 +271,7 @@ void mips_jazz_init (a_ram_addr ram_size,
}
static
void mips_magnum_init (a_ram_addr ram_size,
void mips_magnum_init (ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@ -280,7 +280,7 @@ void mips_magnum_init (a_ram_addr ram_size,
}
static
void mips_pica61_init (a_ram_addr ram_size,
void mips_pica61_init (ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)

24
hw/mips_malta.c
View File

@ -117,7 +117,7 @@ static void malta_fpga_update_display(void *opaque)
# define logout(fmt, ...) ((void)0)
#endif
struct eeprom24c0x {
struct _eeprom24c0x_t {
uint8_t tick;
uint8_t address;
uint8_t command;
@ -129,9 +129,9 @@ struct eeprom24c0x {
uint8_t contents[256];
};
typedef struct eeprom24c0x a_eeprom24c0x;
typedef struct _eeprom24c0x_t eeprom24c0x_t;
static a_eeprom24c0x eeprom = {
static eeprom24c0x_t eeprom = {
.contents = {
/* 00000000: */ 0x80,0x08,0x04,0x0D,0x0A,0x01,0x40,0x00,
/* 00000008: */ 0x01,0x75,0x54,0x00,0x82,0x08,0x00,0x01,
@ -217,7 +217,7 @@ static void eeprom24c0x_write(int scl, int sda)
eeprom.sda = sda;
}
static uint32_t malta_fpga_readl(void *opaque, a_target_phys_addr addr)
static uint32_t malta_fpga_readl(void *opaque, target_phys_addr_t addr)
{
MaltaFPGAState *s = opaque;
uint32_t val = 0;
@ -304,7 +304,7 @@ static uint32_t malta_fpga_readl(void *opaque, a_target_phys_addr addr)
return val;
}
static void malta_fpga_writel(void *opaque, a_target_phys_addr addr,
static void malta_fpga_writel(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
MaltaFPGAState *s = opaque;
@ -431,7 +431,7 @@ static void malta_fpga_led_init(CharDriverState *chr)
qemu_chr_printf(chr, "+--------+\r\n");
}
static MaltaFPGAState *malta_fpga_init(a_target_phys_addr base, qemu_irq uart_irq, CharDriverState *uart_chr)
static MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, qemu_irq uart_irq, CharDriverState *uart_chr)
{
MaltaFPGAState *s;
int malta;
@ -658,7 +658,7 @@ static void write_bootloader (CPUState *env, uint8_t *base,
static void prom_set(int index, const char *string, ...)
{
char buf[ENVP_ENTRY_SIZE];
a_target_phys_addr p;
target_phys_addr_t p;
va_list ap;
int32_t table_addr;
@ -688,7 +688,7 @@ static int64_t load_kernel (CPUState *env)
int64_t kernel_entry, kernel_low, kernel_high;
int index = 0;
long initrd_size;
a_ram_addr initrd_offset;
ram_addr_t initrd_offset;
int big_endian;
#ifdef TARGET_WORDS_BIGENDIAN
@ -763,21 +763,21 @@ static void main_cpu_reset(void *opaque)
}
static
void mips_malta_init (a_ram_addr ram_size,
void mips_malta_init (ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
char *filename;
a_ram_addr ram_offset;
a_ram_addr bios_offset;
ram_addr_t ram_offset;
ram_addr_t bios_offset;
target_long bios_size;
int64_t kernel_entry;
PCIBus *pci_bus;
ISADevice *isa_dev;
CPUState *env;
RTCState *rtc_state;
a_fdctrl *floppy_controller;
fdctrl_t *floppy_controller;
MaltaFPGAState *malta_fpga;
qemu_irq *i8259;
int piix4_devfn;

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