748 lines
19 KiB
C
748 lines
19 KiB
C
/*
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* QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
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*
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* Copyright (c) 2003-2005, 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "nvram.h"
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#include "qemu-timer.h"
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#include "sysemu.h"
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#include "sysbus.h"
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#include "isa.h"
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//#define DEBUG_NVRAM
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#if defined(DEBUG_NVRAM)
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#define NVRAM_PRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0)
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#else
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#define NVRAM_PRINTF(fmt, ...) do { } while (0)
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#endif
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/*
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* The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
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* alarm and a watchdog timer and related control registers. In the
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* PPC platform there is also a nvram lock function.
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*/
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struct m48t59_t {
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/* Model parameters */
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uint32_t type; // 2 = m48t02, 8 = m48t08, 59 = m48t59
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/* Hardware parameters */
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qemu_irq IRQ;
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uint32_t io_base;
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uint32_t size;
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/* RTC management */
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time_t time_offset;
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time_t stop_time;
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/* Alarm & watchdog */
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struct tm alarm;
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struct QEMUTimer *alrm_timer;
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struct QEMUTimer *wd_timer;
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/* NVRAM storage */
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uint8_t lock;
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uint16_t addr;
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uint8_t *buffer;
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};
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typedef struct M48t59ISAState {
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ISADevice busdev;
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m48t59_t state;
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} M48t59ISAState;
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typedef struct M48t59SysBusState {
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SysBusDevice busdev;
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m48t59_t state;
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} M48t59SysBusState;
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/* Fake timer functions */
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/* Generic helpers for BCD */
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static inline uint8_t toBCD (uint8_t value)
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{
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return (((value / 10) % 10) << 4) | (value % 10);
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}
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static inline uint8_t fromBCD (uint8_t BCD)
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{
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return ((BCD >> 4) * 10) + (BCD & 0x0F);
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}
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/* Alarm management */
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static void alarm_cb (void *opaque)
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{
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struct tm tm;
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uint64_t next_time;
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m48t59_t *NVRAM = opaque;
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qemu_set_irq(NVRAM->IRQ, 1);
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if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
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(NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
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(NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) {
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/* Repeat once a month */
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qemu_get_timedate(&tm, NVRAM->time_offset);
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tm.tm_mon++;
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if (tm.tm_mon == 13) {
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tm.tm_mon = 1;
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tm.tm_year++;
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}
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next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset;
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} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
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(NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
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(NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) {
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/* Repeat once a day */
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next_time = 24 * 60 * 60;
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} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
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(NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
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(NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) {
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/* Repeat once an hour */
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next_time = 60 * 60;
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} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
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(NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
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(NVRAM->buffer[0x1FF3] & 0x80) != 0 &&
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) {
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/* Repeat once a minute */
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next_time = 60;
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} else {
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/* Repeat once a second */
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next_time = 1;
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}
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qemu_mod_timer(NVRAM->alrm_timer, qemu_get_clock(vm_clock) +
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next_time * 1000);
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qemu_set_irq(NVRAM->IRQ, 0);
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}
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static void set_alarm (m48t59_t *NVRAM)
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{
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int diff;
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if (NVRAM->alrm_timer != NULL) {
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qemu_del_timer(NVRAM->alrm_timer);
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diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset;
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if (diff > 0)
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qemu_mod_timer(NVRAM->alrm_timer, diff * 1000);
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}
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}
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/* RTC management helpers */
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static inline void get_time (m48t59_t *NVRAM, struct tm *tm)
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{
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qemu_get_timedate(tm, NVRAM->time_offset);
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}
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static void set_time (m48t59_t *NVRAM, struct tm *tm)
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{
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NVRAM->time_offset = qemu_timedate_diff(tm);
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set_alarm(NVRAM);
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}
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/* Watchdog management */
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static void watchdog_cb (void *opaque)
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{
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m48t59_t *NVRAM = opaque;
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NVRAM->buffer[0x1FF0] |= 0x80;
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if (NVRAM->buffer[0x1FF7] & 0x80) {
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NVRAM->buffer[0x1FF7] = 0x00;
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NVRAM->buffer[0x1FFC] &= ~0x40;
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/* May it be a hw CPU Reset instead ? */
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qemu_system_reset_request();
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} else {
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qemu_set_irq(NVRAM->IRQ, 1);
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qemu_set_irq(NVRAM->IRQ, 0);
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}
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}
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static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value)
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{
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uint64_t interval; /* in 1/16 seconds */
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NVRAM->buffer[0x1FF0] &= ~0x80;
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if (NVRAM->wd_timer != NULL) {
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qemu_del_timer(NVRAM->wd_timer);
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if (value != 0) {
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interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F);
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qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) +
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((interval * 1000) >> 4));
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}
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}
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}
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/* Direct access to NVRAM */
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void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
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{
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m48t59_t *NVRAM = opaque;
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struct tm tm;
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int tmp;
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if (addr > 0x1FF8 && addr < 0x2000)
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NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
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/* check for NVRAM access */
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if ((NVRAM->type == 2 && addr < 0x7f8) ||
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(NVRAM->type == 8 && addr < 0x1ff8) ||
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(NVRAM->type == 59 && addr < 0x1ff0))
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goto do_write;
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/* TOD access */
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switch (addr) {
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case 0x1FF0:
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/* flags register : read-only */
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break;
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case 0x1FF1:
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/* unused */
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break;
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case 0x1FF2:
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/* alarm seconds */
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tmp = fromBCD(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) {
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NVRAM->alarm.tm_sec = tmp;
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NVRAM->buffer[0x1FF2] = val;
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set_alarm(NVRAM);
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}
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break;
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case 0x1FF3:
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/* alarm minutes */
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tmp = fromBCD(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) {
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NVRAM->alarm.tm_min = tmp;
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NVRAM->buffer[0x1FF3] = val;
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set_alarm(NVRAM);
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}
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break;
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case 0x1FF4:
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/* alarm hours */
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tmp = fromBCD(val & 0x3F);
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if (tmp >= 0 && tmp <= 23) {
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NVRAM->alarm.tm_hour = tmp;
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NVRAM->buffer[0x1FF4] = val;
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set_alarm(NVRAM);
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}
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break;
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case 0x1FF5:
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/* alarm date */
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tmp = fromBCD(val & 0x1F);
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if (tmp != 0) {
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NVRAM->alarm.tm_mday = tmp;
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NVRAM->buffer[0x1FF5] = val;
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set_alarm(NVRAM);
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}
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break;
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case 0x1FF6:
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/* interrupts */
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NVRAM->buffer[0x1FF6] = val;
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break;
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case 0x1FF7:
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/* watchdog */
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NVRAM->buffer[0x1FF7] = val;
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set_up_watchdog(NVRAM, val);
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break;
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case 0x1FF8:
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case 0x07F8:
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/* control */
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NVRAM->buffer[addr] = (val & ~0xA0) | 0x90;
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break;
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case 0x1FF9:
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case 0x07F9:
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/* seconds (BCD) */
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tmp = fromBCD(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) {
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get_time(NVRAM, &tm);
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tm.tm_sec = tmp;
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set_time(NVRAM, &tm);
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}
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if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) {
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if (val & 0x80) {
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NVRAM->stop_time = time(NULL);
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} else {
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NVRAM->time_offset += NVRAM->stop_time - time(NULL);
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NVRAM->stop_time = 0;
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}
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}
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NVRAM->buffer[addr] = val & 0x80;
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break;
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case 0x1FFA:
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case 0x07FA:
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/* minutes (BCD) */
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tmp = fromBCD(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) {
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get_time(NVRAM, &tm);
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tm.tm_min = tmp;
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set_time(NVRAM, &tm);
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}
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break;
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case 0x1FFB:
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case 0x07FB:
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/* hours (BCD) */
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tmp = fromBCD(val & 0x3F);
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if (tmp >= 0 && tmp <= 23) {
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get_time(NVRAM, &tm);
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tm.tm_hour = tmp;
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set_time(NVRAM, &tm);
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}
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break;
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case 0x1FFC:
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case 0x07FC:
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/* day of the week / century */
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tmp = fromBCD(val & 0x07);
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get_time(NVRAM, &tm);
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tm.tm_wday = tmp;
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set_time(NVRAM, &tm);
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NVRAM->buffer[addr] = val & 0x40;
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break;
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case 0x1FFD:
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case 0x07FD:
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/* date */
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tmp = fromBCD(val & 0x1F);
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if (tmp != 0) {
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get_time(NVRAM, &tm);
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tm.tm_mday = tmp;
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set_time(NVRAM, &tm);
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}
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break;
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case 0x1FFE:
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case 0x07FE:
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/* month */
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tmp = fromBCD(val & 0x1F);
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if (tmp >= 1 && tmp <= 12) {
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get_time(NVRAM, &tm);
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tm.tm_mon = tmp - 1;
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set_time(NVRAM, &tm);
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}
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break;
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case 0x1FFF:
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case 0x07FF:
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/* year */
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tmp = fromBCD(val);
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if (tmp >= 0 && tmp <= 99) {
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get_time(NVRAM, &tm);
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if (NVRAM->type == 8)
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tm.tm_year = fromBCD(val) + 68; // Base year is 1968
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else
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tm.tm_year = fromBCD(val);
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set_time(NVRAM, &tm);
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}
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break;
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default:
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/* Check lock registers state */
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if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
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break;
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if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
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break;
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do_write:
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if (addr < NVRAM->size) {
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NVRAM->buffer[addr] = val & 0xFF;
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}
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break;
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}
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}
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uint32_t m48t59_read (void *opaque, uint32_t addr)
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{
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m48t59_t *NVRAM = opaque;
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struct tm tm;
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uint32_t retval = 0xFF;
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/* check for NVRAM access */
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if ((NVRAM->type == 2 && addr < 0x078f) ||
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(NVRAM->type == 8 && addr < 0x1ff8) ||
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(NVRAM->type == 59 && addr < 0x1ff0))
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goto do_read;
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/* TOD access */
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switch (addr) {
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case 0x1FF0:
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/* flags register */
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goto do_read;
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case 0x1FF1:
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/* unused */
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retval = 0;
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break;
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case 0x1FF2:
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/* alarm seconds */
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goto do_read;
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case 0x1FF3:
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/* alarm minutes */
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goto do_read;
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case 0x1FF4:
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/* alarm hours */
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goto do_read;
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case 0x1FF5:
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/* alarm date */
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goto do_read;
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case 0x1FF6:
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/* interrupts */
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goto do_read;
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case 0x1FF7:
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/* A read resets the watchdog */
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set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
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goto do_read;
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case 0x1FF8:
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case 0x07F8:
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/* control */
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goto do_read;
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case 0x1FF9:
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case 0x07F9:
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/* seconds (BCD) */
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get_time(NVRAM, &tm);
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retval = (NVRAM->buffer[addr] & 0x80) | toBCD(tm.tm_sec);
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break;
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case 0x1FFA:
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case 0x07FA:
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/* minutes (BCD) */
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get_time(NVRAM, &tm);
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retval = toBCD(tm.tm_min);
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break;
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case 0x1FFB:
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case 0x07FB:
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/* hours (BCD) */
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get_time(NVRAM, &tm);
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retval = toBCD(tm.tm_hour);
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break;
|
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case 0x1FFC:
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case 0x07FC:
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/* day of the week / century */
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get_time(NVRAM, &tm);
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retval = NVRAM->buffer[addr] | tm.tm_wday;
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break;
|
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case 0x1FFD:
|
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case 0x07FD:
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/* date */
|
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get_time(NVRAM, &tm);
|
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retval = toBCD(tm.tm_mday);
|
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break;
|
|
case 0x1FFE:
|
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case 0x07FE:
|
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/* month */
|
|
get_time(NVRAM, &tm);
|
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retval = toBCD(tm.tm_mon + 1);
|
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break;
|
|
case 0x1FFF:
|
|
case 0x07FF:
|
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/* year */
|
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get_time(NVRAM, &tm);
|
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if (NVRAM->type == 8)
|
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retval = toBCD(tm.tm_year - 68); // Base year is 1968
|
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else
|
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retval = toBCD(tm.tm_year);
|
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break;
|
|
default:
|
|
/* Check lock registers state */
|
|
if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
|
|
break;
|
|
if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
|
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break;
|
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do_read:
|
|
if (addr < NVRAM->size) {
|
|
retval = NVRAM->buffer[addr];
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}
|
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break;
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}
|
|
if (addr > 0x1FF9 && addr < 0x2000)
|
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NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
|
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|
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return retval;
|
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}
|
|
|
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void m48t59_set_addr (void *opaque, uint32_t addr)
|
|
{
|
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m48t59_t *NVRAM = opaque;
|
|
|
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NVRAM->addr = addr;
|
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}
|
|
|
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void m48t59_toggle_lock (void *opaque, int lock)
|
|
{
|
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m48t59_t *NVRAM = opaque;
|
|
|
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NVRAM->lock ^= 1 << lock;
|
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}
|
|
|
|
/* IO access to NVRAM */
|
|
static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val)
|
|
{
|
|
m48t59_t *NVRAM = opaque;
|
|
|
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addr -= NVRAM->io_base;
|
|
NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
|
|
switch (addr) {
|
|
case 0:
|
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NVRAM->addr &= ~0x00FF;
|
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NVRAM->addr |= val;
|
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break;
|
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case 1:
|
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NVRAM->addr &= ~0xFF00;
|
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NVRAM->addr |= val << 8;
|
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break;
|
|
case 3:
|
|
m48t59_write(NVRAM, val, NVRAM->addr);
|
|
NVRAM->addr = 0x0000;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
static uint32_t NVRAM_readb (void *opaque, uint32_t addr)
|
|
{
|
|
m48t59_t *NVRAM = opaque;
|
|
uint32_t retval;
|
|
|
|
addr -= NVRAM->io_base;
|
|
switch (addr) {
|
|
case 3:
|
|
retval = m48t59_read(NVRAM, NVRAM->addr);
|
|
break;
|
|
default:
|
|
retval = -1;
|
|
break;
|
|
}
|
|
NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
|
|
|
|
return retval;
|
|
}
|
|
|
|
static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
|
|
{
|
|
m48t59_t *NVRAM = opaque;
|
|
|
|
m48t59_write(NVRAM, addr, value & 0xff);
|
|
}
|
|
|
|
static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
|
|
{
|
|
m48t59_t *NVRAM = opaque;
|
|
|
|
m48t59_write(NVRAM, addr, (value >> 8) & 0xff);
|
|
m48t59_write(NVRAM, addr + 1, value & 0xff);
|
|
}
|
|
|
|
static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
|
|
{
|
|
m48t59_t *NVRAM = opaque;
|
|
|
|
m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
|
|
m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
|
|
m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff);
|
|
m48t59_write(NVRAM, addr + 3, value & 0xff);
|
|
}
|
|
|
|
static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
|
|
{
|
|
m48t59_t *NVRAM = opaque;
|
|
uint32_t retval;
|
|
|
|
retval = m48t59_read(NVRAM, addr);
|
|
return retval;
|
|
}
|
|
|
|
static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
|
|
{
|
|
m48t59_t *NVRAM = opaque;
|
|
uint32_t retval;
|
|
|
|
retval = m48t59_read(NVRAM, addr) << 8;
|
|
retval |= m48t59_read(NVRAM, addr + 1);
|
|
return retval;
|
|
}
|
|
|
|
static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
|
|
{
|
|
m48t59_t *NVRAM = opaque;
|
|
uint32_t retval;
|
|
|
|
retval = m48t59_read(NVRAM, addr) << 24;
|
|
retval |= m48t59_read(NVRAM, addr + 1) << 16;
|
|
retval |= m48t59_read(NVRAM, addr + 2) << 8;
|
|
retval |= m48t59_read(NVRAM, addr + 3);
|
|
return retval;
|
|
}
|
|
|
|
static CPUWriteMemoryFunc * const nvram_write[] = {
|
|
&nvram_writeb,
|
|
&nvram_writew,
|
|
&nvram_writel,
|
|
};
|
|
|
|
static CPUReadMemoryFunc * const nvram_read[] = {
|
|
&nvram_readb,
|
|
&nvram_readw,
|
|
&nvram_readl,
|
|
};
|
|
|
|
static void m48t59_save(QEMUFile *f, void *opaque)
|
|
{
|
|
m48t59_t *s = opaque;
|
|
|
|
qemu_put_8s(f, &s->lock);
|
|
qemu_put_be16s(f, &s->addr);
|
|
qemu_put_buffer(f, s->buffer, s->size);
|
|
}
|
|
|
|
static int m48t59_load(QEMUFile *f, void *opaque, int version_id)
|
|
{
|
|
m48t59_t *s = opaque;
|
|
|
|
if (version_id != 1)
|
|
return -EINVAL;
|
|
|
|
qemu_get_8s(f, &s->lock);
|
|
qemu_get_be16s(f, &s->addr);
|
|
qemu_get_buffer(f, s->buffer, s->size);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void m48t59_reset(void *opaque)
|
|
{
|
|
m48t59_t *NVRAM = opaque;
|
|
|
|
NVRAM->addr = 0;
|
|
NVRAM->lock = 0;
|
|
if (NVRAM->alrm_timer != NULL)
|
|
qemu_del_timer(NVRAM->alrm_timer);
|
|
|
|
if (NVRAM->wd_timer != NULL)
|
|
qemu_del_timer(NVRAM->wd_timer);
|
|
}
|
|
|
|
/* Initialisation routine */
|
|
m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
|
|
uint32_t io_base, uint16_t size,
|
|
int type)
|
|
{
|
|
DeviceState *dev;
|
|
SysBusDevice *s;
|
|
M48t59SysBusState *d;
|
|
|
|
dev = qdev_create(NULL, "m48t59");
|
|
qdev_prop_set_uint32(dev, "type", type);
|
|
qdev_prop_set_uint32(dev, "size", size);
|
|
qdev_prop_set_uint32(dev, "io_base", io_base);
|
|
qdev_init(dev);
|
|
s = sysbus_from_qdev(dev);
|
|
sysbus_connect_irq(s, 0, IRQ);
|
|
if (io_base != 0) {
|
|
register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s);
|
|
register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s);
|
|
}
|
|
if (mem_base != 0) {
|
|
sysbus_mmio_map(s, 0, mem_base);
|
|
}
|
|
|
|
d = FROM_SYSBUS(M48t59SysBusState, s);
|
|
|
|
return &d->state;
|
|
}
|
|
|
|
m48t59_t *m48t59_init_isa(uint32_t io_base, uint16_t size, int type)
|
|
{
|
|
M48t59ISAState *d;
|
|
ISADevice *dev;
|
|
m48t59_t *s;
|
|
|
|
dev = isa_create("m48t59_isa");
|
|
qdev_prop_set_uint32(&dev->qdev, "type", type);
|
|
qdev_prop_set_uint32(&dev->qdev, "size", size);
|
|
qdev_prop_set_uint32(&dev->qdev, "io_base", io_base);
|
|
qdev_init(&dev->qdev);
|
|
d = DO_UPCAST(M48t59ISAState, busdev, dev);
|
|
s = &d->state;
|
|
|
|
if (io_base != 0) {
|
|
register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s);
|
|
register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s);
|
|
}
|
|
|
|
return s;
|
|
}
|
|
|
|
static void m48t59_init_common(m48t59_t *s)
|
|
{
|
|
s->buffer = qemu_mallocz(s->size);
|
|
if (s->type == 59) {
|
|
s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s);
|
|
s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s);
|
|
}
|
|
qemu_get_timedate(&s->alarm, 0);
|
|
|
|
qemu_register_reset(m48t59_reset, s);
|
|
register_savevm("m48t59", -1, 1, m48t59_save, m48t59_load, s);
|
|
}
|
|
|
|
static int m48t59_init_isa1(ISADevice *dev)
|
|
{
|
|
M48t59ISAState *d = DO_UPCAST(M48t59ISAState, busdev, dev);
|
|
m48t59_t *s = &d->state;
|
|
|
|
isa_init_irq(dev, &s->IRQ, 8);
|
|
m48t59_init_common(s);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int m48t59_init1(SysBusDevice *dev)
|
|
{
|
|
M48t59SysBusState *d = FROM_SYSBUS(M48t59SysBusState, dev);
|
|
m48t59_t *s = &d->state;
|
|
int mem_index;
|
|
|
|
sysbus_init_irq(dev, &s->IRQ);
|
|
|
|
mem_index = cpu_register_io_memory(nvram_read, nvram_write, s);
|
|
sysbus_init_mmio(dev, s->size, mem_index);
|
|
m48t59_init_common(s);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static ISADeviceInfo m48t59_isa_info = {
|
|
.init = m48t59_init_isa1,
|
|
.qdev.name = "m48t59_isa",
|
|
.qdev.size = sizeof(M48t59ISAState),
|
|
.qdev.no_user = 1,
|
|
.qdev.props = (Property[]) {
|
|
DEFINE_PROP_UINT32("size", M48t59ISAState, state.size, -1),
|
|
DEFINE_PROP_UINT32("type", M48t59ISAState, state.type, -1),
|
|
DEFINE_PROP_HEX32( "io_base", M48t59ISAState, state.io_base, 0),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
}
|
|
};
|
|
|
|
static SysBusDeviceInfo m48t59_info = {
|
|
.init = m48t59_init1,
|
|
.qdev.name = "m48t59",
|
|
.qdev.size = sizeof(M48t59SysBusState),
|
|
.qdev.props = (Property[]) {
|
|
DEFINE_PROP_UINT32("size", M48t59SysBusState, state.size, -1),
|
|
DEFINE_PROP_UINT32("type", M48t59SysBusState, state.type, -1),
|
|
DEFINE_PROP_HEX32( "io_base", M48t59SysBusState, state.io_base, 0),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
}
|
|
};
|
|
|
|
static void m48t59_register_devices(void)
|
|
{
|
|
sysbus_register_withprop(&m48t59_info);
|
|
isa_qdev_register(&m48t59_isa_info);
|
|
}
|
|
|
|
device_init(m48t59_register_devices)
|