mirror of https://gerrit.osmocom.org/libusrp
c84380718a
Adds --enable-python option to configure (defaults to yes). Using --disable-python or --enable-python=no will cause only C++ API targets to be created and installed. Several new shared libraries are now created. Where in the past, the C++ objects of the actual gnuradio blocks that were in a component were hidden inside their corresponding Python extension modules, these are now split out into a libgnuradio-foo.so library, and the _foo.so Python module is linked to that. This has been the way several top- level components have operated for some time, such as gr-audio-alsa and gr-usrp and gr-usrp2. This changeset applies that pattern to all components. C++ API users can use pkg-config to discover the cflags and libs parameters needed to include and link against these libraries. These components have not been tested: gr-comedi gr-audio-osx gr-audio-windows Passes distcheck. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@11150 221aa14e-8319-0410-a670-987f0aec2ac5 |
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doc | ||
firmware | ||
fpga | ||
host | ||
Makefile.am | ||
README | ||
usrp-inband.pc.in | ||
usrp.inf | ||
usrp.iss.in | ||
usrp.pc.in |
README
# # README -- the short version # The top level makefile handles the host code and FX2 firmware. Besides the normal gcc suite and all the auto tools, you'll need the SDCC free C compiler to build the firmware. You MUST USE VERSION 2.4.0 or VERSION 2.5.0 due to some problems with variable initialization. http://sdcc.sourceforge.net The high level interface to the USRP using our standard FPGA bitstram is contained in usrp/host/lib/usrp_standard.h If you've got doxygen installed, there are html docs in usrp/doc/html/index.html # Compiling the verilog (not required unless you're modifying it) If you want to build the FPGA .rbf file from source (not required; we provide pre-compiled .rbf files in usrp/fpga/rbf directory), you'll need Altera's no cost Quartus II development tools. We're currently building with Quartus II 5.1sp1 Web Edition. The project file is usrp/fpga/toplevel/usrp_std/usrp_std.qpf. The toplevel verilog file is usrp/fpga/toplevel/usrp_std/usrp_std.v. The bulk of the verilog modules are contained in usrp/fpga/sdr_lib