by a configurable number of clock ticks, to allow users to precisely
align their T/R output with the pipeline delays in the transmitter.
There are two new registers:
FR_ATR_TX_DELAY (7'd2)
FR_ATR_RX_DELAY (7'd3)
...and the corresponding db_base.py methods to set them:
db_base.set_atr_tx_delay(clock_ticks)
db_base.set_atr_rx_delay(clock_ticks)
These methods are inherited by all the daughterboard objects so you can
call them from your scripts as:
subdev.set_atr_tx_delay(...)
...where 'subdev' represents the daughtercard object you're working with.
The FPGA synthesis for the 2 RXHB, 2 TX case expands from 95% to 96%,
with no additional synthesis messages or impact on timing.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@5022 221aa14e-8319-0410-a670-987f0aec2ac5
* firmware/include/Makefile.am: avoid nonportable use of $< (first
prereq in GNU make, implied source for pattern rule in BSD make)
used in a non-pattern rule.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@3762 221aa14e-8319-0410-a670-987f0aec2ac5
/gnuradio/branches/developers/jcorgan/ticket-10. 'make distcheck' now
successfully completes on a machine that has never had gnuradio installed
before. In addition, several cleanups and refactoring of build system
code have been applied. NOTE: gr-audio-portaudio, gr-audio-osx, and
gr-audio-windows have not been fully tested and will need verification
by the maintainers of these components.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@3216 221aa14e-8319-0410-a670-987f0aec2ac5
eb