mirror of https://gerrit.osmocom.org/libusrp
Merged r6749:6763 from jcorgan/t179. Fixes ticket:179. New RBFs synthesized with 7.1SP1.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@6764 221aa14e-8319-0410-a670-987f0aec2ac5
This commit is contained in:
jcorgan
parent
9ba1d3956a
commit
c1a7b06c3a
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@ -0,0 +1,186 @@
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// megafunction wizard: %FIFO%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: dcfifo
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// ============================================================
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// File Name: fifo_4k_18.v
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// Megafunction Name(s):
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// dcfifo
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//
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// Simulation Library Files(s):
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// altera_mf
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 7.1 Build 178 06/25/2007 SP 1 SJ Web Edition
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// ************************************************************
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//Copyright (C) 1991-2007 Altera Corporation
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//Your use of Altera Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Altera Program License
|
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//Subscription Agreement, Altera MegaCore Function License
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//Agreement, or other applicable license agreement, including,
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//without limitation, that your use is for the sole purpose of
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//programming logic devices manufactured by Altera and sold by
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//Altera or its authorized distributors. Please refer to the
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//applicable agreement for further details.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module fifo_4k_18 (
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aclr,
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data,
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rdclk,
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rdreq,
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wrclk,
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wrreq,
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q,
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rdempty,
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rdusedw,
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wrfull,
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wrusedw);
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input aclr;
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input [17:0] data;
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input rdclk;
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input rdreq;
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input wrclk;
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input wrreq;
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output [17:0] q;
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output rdempty;
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output [11:0] rdusedw;
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output wrfull;
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output [11:0] wrusedw;
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wire sub_wire0;
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wire [11:0] sub_wire1;
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wire sub_wire2;
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wire [17:0] sub_wire3;
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wire [11:0] sub_wire4;
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wire rdempty = sub_wire0;
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wire [11:0] wrusedw = sub_wire1[11:0];
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wire wrfull = sub_wire2;
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wire [17:0] q = sub_wire3[17:0];
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wire [11:0] rdusedw = sub_wire4[11:0];
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dcfifo dcfifo_component (
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.wrclk (wrclk),
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.rdreq (rdreq),
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.aclr (aclr),
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.rdclk (rdclk),
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.wrreq (wrreq),
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.data (data),
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.rdempty (sub_wire0),
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.wrusedw (sub_wire1),
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.wrfull (sub_wire2),
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.q (sub_wire3),
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.rdusedw (sub_wire4)
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// synopsys translate_off
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,
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.rdfull (),
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.wrempty ()
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// synopsys translate_on
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);
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defparam
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dcfifo_component.add_ram_output_register = "OFF",
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dcfifo_component.clocks_are_synchronized = "FALSE",
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dcfifo_component.intended_device_family = "Cyclone",
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dcfifo_component.lpm_numwords = 4096,
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dcfifo_component.lpm_showahead = "ON",
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dcfifo_component.lpm_type = "dcfifo",
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dcfifo_component.lpm_width = 18,
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dcfifo_component.lpm_widthu = 12,
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dcfifo_component.overflow_checking = "OFF",
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dcfifo_component.underflow_checking = "OFF",
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dcfifo_component.use_eab = "ON";
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
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// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
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// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
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// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
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// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
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// Retrieval info: PRIVATE: Clock NUMERIC "4"
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// Retrieval info: PRIVATE: Depth NUMERIC "4096"
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// Retrieval info: PRIVATE: Empty NUMERIC "1"
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// Retrieval info: PRIVATE: Full NUMERIC "1"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
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// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
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// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
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// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
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// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
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// Retrieval info: PRIVATE: Optimize NUMERIC "2"
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// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
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// Retrieval info: PRIVATE: UsedW NUMERIC "1"
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// Retrieval info: PRIVATE: Width NUMERIC "18"
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// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
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// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
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// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
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// Retrieval info: PRIVATE: output_width NUMERIC "18"
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// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
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// Retrieval info: PRIVATE: rsFull NUMERIC "0"
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// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
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// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
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// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
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// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
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// Retrieval info: PRIVATE: wsFull NUMERIC "1"
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// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
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// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
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// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
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// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
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// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
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// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "18"
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// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
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// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
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// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
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// Retrieval info: CONSTANT: USE_EAB STRING "ON"
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// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
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// Retrieval info: USED_PORT: data 0 0 18 0 INPUT NODEFVAL data[17..0]
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// Retrieval info: USED_PORT: q 0 0 18 0 OUTPUT NODEFVAL q[17..0]
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// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
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// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
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// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
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// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]
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// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
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// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
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// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
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// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]
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// Retrieval info: CONNECT: @data 0 0 18 0 data 0 0 18 0
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// Retrieval info: CONNECT: q 0 0 18 0 @q 0 0 18 0
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// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
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// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
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// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
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// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
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// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
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// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
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// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
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// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
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// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
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// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.inc FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.cmp FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.bsf FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_inst.v FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_bb.v FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_waveforms.html FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_wave*.jpg FALSE
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// Retrieval info: LIB_FILE: altera_mf
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@ -77,5 +77,6 @@ module fifo( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
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assign rdempty = (rdusedw == 0);
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assign rdfull = (rdusedw == depth-1);
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endmodule // fifo_1c_1k
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endmodule // fifo
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@ -0,0 +1,26 @@
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module fifo_4k_18
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(input [17:0] data,
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input wrreq,
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input wrclk,
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output wrfull,
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output wrempty,
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output [11:0] wrusedw,
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output [17:0] q,
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input rdreq,
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input rdclk,
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output rdfull,
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output rdempty,
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output [11:0] rdusedw,
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input aclr );
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fifo #(.width(18),.depth(4096),.addr_bits(12)) fifo_4k
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( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
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rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
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endmodule // fifo_4k_18
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Binary file not shown.
Binary file not shown.
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@ -24,115 +24,147 @@
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// Fifo has 1024 or 2048 lines
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module tx_buffer
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( input usbclk,
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( // USB Side
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input usbclk,
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input bus_reset, // Used here for the 257-Hack to fix the FX2 bug
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input reset, // standard DSP-side reset
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input [15:0] usbdata,
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input wire WR,
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output wire have_space,
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output reg have_space,
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output reg tx_underrun,
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input clear_status,
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// DSP Side
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input txclk,
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input reset, // standard DSP-side reset
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input wire [3:0] channels,
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output reg [15:0] tx_i_0,
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output reg [15:0] tx_q_0,
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output reg [15:0] tx_i_1,
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output reg [15:0] tx_q_1,
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output reg [15:0] tx_i_2,
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output reg [15:0] tx_q_2,
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output reg [15:0] tx_i_3,
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output reg [15:0] tx_q_3,
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input txclk,
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input txstrobe,
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input clear_status,
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output wire tx_empty,
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output [11:0] debugbus
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output [31:0] debugbus
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);
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wire [11:0] txfifolevel;
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reg [8:0] write_count;
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wire tx_full;
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wire [15:0] fifodata;
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wire rdreq;
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reg [3:0] load_next;
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// DAC Side of FIFO
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assign rdreq = ((load_next != channels) & !tx_empty);
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wire [11:0] txfifolevel;
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wire [15:0] fifodata;
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wire rdreq;
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reg [3:0] phase;
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wire sop_f, iq_f;
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reg sop;
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// USB Side of FIFO
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reg [15:0] usbdata_reg;
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reg wr_reg;
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reg [8:0] write_count;
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always @(posedge usbclk)
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have_space <= (txfifolevel < (4092-256)); // be extra conservative
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always @(posedge usbclk)
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begin
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wr_reg <= WR;
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usbdata_reg <= usbdata;
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end
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always @(posedge usbclk)
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if(bus_reset)
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write_count <= 0;
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else if(wr_reg)
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write_count <= write_count + 1;
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else
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write_count <= 0;
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always @(posedge usbclk)
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sop <= WR & ~wr_reg; // Edge detect
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// FIFO
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fifo_4k_18 txfifo
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( // USB Write Side
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.data ( {sop,write_count[0],usbdata_reg} ),
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.wrreq ( wr_reg & ~write_count[8] ),
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.wrclk ( usbclk ),
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.wrfull ( ),
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.wrempty ( ),
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.wrusedw ( txfifolevel ),
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// DSP Read Side
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.q ( {sop_f, iq_f, fifodata} ),
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.rdreq ( rdreq ),
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.rdclk ( txclk ),
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.rdfull ( ),
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.rdempty ( tx_empty ),
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.rdusedw ( ),
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// Async, shared
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.aclr ( reset ) );
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// DAC Side of FIFO
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always @(posedge txclk)
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if(reset)
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begin
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{tx_i_0,tx_q_0,tx_i_1,tx_q_1,tx_i_2,tx_q_2,tx_i_3,tx_q_3}
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<= #1 128'h0;
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load_next <= #1 4'd0;
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{tx_i_0,tx_q_0,tx_i_1,tx_q_1} <= 64'h0;
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phase <= 4'd0;
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end
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else if(phase == channels)
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begin
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if(txstrobe)
|
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phase <= 4'd0;
|
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end
|
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else
|
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if(load_next != channels)
|
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if(~tx_empty)
|
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begin
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load_next <= #1 load_next + 4'd1;
|
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case(load_next)
|
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4'd0 : tx_i_0 <= #1 tx_empty ? 16'd0 : fifodata;
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4'd1 : tx_q_0 <= #1 tx_empty ? 16'd0 : fifodata;
|
||||
4'd2 : tx_i_1 <= #1 tx_empty ? 16'd0 : fifodata;
|
||||
4'd3 : tx_q_1 <= #1 tx_empty ? 16'd0 : fifodata;
|
||||
4'd4 : tx_i_2 <= #1 tx_empty ? 16'd0 : fifodata;
|
||||
4'd5 : tx_q_2 <= #1 tx_empty ? 16'd0 : fifodata;
|
||||
4'd6 : tx_i_3 <= #1 tx_empty ? 16'd0 : fifodata;
|
||||
4'd7 : tx_q_3 <= #1 tx_empty ? 16'd0 : fifodata;
|
||||
endcase // case(load_next)
|
||||
end // if (load_next != channels)
|
||||
else if(txstrobe & (load_next == channels))
|
||||
begin
|
||||
load_next <= #1 4'd0;
|
||||
case(phase)
|
||||
4'd0 : tx_i_0 <= fifodata;
|
||||
4'd1 : tx_q_0 <= fifodata;
|
||||
4'd2 : tx_i_1 <= fifodata;
|
||||
4'd3 : tx_q_1 <= fifodata;
|
||||
endcase // case(phase)
|
||||
phase <= phase + 4'd1;
|
||||
end
|
||||
|
||||
// USB Side of FIFO
|
||||
assign have_space = (txfifolevel <= (4095-256));
|
||||
|
||||
assign rdreq = ((phase != channels) & ~tx_empty);
|
||||
|
||||
// Detect Underruns, cross clock domains
|
||||
reg clear_status_dsp, tx_underrun_dsp;
|
||||
always @(posedge txclk)
|
||||
clear_status_dsp <= clear_status;
|
||||
|
||||
always @(posedge usbclk)
|
||||
if(bus_reset) // Use bus reset because this is on usbclk
|
||||
write_count <= #1 0;
|
||||
else if(WR & ~write_count[8])
|
||||
write_count <= #1 write_count + 9'd1;
|
||||
else
|
||||
write_count <= #1 WR ? write_count : 9'b0;
|
||||
|
||||
// Detect Underruns
|
||||
tx_underrun <= tx_underrun_dsp;
|
||||
|
||||
always @(posedge txclk)
|
||||
if(reset)
|
||||
tx_underrun <= 1'b0;
|
||||
else if(txstrobe & (load_next != channels))
|
||||
tx_underrun <= 1'b1;
|
||||
else if(clear_status)
|
||||
tx_underrun <= 1'b0;
|
||||
tx_underrun_dsp <= 1'b0;
|
||||
else if(txstrobe & (phase != channels))
|
||||
tx_underrun_dsp <= 1'b1;
|
||||
else if(clear_status_dsp)
|
||||
tx_underrun_dsp <= 1'b0;
|
||||
|
||||
// FIFO
|
||||
fifo_4k txfifo
|
||||
( .data ( usbdata ),
|
||||
.wrreq ( WR & ~write_count[8] ),
|
||||
.wrclk ( usbclk ),
|
||||
|
||||
.q ( fifodata ),
|
||||
.rdreq ( rdreq ),
|
||||
.rdclk ( txclk ),
|
||||
|
||||
.aclr ( reset ), // asynch, so we can use either
|
||||
|
||||
.rdempty ( tx_empty ),
|
||||
.rdusedw ( ),
|
||||
.wrfull ( tx_full ),
|
||||
.wrusedw ( txfifolevel )
|
||||
);
|
||||
|
||||
// Debugging Aids
|
||||
assign debugbus[0] = WR;
|
||||
assign debugbus[1] = have_space;
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||||
assign debugbus[2] = tx_empty;
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||||
assign debugbus[3] = tx_full;
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||||
assign debugbus[4] = tx_underrun;
|
||||
assign debugbus[5] = write_count[8];
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||||
assign debugbus[6] = txstrobe;
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||||
assign debugbus[7] = rdreq;
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assign debugbus[11:8] = load_next;
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||||
// TX debug bus
|
||||
//
|
||||
// 15:0 txclk domain => TXA [15:0]
|
||||
// 31:16 usbclk domain => RXA [15:0]
|
||||
|
||||
assign debugbus[0] = reset;
|
||||
assign debugbus[1] = txstrobe;
|
||||
assign debugbus[2] = rdreq;
|
||||
assign debugbus[6:3] = phase;
|
||||
assign debugbus[7] = tx_empty;
|
||||
assign debugbus[8] = tx_underrun_dsp;
|
||||
assign debugbus[9] = iq_f;
|
||||
assign debugbus[10] = sop_f;
|
||||
assign debugbus[14:11] = 0;
|
||||
assign debugbus[15] = txclk;
|
||||
|
||||
assign debugbus[16] = bus_reset;
|
||||
assign debugbus[17] = WR;
|
||||
assign debugbus[18] = wr_reg;
|
||||
assign debugbus[19] = have_space;
|
||||
assign debugbus[20] = write_count[8];
|
||||
assign debugbus[21] = write_count[0];
|
||||
assign debugbus[22] = sop;
|
||||
assign debugbus[23] = tx_underrun;
|
||||
assign debugbus[30:24] = 0;
|
||||
assign debugbus[31] = usbclk;
|
||||
|
||||
endmodule // tx_buffer
|
||||
|
||||
|
|
|
|||
|
|
@ -370,6 +370,7 @@ set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk
|
|||
|
||||
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k_18.v
|
||||
set_global_assignment -name VERILOG_FILE ../../sdr_lib/atr_delay.v
|
||||
set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_dec_shifter.v
|
||||
set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v
|
||||
|
|
@ -381,7 +382,6 @@ set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/ram16_2sum.v
|
|||
set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_rom.v
|
||||
set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/halfband_decim.v
|
||||
set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mac.v
|
||||
set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_ram.v
|
||||
set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_chain.v
|
||||
set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_dcoffset.v
|
||||
set_global_assignment -name VERILOG_FILE ../../sdr_lib/adc_interface.v
|
||||
|
|
|
|||
|
|
@ -93,7 +93,8 @@ module usrp_std
|
|||
wire [2:0] tx_numchan;
|
||||
|
||||
wire [7:0] interp_rate, decim_rate;
|
||||
wire [15:0] tx_debugbus, rx_debugbus;
|
||||
wire [15:0] rx_debugbus;
|
||||
wire [31:0] tx_debugbus;
|
||||
|
||||
wire enable_tx, enable_rx;
|
||||
wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset;
|
||||
|
|
@ -130,18 +131,17 @@ module usrp_std
|
|||
assign bb_tx_q1 = ch3tx;
|
||||
|
||||
tx_buffer tx_buffer
|
||||
( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),
|
||||
.usbdata(usbdata),.WR(WR),.have_space(have_space),.tx_underrun(tx_underrun),
|
||||
( .usbclk(usbclk), .bus_reset(tx_bus_reset),
|
||||
.usbdata(usbdata),.WR(WR), .have_space(have_space),
|
||||
.tx_underrun(tx_underrun), .clear_status(clear_status),
|
||||
.txclk(clk64), .reset(tx_dsp_reset),
|
||||
.channels({tx_numchan,1'b0}),
|
||||
.tx_i_0(ch0tx),.tx_q_0(ch1tx),
|
||||
.tx_i_1(ch2tx),.tx_q_1(ch3tx),
|
||||
.tx_i_2(),.tx_q_2(),
|
||||
.tx_i_3(),.tx_q_3(),
|
||||
.txclk(clk64),.txstrobe(strobe_interp),
|
||||
.clear_status(clear_status),
|
||||
.txstrobe(strobe_interp),
|
||||
.tx_empty(tx_empty),
|
||||
.debugbus(tx_debugbus) );
|
||||
|
||||
|
||||
`ifdef TX_EN_0
|
||||
tx_chain tx_chain_0
|
||||
( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
|
||||
|
|
@ -317,7 +317,7 @@ module usrp_std
|
|||
.rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
|
||||
.tx_empty(tx_empty),
|
||||
//.debug_0(rx_a_a),.debug_1(ddc0_in_i),
|
||||
.debug_0(rx_debugbus),.debug_1(ddc0_in_i),
|
||||
.debug_0(tx_debugbus[15:0]),.debug_1(tx_debugbus[31:16]),
|
||||
.debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,tx_underrun,rx_overrun,decim_rate}),
|
||||
.reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) );
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue