// Registers 64 to 79 are reserved for user custom FPGA builds.
// The standard USRP software will not touch these.
#define FR_USER_0 64
#define FR_USER_1 65
#define FR_USER_2 66
#define FR_USER_3 67
#define FR_USER_4 68
#define FR_USER_5 69
#define FR_USER_6 70
#define FR_USER_7 71
#define FR_USER_8 72
#define FR_USER_9 73
#define FR_USER_10 74
#define FR_USER_11 75
#define FR_USER_12 76
#define FR_USER_13 77
#define FR_USER_14 78
#define FR_USER_15 79
//Registers needed for multi usrp master/slave configuration
//
//Rx Master/slave control register (FR_RX_MASTER_SLAVE = FR_USER_0)
//
#define FR_RX_MASTER_SLAVE 64
#define bitnoFR_RX_SYNC 0
#define bitnoFR_RX_SYNC_MASTER 1
#define bitnoFR_RX_SYNC_SLAVE 2
# define bmFR_RX_SYNC (1 <<bitnoFR_RX_SYNC) //1 If this is a master "sync now" and send sync to slave.
// If this is a slave "sync now" (testing purpose only)
// Sync is allmost the same as reset (clear all counters and buffers)
// except that the io outputs and settings don't get reset (otherwise it couldn't send the sync to the slave)
//0 Normal operation
# define bmFR_RX_SYNC_MASTER (1 <<bitnoFR_RX_SYNC_MASTER) //1 This is a rx sync master, output sync_rx on rx_a_io[15]
//0 This is not a rx sync master
# define bmFR_RX_SYNC_SLAVE (1 <<bitnoFR_RX_SYNC_SLAVE) //1 This is a rx sync slave, follow sync_rx on rx_a_io[bitnoFR_RX_SYNC_INPUT_IOPIN]
//0 This is not an rx sync slave.
//Caution The master settings will output values on the io lines.
//They inheritely enable these lines as output. If you have a daughtercard which uses these lines also as output then you will burn your usrp and daughtercard.
//If you set the slave bits then your usrp won't do anything if you don't connect a master.
// Rx Master/slave control register
//
// The way this is supposed to be used is connecting a (short) 16pin flatcable from an rx daughterboard in RXA master io_rx[8..15] to slave io_rx[8..15] on RXA of slave usrp
// This can be done with basic_rx boards or dbsrx boards
//dbsrx: connect master-J25 to slave-J25
//basic rx: connect J25 to slave-J25
//CAUTION: pay attention to the lineup of your connector.
//The red line (pin1) should be at the same side of the daughterboards on master and slave.
//If you turnaround the cable on one end you will burn your usrp.
//You cannot use a 16pin flatcable if you are using FLEX400 or FLEX2400 daughterboards, since these use a lot of the io pins.
//You can still link them but you must use only a 2pin or 1pin cable
//You can also use a 2-wire link. put a 2pin header on io[15],gnd of the master RXA daughterboard and connect it to io15,gnd of the slave RXA db.
//You can use a cable like the ones found with the leds on the mainbord of a PC.
//Make sure you don't twist the cable, otherwise you connect the sync output to ground.
//To be save you could also just use a single wire from master io[15] to slave io[15], but this is not optimal for signal integrity.
// Since rx_io[0] can normally be used as a refclk and is not exported on all daughterboards this line
// still has the refclk function if you use the master/slave setup (it is not touched by the master/slave settings).
// The master/slave circuitry will only use io pin 15 and does not touch any of the other io pins.