Sylvain Munaut 488bf8a29f gateware/common: Add register stage for the 'ack' and 'rdata' ... This greatly improves timing at the expense of one cycle delay for all wishbone access to peripherals. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>		2020-10-09 13:05:53 +02:00
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fw	gateware: Initial import of all common parts	2020-09-14 10:56:49 +02:00
rtl	gateware/common: Add register stage for the 'ack' and 'rdata'	2020-10-09 13:05:53 +02:00