gateware: Minor syntax fixes
Theses syntax error are ignored by yosys but trying synopsys, it is more strict, so fix them. Right thing to do anyway ... Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
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@ -261,7 +261,7 @@ module soc_base #(
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// Boot memory - 1k
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// Boot memory - 1k
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soc_bram #(
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soc_bram #(
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.AW(8),
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.AW(8),
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.INIT_FILE("boot.hex"),
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.INIT_FILE("boot.hex")
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) bram_I (
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) bram_I (
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.addr (bram_addr),
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.addr (bram_addr),
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.rdata(bram_rdata),
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.rdata(bram_rdata),
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@ -37,7 +37,7 @@ module sysmgr (
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.PIN_TYPE(6'b000001)
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.PIN_TYPE(6'b000001)
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) gb_in (
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) gb_in (
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.PACKAGE_PIN(clk_in),
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.PACKAGE_PIN(clk_in),
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.GLOBAL_BUFFER_OUTPUT(clk_12m_i),
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.GLOBAL_BUFFER_OUTPUT(clk_12m_i)
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);
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);
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// PLL instance
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// PLL instance
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@ -33,10 +33,10 @@ module sysmgr (
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// Global input buffer for 30.72 MHz clock
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// Global input buffer for 30.72 MHz clock
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SB_GB_IO #(
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SB_GB_IO #(
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.PIN_TYPE(6'b000001),
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.PIN_TYPE(6'b000001)
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) gb_in (
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) gb_in (
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.PACKAGE_PIN(clk_in),
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.PACKAGE_PIN(clk_in),
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.GLOBAL_BUFFER_OUTPUT(clk_30m72_i),
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.GLOBAL_BUFFER_OUTPUT(clk_30m72_i)
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);
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);
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// PLL instance
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// PLL instance
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@ -50,7 +50,7 @@ module sysmgr (
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.FDA_FEEDBACK(4'b0000),
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.FDA_FEEDBACK(4'b0000),
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.SHIFTREG_DIV_MODE(2'b00),
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.SHIFTREG_DIV_MODE(2'b00),
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.PLLOUT_SELECT("GENCLK"),
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.PLLOUT_SELECT("GENCLK"),
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.ENABLE_ICEGATE(1'b0),
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.ENABLE_ICEGATE(1'b0)
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) pll_I (
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) pll_I (
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.REFERENCECLK(clk_30m72_i),
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.REFERENCECLK(clk_30m72_i),
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.PLLOUTCORE(),
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.PLLOUTCORE(),
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@ -75,7 +75,7 @@ module led_blinker (
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// Per-led
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// Per-led
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always @(*)
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always @(*)
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begin : led_state
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begin : led_state_proc
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integer i;
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integer i;
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for (i=0; i<4; i=i+1)
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for (i=0; i<4; i=i+1)
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led[i] = led_state[2*i+1] ? (led_state[2*i] ? blink_fast : blink_slow) : led_state[2*i];
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led[i] = led_state[2*i+1] ? (led_state[2*i] ? blink_fast : blink_slow) : led_state[2*i];
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@ -33,10 +33,10 @@ module sysmgr (
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// Global input buffer for 30.72 MHz clock
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// Global input buffer for 30.72 MHz clock
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SB_GB_IO #(
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SB_GB_IO #(
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.PIN_TYPE(6'b000001),
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.PIN_TYPE(6'b000001)
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) gb_in (
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) gb_in (
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.PACKAGE_PIN(clk_in),
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.PACKAGE_PIN(clk_in),
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.GLOBAL_BUFFER_OUTPUT(clk_30m72_i),
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.GLOBAL_BUFFER_OUTPUT(clk_30m72_i)
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);
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);
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// PLL instance
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// PLL instance
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@ -50,7 +50,7 @@ module sysmgr (
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.FDA_FEEDBACK(4'b0000),
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.FDA_FEEDBACK(4'b0000),
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.SHIFTREG_DIV_MODE(2'b00),
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.SHIFTREG_DIV_MODE(2'b00),
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.PLLOUT_SELECT("GENCLK"),
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.PLLOUT_SELECT("GENCLK"),
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.ENABLE_ICEGATE(1'b0),
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.ENABLE_ICEGATE(1'b0)
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) pll_I (
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) pll_I (
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.REFERENCECLK(clk_30m72_i),
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.REFERENCECLK(clk_30m72_i),
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.PLLOUTCORE(),
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.PLLOUTCORE(),
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