Commit Graph

14 Commits

Author SHA1 Message Date
Zang Roy-r61911 63247a5acd u-boot: v2: Remove the fixed TLB and LAW entrynubmer
Remove the fixed TLB and LAW entry nubmer. Use actually TLB and LAW
entry number to control the loop.  This can reduce the potential risk
for the 85xx processor increasing its TLB adn LAW entry number.

Signed-off-by: Swarthout Edward <swarthout@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
2007-04-23 19:58:27 -05:00
Wolfgang Denk b38dbd4622 Fix bug in [id]cache_status commands for MPC85xx processors;
should look at LSB of L1CSRn registers to determine if L1 cache is
enabled, not the MSB.
Patch by Murray Jensen, 19 Jul 2005
2006-03-13 00:46:05 +01:00
Wolfgang Denk 99b0d2851a Added support for KwikByte KB920x boards (based on AT91RM9200)
Patch by Matt ?? <kb9200_dev@kwikbyte.com>, 27 Apr 2005
2005-10-05 00:19:34 +02:00
Wolfgang Denk 7d314992a8 E500 update: repoint IVPR to RAM when code is relocated
Patch by Kylo Ginsberg, 13 Apr 2005
2005-10-05 00:00:54 +02:00
Wolfgang Denk cbf9c11728 Merge with /home/wd/git/u-boot/master 2005-08-05 11:22:28 +02:00
Wolfgang Denk 3e0bc4473a Fix typos in cpu/85xx/start.S which caused DataTLB exception to be
routed to the Watchdog handler
Patch by Eugene Surovegin, 18 Jun 2005
2005-08-04 01:24:19 +02:00
Lunsheng Wang b0e3294923 * Patch by Ron Alder, 11 July 2005
Add Xianghua Xiao and Lunsheng Wang's support for the
    GDA MPC8540 EVAL board.
2005-07-29 10:20:29 -05:00
Jon Loeliger d9b94f28a4 * Patch by Jon Loeliger, 2005-05-05
Implemented support for MPC8548CDS board.
  Added DDR II support based on SPD values for MPC85xx boards.
  This roll-up patch also includes bugfies for the previously
  published patches:
    DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O
2005-07-25 14:05:07 -05:00
wdenk 343117bf12 Fix timer handling on MPC85xx systems 2005-05-13 22:49:36 +00:00
wdenk 9aea95307f Patch by Jon Loeliger, 16 Jul 2004:
- support larger DDR memories up to 2G on the PC8540/8560ADS and
  STXGP3 boards
- Made MPC8540/8560ADS be 33Mhz PCI by default.
- Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16
  and CONFIG_L2_INIT_RAM options.
- Refactor Local Bus initialization out of SDRAM setup.
- Re-implement new version of LBC11/DDR11 errata workarounds.
- Moved board specific PCI init parts out of CPU directory.
- Added TLB entry for PCI-1 IO Memory
- Updated README.mpc85xxads
2004-08-01 23:02:45 +00:00
wdenk 0ac6f8b749 Patch by Jon Loeliger, 17 June 2004:
Completion of the 8540ADS/8560ADS updates:
Fix some PCI and Rapid I/O memory maps,
Initialize both TSEC 1 and 2,
Initialize SDRAM
Update MAINTAINER for 85xx boards and README.mpc85xxads
2004-07-09 23:27:13 +00:00
wdenk 97d80fc391 Patches Part 1 by Jon Loeliger, 11 May 2004:
Dynamically handle REV1 and REV2 MPC85xx parts.
  (Jon Loeliger, 10-May-2004).
New consistent memory map and Local Access Window across MPC85xx line.
New CCSRBAR at 0xE000_0000 now.
Add RAPID I/O memory map.
New memory map in README.MPC85xxads
  (Kumar Gala, 10-May-2004)
Better board and CPU identification on MPC85xx boards at boot.
  (Jon Loeliger, 10-May-2004)
SDRAM clock control fixes on MPC8540ADS & MPC8560 boards.
Some configuration options for MPC8540ADS & MPC8560ADS cleaned up.
  (Jim Robertson, 10-May-2004)
Rewrite of the MPC85xx Three Speed Ethernet Controller (TSEC) driver.
Supports multiple PHYs.
  (Andy Fleming, 10-May-2004)
Some README.MPC85xxads updates.
  (Kumar Gala, 10-May-2004)
Copyright updates for "Freescale"
  (Andy Fleming, 10-May-2004)
2004-06-09 00:34:46 +00:00
wdenk a57a496f4d * Patch by Xiao Xianghua, 23 Oct 2003:
small patch for mpc85xx

* Fix small problem in MPC5200 I2C driver

* Fix FCC3 support on ATC board
2003-10-26 22:52:58 +00:00
wdenk 42d1f0394b * Patches by Xianghua Xiao, 15 Oct 2003:
- Added Motorola CPU 8540/8560 support (cpu/85xx)
  - Added Motorola MPC8540ADS board support (board/mpc8540ads)
  - Added Motorola MPC8560ADS board support (board/mpc8560ads)

* Minor code cleanup
2003-10-15 23:53:47 +00:00