Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx
This commit is contained in:
Wolfgang Denk
commit
e1e3cf7c79
|
|
@ -428,6 +428,7 @@ Heiko Schocher <hs@denx.de>
|
|||
sc3 PPC405GP
|
||||
suen3 ARM926EJS (Kirkwood SoC)
|
||||
uc101 MPC5200
|
||||
ve8313 MPC8313
|
||||
|
||||
Peter De Schrijver <p2@mind.be>
|
||||
|
||||
|
|
@ -490,6 +491,10 @@ Stephen Williams <steve@icarus.com>
|
|||
|
||||
JSE PPC405GPr
|
||||
|
||||
Ilya Yanok <yanok@emcraft.com>
|
||||
|
||||
MPC8308RDB MPC8308
|
||||
|
||||
Roy Zang <tie-fei.zang@freescale.com>
|
||||
|
||||
mpc7448hpc2 MPC7448
|
||||
|
|
|
|||
2
MAKEALL
2
MAKEALL
|
|
@ -360,6 +360,7 @@ LIST_8260=" \
|
|||
LIST_83xx=" \
|
||||
caddy2 \
|
||||
kmeter1 \
|
||||
MPC8308RDB \
|
||||
MPC8313ERDB_33 \
|
||||
MPC8313ERDB_NAND_66 \
|
||||
MPC8315ERDB \
|
||||
|
|
@ -380,6 +381,7 @@ LIST_83xx=" \
|
|||
sbc8349 \
|
||||
SIMPC8313_LP \
|
||||
TQM834x \
|
||||
ve8313 \
|
||||
vme8349 \
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||||
"
|
||||
|
||||
|
|
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|||
|
|
@ -55,6 +55,7 @@ int checkcpu(void)
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|||
char name[15];
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||||
u32 partid;
|
||||
} cpu_type_list [] = {
|
||||
CPU_TYPE_ENTRY(8308),
|
||||
CPU_TYPE_ENTRY(8311),
|
||||
CPU_TYPE_ENTRY(8313),
|
||||
CPU_TYPE_ENTRY(8314),
|
||||
|
|
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|||
|
|
@ -100,7 +100,8 @@ int get_clocks(void)
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|||
u32 lcrr;
|
||||
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||||
u32 csb_clk;
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||||
#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
|
||||
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
|
||||
defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
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||||
u32 tsec1_clk;
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||||
u32 tsec2_clk;
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||||
u32 usbdr_clk;
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||||
|
|
@ -132,7 +133,8 @@ int get_clocks(void)
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|||
u32 qe_clk;
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||||
u32 brg_clk;
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||||
#endif
|
||||
#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC831x)
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||||
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
|
||||
defined(CONFIG_MPC837x)
|
||||
u32 pciexp1_clk;
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||||
u32 pciexp2_clk;
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||||
#endif
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||||
|
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@ -164,7 +166,8 @@ int get_clocks(void)
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|||
|
||||
sccr = im->clk.sccr;
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||||
|
||||
#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
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||||
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
|
||||
defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
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||||
switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
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||||
case 0:
|
||||
tsec1_clk = 0;
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||||
|
|
@ -202,7 +205,8 @@ int get_clocks(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
|
||||
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) || \
|
||||
defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
|
||||
switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
|
||||
case 0:
|
||||
tsec2_clk = 0;
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||||
|
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@ -319,7 +323,7 @@ int get_clocks(void)
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|||
i2c1_clk = csb_clk;
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||||
#elif defined(CONFIG_MPC832x)
|
||||
i2c1_clk = enc_clk;
|
||||
#elif defined(CONFIG_MPC831x)
|
||||
#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
|
||||
i2c1_clk = enc_clk;
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||||
#elif defined(CONFIG_FSL_ESDHC)
|
||||
i2c1_clk = sdhc_clk;
|
||||
|
|
@ -328,7 +332,8 @@ int get_clocks(void)
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|||
i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC831x)
|
||||
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
|
||||
defined(CONFIG_MPC837x)
|
||||
switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
|
||||
case 0:
|
||||
pciexp1_clk = 0;
|
||||
|
|
@ -444,7 +449,8 @@ int get_clocks(void)
|
|||
#endif
|
||||
|
||||
gd->csb_clk = csb_clk;
|
||||
#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
|
||||
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
|
||||
defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
|
||||
gd->tsec1_clk = tsec1_clk;
|
||||
gd->tsec2_clk = tsec2_clk;
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||||
gd->usbdr_clk = usbdr_clk;
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||||
|
|
@ -525,7 +531,8 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
|
|||
#if defined(CONFIG_FSL_ESDHC)
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||||
printf(" SDHC: %-4s MHz\n", strmhz(buf, gd->sdhc_clk));
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||||
#endif
|
||||
#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
|
||||
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
|
||||
defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
|
||||
printf(" TSEC1: %-4s MHz\n", strmhz(buf, gd->tsec1_clk));
|
||||
printf(" TSEC2: %-4s MHz\n", strmhz(buf, gd->tsec2_clk));
|
||||
printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
|
||||
|
|
|
|||
|
|
@ -60,7 +60,8 @@ typedef struct global_data {
|
|||
#if defined(CONFIG_MPC83xx)
|
||||
/* There are other clocks in the MPC83XX */
|
||||
u32 csb_clk;
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||||
#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
|
||||
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
|
||||
defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
|
||||
u32 tsec1_clk;
|
||||
u32 tsec2_clk;
|
||||
u32 usbdr_clk;
|
||||
|
|
@ -76,7 +77,8 @@ typedef struct global_data {
|
|||
u32 lbiu_clk;
|
||||
u32 lclk_clk;
|
||||
u32 pci_clk;
|
||||
#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC831x)
|
||||
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
|
||||
defined(CONFIG_MPC837x)
|
||||
u32 pciexp1_clk;
|
||||
u32 pciexp2_clk;
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -73,7 +73,11 @@ typedef struct sysconf83xx {
|
|||
u32 obir; /* Output Buffer Impedance Register */
|
||||
u8 res8[0xC];
|
||||
u32 pecr1; /* PCI Express control register 1 */
|
||||
#ifdef CONFIG_MPC8308
|
||||
u32 sdhccr; /* eSDHC Control Registers for MPC8308 */
|
||||
#else
|
||||
u32 pecr2; /* PCI Express control register 2 */
|
||||
#endif
|
||||
u8 res9[0xB8];
|
||||
} sysconf83xx_t;
|
||||
|
||||
|
|
@ -589,7 +593,14 @@ typedef struct sdhc83xx {
|
|||
* SerDes
|
||||
*/
|
||||
typedef struct serdes83xx {
|
||||
u8 fixme[0x100];
|
||||
u32 srdscr0;
|
||||
u32 srdscr1;
|
||||
u32 srdscr2;
|
||||
u32 srdscr3;
|
||||
u32 srdscr4;
|
||||
u8 res0[0xc];
|
||||
u32 srdsrstctl;
|
||||
u8 res1[0xdc];
|
||||
} serdes83xx_t;
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||||
|
||||
/*
|
||||
|
|
@ -691,7 +702,7 @@ typedef struct immap {
|
|||
u8 res7[0xC0000];
|
||||
} immap_t;
|
||||
|
||||
#elif defined(CONFIG_MPC8315)
|
||||
#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
|
||||
typedef struct immap {
|
||||
sysconf83xx_t sysconf; /* System configuration */
|
||||
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
|
||||
|
|
|
|||
|
|
@ -27,9 +27,10 @@
|
|||
|
||||
#include <asm/types.h>
|
||||
|
||||
#if defined(CONFIG_MPC834x) || \
|
||||
#if defined(CONFIG_MPC8308) || \
|
||||
defined(CONFIG_MPC8313) || \
|
||||
defined(CONFIG_MPC8315) || \
|
||||
defined(CONFIG_MPC834x) || \
|
||||
defined(CONFIG_MPC837x)
|
||||
|
||||
typedef struct spi8xxx {
|
||||
|
|
|
|||
|
|
@ -0,0 +1,52 @@
|
|||
#
|
||||
# (C) Copyright 2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
# (C) Copyright 2010
|
||||
# Ilya Yanok, Emcraft Systems, yanok@emcraft.com
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := $(BOARD).o sdram.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1 @@
|
|||
TEXT_BASE = 0xFE000000
|
||||
|
|
@ -0,0 +1,160 @@
|
|||
/*
|
||||
* Copyright (C) 2010 Freescale Semiconductor, Inc.
|
||||
* Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <hwconfig.h>
|
||||
#include <i2c.h>
|
||||
#include <libfdt.h>
|
||||
#include <fdt_support.h>
|
||||
#include <pci.h>
|
||||
#include <mpc83xx.h>
|
||||
#include <vsc7385.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/fsl_serdes.h>
|
||||
#include <asm/fsl_mpc83xx_serdes.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
|
||||
|
||||
if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF)
|
||||
gd->flags |= GD_FLG_SILENT;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u8 read_board_info(void)
|
||||
{
|
||||
u8 val8;
|
||||
i2c_set_bus_num(0);
|
||||
|
||||
if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
|
||||
return val8;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
static const char * const rev_str[] = {
|
||||
"1.0",
|
||||
"<reserved>",
|
||||
"<reserved>",
|
||||
"<reserved>",
|
||||
"<unknown>",
|
||||
};
|
||||
u8 info;
|
||||
int i;
|
||||
|
||||
info = read_board_info();
|
||||
i = (!info) ? 4 : info & 0x03;
|
||||
|
||||
printf("Board: Freescale MPC8308RDB Rev %s\n", rev_str[i]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct pci_region pcie_regions_0[] = {
|
||||
{
|
||||
.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
|
||||
.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
|
||||
.size = CONFIG_SYS_PCIE1_MEM_SIZE,
|
||||
.flags = PCI_REGION_MEM,
|
||||
},
|
||||
{
|
||||
.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
|
||||
.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
|
||||
.size = CONFIG_SYS_PCIE1_IO_SIZE,
|
||||
.flags = PCI_REGION_IO,
|
||||
},
|
||||
};
|
||||
|
||||
void pci_init_board(void)
|
||||
{
|
||||
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
|
||||
sysconf83xx_t *sysconf = &immr->sysconf;
|
||||
clk83xx_t *clk = (clk83xx_t *)&immr->clk;
|
||||
law83xx_t *pcie_law = sysconf->pcielaw;
|
||||
struct pci_region *pcie_reg[] = { pcie_regions_0 };
|
||||
|
||||
fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
|
||||
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
|
||||
|
||||
clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM ,
|
||||
SCCR_PCIEXP1CM_1);
|
||||
|
||||
/* Deassert the resets in the control register */
|
||||
out_be32(&sysconf->pecr1, 0xE0008000);
|
||||
udelay(2000);
|
||||
|
||||
/* Configure PCI Express Local Access Windows */
|
||||
out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
|
||||
out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
|
||||
|
||||
mpc83xx_pcie_init(1, pcie_reg, 0);
|
||||
}
|
||||
/*
|
||||
* Miscellaneous late-boot configurations
|
||||
*
|
||||
* If a VSC7385 microcode image is present, then upload it.
|
||||
*/
|
||||
int misc_init_r(void)
|
||||
{
|
||||
#ifdef CONFIG_VSC7385_IMAGE
|
||||
if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
|
||||
CONFIG_VSC7385_IMAGE_SIZE)) {
|
||||
puts("Failure uploading VSC7385 microcode.\n");
|
||||
return 1;
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
ft_cpu_setup(blob, bd);
|
||||
fdt_fixup_dr_usb(blob, bd);
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int rv, num_if = 0;
|
||||
|
||||
/* Initialize TSECs first */
|
||||
if ((rv = cpu_eth_init(bis)) >= 0)
|
||||
num_if += rv;
|
||||
else
|
||||
printf("ERROR: failed to initialize TSECs.\n");
|
||||
|
||||
if ((rv = pci_eth_init(bis)) >= 0)
|
||||
num_if += rv;
|
||||
else
|
||||
printf("ERROR: failed to initialize PCI Ethernet.\n");
|
||||
|
||||
return num_if;
|
||||
}
|
||||
|
|
@ -0,0 +1,126 @@
|
|||
/*
|
||||
* Copyright (C) 2007 Freescale Semiconductor, Inc.
|
||||
* Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
|
||||
*
|
||||
* Authors: Nick.Spence@freescale.com
|
||||
* Wilson.Lo@freescale.com
|
||||
* scottwood@freescale.com
|
||||
*
|
||||
* This files is mostly identical to the original from
|
||||
* board\freescale\mpc8315erdb\sdram.c
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <mpc83xx.h>
|
||||
|
||||
#include <asm/bitops.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#include <asm/processor.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static void resume_from_sleep(void)
|
||||
{
|
||||
u32 magic = *(u32 *)0;
|
||||
|
||||
typedef void (*func_t)(void);
|
||||
func_t resume = *(func_t *)4;
|
||||
|
||||
if (magic == 0xf5153ae5)
|
||||
resume();
|
||||
|
||||
gd->flags &= ~GD_FLG_SILENT;
|
||||
puts("\nResume from sleep failed: bad magic word\n");
|
||||
}
|
||||
|
||||
/* Fixed sdram init -- doesn't use serial presence detect.
|
||||
*
|
||||
* This is useful for faster booting in configs where the RAM is unlikely
|
||||
* to be changed, or for things like NAND booting where space is tight.
|
||||
*/
|
||||
static long fixed_sdram(void)
|
||||
{
|
||||
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
|
||||
u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
|
||||
u32 msize_log2 = __ilog2(msize);
|
||||
|
||||
out_be32(&im->sysconf.ddrlaw[0].bar,
|
||||
CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000);
|
||||
out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
|
||||
out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
|
||||
|
||||
/*
|
||||
* Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
|
||||
* or the DDR2 controller may fail to initialize correctly.
|
||||
*/
|
||||
udelay(50000);
|
||||
|
||||
out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
|
||||
out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
|
||||
|
||||
/* Currently we use only one CS, so disable the other bank. */
|
||||
out_be32(&im->ddr.cs_config[1], 0);
|
||||
|
||||
out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
|
||||
out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
|
||||
out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
|
||||
out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
|
||||
out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
|
||||
|
||||
if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF) {
|
||||
out_be32(&im->ddr.sdram_cfg,
|
||||
CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI);
|
||||
} else {
|
||||
out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
|
||||
}
|
||||
|
||||
out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
|
||||
out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
|
||||
out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
|
||||
|
||||
out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
|
||||
sync();
|
||||
|
||||
/* enable DDR controller */
|
||||
setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
|
||||
sync();
|
||||
|
||||
return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
|
||||
}
|
||||
|
||||
phys_size_t initdram(int board_type)
|
||||
{
|
||||
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
|
||||
u32 msize;
|
||||
|
||||
if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
|
||||
return -1;
|
||||
|
||||
/* DDR SDRAM */
|
||||
msize = fixed_sdram();
|
||||
|
||||
if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF)
|
||||
resume_from_sleep();
|
||||
|
||||
/* return total bus SDRAM size(bytes) -- DDR */
|
||||
return msize;
|
||||
}
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
#
|
||||
# (C) Copyright 2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := $(BOARD).o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
ifndef NAND_SPL
|
||||
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
|
||||
endif
|
||||
|
||||
ifndef TEXT_BASE
|
||||
TEXT_BASE = 0xfe000000
|
||||
endif
|
||||
|
|
@ -0,0 +1,215 @@
|
|||
/*
|
||||
* Copyright (C) Freescale Semiconductor, Inc. 2006-2007
|
||||
*
|
||||
* Author: Scott Wood <scottwood@freescale.com>
|
||||
*
|
||||
* (C) Copyright 2010
|
||||
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <libfdt.h>
|
||||
#include <pci.h>
|
||||
#include <mpc83xx.h>
|
||||
#include <ns16550.h>
|
||||
#include <nand.h>
|
||||
|
||||
#include <asm/bitops.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
extern void disable_addr_trans (void);
|
||||
extern void enable_addr_trans (void);
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: ve8313\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static long fixed_sdram(void)
|
||||
{
|
||||
u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
|
||||
|
||||
#ifndef CONFIG_SYS_RAMBOOT
|
||||
volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
|
||||
u32 msize_log2 = __ilog2(msize);
|
||||
|
||||
out_be32(&im->sysconf.ddrlaw[0].bar,
|
||||
(CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000));
|
||||
out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1)));
|
||||
out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
|
||||
|
||||
/*
|
||||
* Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
|
||||
* or the DDR2 controller may fail to initialize correctly.
|
||||
*/
|
||||
__udelay(50000);
|
||||
|
||||
out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
|
||||
out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CONFIG);
|
||||
|
||||
/* Currently we use only one CS, so disable the other bank. */
|
||||
out_be32(&im->ddr.cs_config[1], 0);
|
||||
|
||||
out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
|
||||
out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
|
||||
out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
|
||||
out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
|
||||
out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
|
||||
|
||||
out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);
|
||||
|
||||
out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);
|
||||
out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
|
||||
out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);
|
||||
|
||||
out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
|
||||
sync();
|
||||
|
||||
/* enable DDR controller */
|
||||
setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
|
||||
|
||||
/* now check the real size */
|
||||
disable_addr_trans ();
|
||||
msize = get_ram_size (CONFIG_SYS_DDR_BASE, msize);
|
||||
enable_addr_trans ();
|
||||
#endif
|
||||
|
||||
return msize;
|
||||
}
|
||||
|
||||
phys_size_t initdram(int board_type)
|
||||
{
|
||||
volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
|
||||
volatile fsl_lbus_t *lbc = &im->lbus;
|
||||
u32 msize;
|
||||
|
||||
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
|
||||
return -1;
|
||||
|
||||
/* DDR SDRAM - Main SODIMM */
|
||||
msize = fixed_sdram();
|
||||
|
||||
/* Local Bus setup lbcr and mrtpr */
|
||||
out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
|
||||
out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
|
||||
sync();
|
||||
|
||||
/* return total bus SDRAM size(bytes) -- DDR */
|
||||
return msize;
|
||||
}
|
||||
|
||||
#define VE8313_WDT_EN 0x00020000
|
||||
#define VE8313_WDT_TRIG 0x00040000
|
||||
|
||||
int board_early_init_f (void)
|
||||
{
|
||||
volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
|
||||
volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;
|
||||
|
||||
#if defined(CONFIG_HW_WATCHDOG)
|
||||
/* enable WDT */
|
||||
clrbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG);
|
||||
#else
|
||||
/* disable WDT */
|
||||
setbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG);
|
||||
#endif
|
||||
/* set WDT pins as output */
|
||||
setbits_be32(&gpio->dir, VE8313_WDT_EN | VE8313_WDT_TRIG);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_HW_WATCHDOG)
|
||||
void hw_watchdog_reset(void)
|
||||
{
|
||||
volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
|
||||
volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;
|
||||
unsigned long reg;
|
||||
|
||||
reg = in_be32(&gpio->dat);
|
||||
if (reg & VE8313_WDT_TRIG)
|
||||
clrbits_be32(&gpio->dat, VE8313_WDT_TRIG);
|
||||
else
|
||||
setbits_be32(&gpio->dat, VE8313_WDT_TRIG);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
static struct pci_region pci_regions[] = {
|
||||
{
|
||||
bus_start: CONFIG_SYS_PCI1_MEM_BASE,
|
||||
phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
|
||||
size: CONFIG_SYS_PCI1_MEM_SIZE,
|
||||
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
|
||||
},
|
||||
{
|
||||
bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
|
||||
phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
|
||||
size: CONFIG_SYS_PCI1_MMIO_SIZE,
|
||||
flags: PCI_REGION_MEM
|
||||
},
|
||||
{
|
||||
bus_start: CONFIG_SYS_PCI1_IO_BASE,
|
||||
phys_start: CONFIG_SYS_PCI1_IO_PHYS,
|
||||
size: CONFIG_SYS_PCI1_IO_SIZE,
|
||||
flags: PCI_REGION_IO
|
||||
}
|
||||
};
|
||||
|
||||
void pci_init_board(void)
|
||||
{
|
||||
volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
|
||||
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
|
||||
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
|
||||
struct pci_region *reg[] = { pci_regions };
|
||||
int warmboot;
|
||||
|
||||
/* Enable all 3 PCI_CLK_OUTPUTs. */
|
||||
setbits_be32(&clk->occr, 0xe0000000);
|
||||
|
||||
/*
|
||||
* Configure PCI Local Access Windows
|
||||
*/
|
||||
out_be32(&pci_law[0].bar, CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR);
|
||||
out_be32(&pci_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
|
||||
|
||||
out_be32(&pci_law[1].bar, CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR);
|
||||
out_be32(&pci_law[1].ar, LBLAWAR_EN | LBLAWAR_1MB);
|
||||
|
||||
warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM;
|
||||
|
||||
mpc83xx_pci_init(1, reg, warmboot);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
ft_cpu_setup(blob, bd);
|
||||
#ifdef CONFIG_PCI
|
||||
ft_pci_setup(blob, bd);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
|
@ -132,6 +132,7 @@ ZPC1900 powerpc mpc8260 zpc1900
|
|||
mgcoge powerpc mpc8260 - keymile
|
||||
SCM powerpc mpc8260 - siemens
|
||||
TQM8272 powerpc mpc8260 tqm8272 tqc
|
||||
ve8313 powerpc mpc83xx ve8313
|
||||
kmeter1 powerpc mpc83xx kmeter1 keymile
|
||||
MVBLM7 powerpc mpc83xx mvblm7 matrix_vision
|
||||
TQM834x powerpc mpc83xx tqm834x tqc
|
||||
|
|
@ -332,6 +333,7 @@ ppmc8260 powerpc mpc8260
|
|||
RPXsuper powerpc mpc8260 rpxsuper
|
||||
rsdproto powerpc mpc8260
|
||||
MPC8266ADS powerpc mpc8260 mpc8266ads freescale
|
||||
MPC8308RDB powerpc mpc83xx mpc8308rdb freescale
|
||||
MPC8323ERDB powerpc mpc83xx mpc8323erdb freescale
|
||||
MPC8349EMDS powerpc mpc83xx mpc8349emds freescale
|
||||
MPC837XERDB powerpc mpc83xx mpc837xerdb freescale
|
||||
|
|
|
|||
|
|
@ -0,0 +1,560 @@
|
|||
/*
|
||||
* Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
|
||||
* Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
|
||||
*
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
*/
|
||||
#define CONFIG_E300 1 /* E300 family */
|
||||
#define CONFIG_MPC83xx 1 /* MPC83xx family */
|
||||
#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
|
||||
#define CONFIG_MPC8308RDB 1 /* MPC8308RDB board specific */
|
||||
|
||||
#define CONFIG_MISC_INIT_R
|
||||
|
||||
/*
|
||||
* On-board devices
|
||||
*
|
||||
* TSEC1 is SoC TSEC
|
||||
* TSEC2 is VSC switch
|
||||
*/
|
||||
#define CONFIG_TSEC1
|
||||
#define CONFIG_VSC7385_ENET
|
||||
|
||||
/*
|
||||
* System Clock Setup
|
||||
*/
|
||||
#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
|
||||
#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
|
||||
|
||||
/*
|
||||
* Hardware Reset Configuration Word
|
||||
* if CLKIN is 66.66MHz, then
|
||||
* CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
|
||||
* We choose the A type silicon as default, so the core is 400Mhz.
|
||||
*/
|
||||
#define CONFIG_SYS_HRCW_LOW (\
|
||||
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
|
||||
HRCWL_DDR_TO_SCB_CLK_2X1 |\
|
||||
HRCWL_SVCOD_DIV_2 |\
|
||||
HRCWL_CSB_TO_CLKIN_4X1 |\
|
||||
HRCWL_CORE_TO_CSB_3X1)
|
||||
/*
|
||||
* There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
|
||||
* in 8308's HRCWH according to the manual, but original Freescale's
|
||||
* code has them and I've expirienced some problems using the board
|
||||
* with BDI3000 attached when I've tried to set these bits to zero
|
||||
* (UART doesn't work after the 'reset run' command).
|
||||
*/
|
||||
#define CONFIG_SYS_HRCW_HIGH (\
|
||||
HRCWH_PCI_HOST |\
|
||||
HRCWH_PCI1_ARBITER_ENABLE |\
|
||||
HRCWH_CORE_ENABLE |\
|
||||
HRCWH_FROM_0X00000100 |\
|
||||
HRCWH_BOOTSEQ_DISABLE |\
|
||||
HRCWH_SW_WATCHDOG_DISABLE |\
|
||||
HRCWH_ROM_LOC_LOCAL_16BIT |\
|
||||
HRCWH_RL_EXT_LEGACY |\
|
||||
HRCWH_TSEC1M_IN_RGMII |\
|
||||
HRCWH_TSEC2M_IN_RGMII |\
|
||||
HRCWH_BIG_ENDIAN)
|
||||
|
||||
/*
|
||||
* System IO Config
|
||||
*/
|
||||
#define CONFIG_SYS_SICRH 0x01b7d103
|
||||
#define CONFIG_SYS_SICRL 0x00000040 /* 3.3V, no delay */
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
|
||||
|
||||
/*
|
||||
* IMMR new address
|
||||
*/
|
||||
#define CONFIG_SYS_IMMR 0xE0000000
|
||||
|
||||
/*
|
||||
* SERDES
|
||||
*/
|
||||
#define CONFIG_FSL_SERDES
|
||||
#define CONFIG_FSL_SERDES1 0xe3000
|
||||
|
||||
/*
|
||||
* Arbiter Setup
|
||||
*/
|
||||
#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
|
||||
#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
|
||||
#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
|
||||
|
||||
/*
|
||||
* DDR Setup
|
||||
*/
|
||||
#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
|
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
|
||||
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
|
||||
#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
|
||||
| DDRCDR_PZ_LOZ \
|
||||
| DDRCDR_NZ_LOZ \
|
||||
| DDRCDR_ODT \
|
||||
| DDRCDR_Q_DRN)
|
||||
/* 0x7b880001 */
|
||||
/*
|
||||
* Manually set up DDR parameters
|
||||
* consist of two chips HY5PS12621BFP-C4 from HYNIX
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_DDR_SIZE 128 /* MB */
|
||||
|
||||
#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
|
||||
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
|
||||
| 0x00010000 /* ODT_WR to CSn */ \
|
||||
| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
|
||||
/* 0x80010102 */
|
||||
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
|
||||
#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
|
||||
| (0 << TIMING_CFG0_WRT_SHIFT) \
|
||||
| (0 << TIMING_CFG0_RRT_SHIFT) \
|
||||
| (0 << TIMING_CFG0_WWT_SHIFT) \
|
||||
| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
|
||||
| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
|
||||
| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
|
||||
| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
|
||||
/* 0x00220802 */
|
||||
#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
|
||||
| (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
|
||||
| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
|
||||
| (5 << TIMING_CFG1_CASLAT_SHIFT) \
|
||||
| (6 << TIMING_CFG1_REFREC_SHIFT) \
|
||||
| (2 << TIMING_CFG1_WRREC_SHIFT) \
|
||||
| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
|
||||
| (2 << TIMING_CFG1_WRTORD_SHIFT))
|
||||
/* 0x27256222 */
|
||||
#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
|
||||
| (4 << TIMING_CFG2_CPO_SHIFT) \
|
||||
| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
|
||||
| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
|
||||
| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
|
||||
| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
|
||||
| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
|
||||
/* 0x121048c5 */
|
||||
#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
|
||||
| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
|
||||
/* 0x03600100 */
|
||||
#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
|
||||
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
|
||||
| SDRAM_CFG_32_BE)
|
||||
/* 0x43080000 */
|
||||
|
||||
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
|
||||
#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
|
||||
| (0x0232 << SDRAM_MODE_SD_SHIFT))
|
||||
/* ODT 150ohm CL=3, AL=1 on SDRAM */
|
||||
#define CONFIG_SYS_DDR_MODE2 0x00000000
|
||||
|
||||
/*
|
||||
* Memory test
|
||||
*/
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x07f00000
|
||||
|
||||
/*
|
||||
* The reserved memory
|
||||
*/
|
||||
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
|
||||
#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
|
||||
|
||||
/*
|
||||
* Initial RAM Base Address Setup
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK 1
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
|
||||
#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
|
||||
|
||||
/*
|
||||
* Local Bus Configuration & Clock Setup
|
||||
*/
|
||||
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
|
||||
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
|
||||
#define CONFIG_SYS_LBC_LBCR 0x00040000
|
||||
|
||||
/*
|
||||
* FLASH on the Local Bus
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
|
||||
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
|
||||
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
|
||||
|
||||
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
|
||||
#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
|
||||
#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
|
||||
|
||||
/* Window base at flash base */
|
||||
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8MB window size */
|
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM (\
|
||||
CONFIG_SYS_FLASH_BASE /* Flash Base address */ |\
|
||||
(2 << BR_PS_SHIFT) /* 16 bit port size */ |\
|
||||
BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
|
||||
| OR_UPM_XAM \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_ACS_DIV2 \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_TRLX \
|
||||
| OR_GPCM_EHTR \
|
||||
| OR_GPCM_EAD)
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
/* 127 64KB sectors and 8 8KB top sectors per device */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 135
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||
|
||||
/*
|
||||
* NAND Flash on the Local Bus
|
||||
*/
|
||||
#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
|
||||
#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_NAND_BASE \
|
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* Port Size = 8 bit */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V ) /* valid */
|
||||
#define CONFIG_SYS_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \
|
||||
| OR_FCM_CSCT \
|
||||
| OR_FCM_CST \
|
||||
| OR_FCM_CHT \
|
||||
| OR_FCM_SCY_1 \
|
||||
| OR_FCM_TRLX \
|
||||
| OR_FCM_EHTR )
|
||||
/* 0xFFFF8396 */
|
||||
|
||||
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
|
||||
#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
|
||||
|
||||
#ifdef CONFIG_VSC7385_ENET
|
||||
#define CONFIG_TSEC2
|
||||
#define CONFIG_SYS_VSC7385_BASE 0xF0000000
|
||||
#define CONFIG_SYS_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */
|
||||
#define CONFIG_SYS_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/
|
||||
/* Access window base at VSC7385 base */
|
||||
#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
|
||||
/* Access window size 128K */
|
||||
#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010
|
||||
/* The flash address and size of the VSC7385 firmware image */
|
||||
#define CONFIG_VSC7385_IMAGE 0xFE7FE000
|
||||
#define CONFIG_VSC7385_IMAGE_SIZE 8192
|
||||
#endif
|
||||
/*
|
||||
* Serial Port
|
||||
*/
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
|
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
|
||||
|
||||
/* Use the HUSH parser */
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
|
||||
/* Pass open firmware flat tree */
|
||||
#define CONFIG_OF_LIBFDT 1
|
||||
#define CONFIG_OF_BOARD_SETUP 1
|
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_NOPROBES {{0x51}} /* Don't probe these addrs */
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
|
||||
|
||||
/*
|
||||
* Board info - revision and where boot from
|
||||
*/
|
||||
#define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
|
||||
|
||||
/*
|
||||
* Config on-board RTC
|
||||
*/
|
||||
#define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
|
||||
|
||||
/*
|
||||
* General PCI
|
||||
* Addresses are mapped 1-1.
|
||||
*/
|
||||
#define CONFIG_SYS_PCIE1_BASE 0xA0000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
|
||||
#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
|
||||
#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
|
||||
#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
|
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
|
||||
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
|
||||
|
||||
/*
|
||||
* Fake PCIE2 definitions: there is no PCIE2 on this board but the code
|
||||
* in arch/powerpc/cpu/mpc83xx/pcie.c doesn't compile without this
|
||||
*/
|
||||
#define CONFIG_SYS_PCIE2_BASE 0xC0000000
|
||||
#define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000
|
||||
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000
|
||||
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
|
||||
#define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000
|
||||
#define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000
|
||||
#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
|
||||
#define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000
|
||||
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
|
||||
|
||||
#define CONFIG_PCI
|
||||
#define CONFIG_PCIE
|
||||
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
|
||||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
|
||||
#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
|
||||
|
||||
/*
|
||||
* TSEC
|
||||
*/
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_TSEC_ENET /* TSEC ethernet support */
|
||||
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
|
||||
#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
|
||||
#define CONFIG_SYS_TSEC2_OFFSET 0x25000
|
||||
#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
|
||||
|
||||
/*
|
||||
* TSEC ethernet configuration
|
||||
*/
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_TSEC1_NAME "eTSEC0"
|
||||
#define CONFIG_TSEC2_NAME "eTSEC1"
|
||||
#define TSEC1_PHY_ADDR 2
|
||||
#define TSEC2_PHY_ADDR 1
|
||||
#define TSEC1_PHYIDX 0
|
||||
#define TSEC2_PHYIDX 0
|
||||
#define TSEC1_FLAGS TSEC_GIGABIT
|
||||
#define TSEC2_FLAGS TSEC_GIGABIT
|
||||
|
||||
/* Options are: eTSEC[0-1] */
|
||||
#define CONFIG_ETHPRIME "eTSEC0"
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
|
||||
CONFIG_SYS_MONITOR_LEN)
|
||||
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_PING
|
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
||||
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
/* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*
|
||||
* Core HID Setup
|
||||
*/
|
||||
#define CONFIG_SYS_HID0_INIT 0x000000000
|
||||
#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
|
||||
HID0_ENABLE_INSTRUCTION_CACHE | \
|
||||
HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
|
||||
#define CONFIG_SYS_HID2 HID2_HBE
|
||||
|
||||
/*
|
||||
* MMU Setup
|
||||
*/
|
||||
|
||||
/* DDR: cache cacheable */
|
||||
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
|
||||
BATL_MEMCOHERENCE)
|
||||
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
|
||||
BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
|
||||
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
|
||||
|
||||
/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
|
||||
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
|
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
|
||||
BATU_VP)
|
||||
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
|
||||
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
|
||||
|
||||
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
|
||||
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
|
||||
BATL_MEMCOHERENCE)
|
||||
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
|
||||
BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
|
||||
BATL_CACHEINHIBIT | \
|
||||
BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
|
||||
|
||||
/* Stack in dcache: cacheable, no memory coherence */
|
||||
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
|
||||
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
|
||||
BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
|
||||
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
/*
|
||||
* Environment Configuration
|
||||
*/
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#if defined(CONFIG_TSEC_ENET)
|
||||
#define CONFIG_HAS_ETH0
|
||||
#define CONFIG_HAS_ETH1
|
||||
#endif
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
|
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
|
||||
|
||||
#define xstr(s) str(s)
|
||||
#define str(s) #s
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addtty=setenv bootargs ${bootargs}" \
|
||||
" console=${consoledev},${baudrate}\0" \
|
||||
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
|
||||
"addmisc=setenv bootargs ${bootargs}\0" \
|
||||
"kernel_addr=FE080000\0" \
|
||||
"fdt_addr=FE280000\0" \
|
||||
"ramdisk_addr=FE290000\0" \
|
||||
"u-boot=mpc8308rdb/u-boot.bin\0" \
|
||||
"kernel_addr_r=1000000\0" \
|
||||
"fdt_addr_r=C00000\0" \
|
||||
"hostname=mpc8308rdb\0" \
|
||||
"bootfile=mpc8308rdb/uImage\0" \
|
||||
"fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \
|
||||
"rootpath=/opt/eldk-4.2/ppc_6xx\0" \
|
||||
"flash_self=run ramargs addip addtty addmtd addmisc;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
|
||||
"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
|
||||
"bootm ${kernel_addr} - ${fdt_addr}\0" \
|
||||
"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
|
||||
"tftp ${fdt_addr_r} ${fdtfile};" \
|
||||
"run nfsargs addip addtty addmtd addmisc;" \
|
||||
"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
|
||||
"bootcmd=run flash_self\0" \
|
||||
"load=tftp ${loadaddr} ${u-boot}\0" \
|
||||
"update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \
|
||||
" +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \
|
||||
" +${filesize};cp.b ${fileaddr} " \
|
||||
xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
|
||||
"upd=run load update\0" \
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -0,0 +1,511 @@
|
|||
/*
|
||||
* Copyright (C) Freescale Semiconductor, Inc. 2006.
|
||||
*
|
||||
* (C) Copyright 2010
|
||||
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
/*
|
||||
* ve8313 board configuration file
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
*/
|
||||
#define CONFIG_E300 1
|
||||
#define CONFIG_MPC83xx 1
|
||||
#define CONFIG_MPC831x 1
|
||||
#define CONFIG_MPC8313 1
|
||||
#define CONFIG_VE8313 1
|
||||
|
||||
#define CONFIG_PCI 1
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1
|
||||
|
||||
/*
|
||||
* On-board devices
|
||||
*
|
||||
*/
|
||||
#define CONFIG_83XX_CLKIN 32000000 /* in Hz */
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
|
||||
|
||||
#define CONFIG_SYS_IMMR 0xE0000000
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00001000
|
||||
#define CONFIG_SYS_MEMTEST_END 0x07000000
|
||||
|
||||
#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth */
|
||||
#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count */
|
||||
|
||||
/*
|
||||
* Device configurations
|
||||
*/
|
||||
|
||||
/*
|
||||
* DDR Setup
|
||||
*/
|
||||
#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
|
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
|
||||
|
||||
/*
|
||||
* Manually set up DDR parameters, as this board does not
|
||||
* have the SPD connected to I2C.
|
||||
*/
|
||||
#define CONFIG_SYS_DDR_SIZE 128 /* MB */
|
||||
#define CONFIG_SYS_DDR_CONFIG ( CSCONFIG_EN \
|
||||
| CSCONFIG_AP \
|
||||
| 0x00040000 /* TODO */ \
|
||||
| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
|
||||
/* 0x80840102 */
|
||||
|
||||
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
|
||||
#define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
|
||||
| ( 0 << TIMING_CFG0_WRT_SHIFT ) \
|
||||
| ( 3 << TIMING_CFG0_RRT_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG0_WWT_SHIFT ) \
|
||||
| ( 7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
|
||||
| ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
|
||||
/* 0x0e720802 */
|
||||
#define CONFIG_SYS_DDR_TIMING_1 ( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \
|
||||
| ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \
|
||||
| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
|
||||
| ( 6 << TIMING_CFG1_REFREC_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG1_WRREC_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
|
||||
/* 0x26256222 */
|
||||
#define CONFIG_SYS_DDR_TIMING_2 ( ( 0 << TIMING_CFG2_ADD_LAT_SHIFT ) \
|
||||
| ( 5 << TIMING_CFG2_CPO_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
|
||||
| ( 1 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
|
||||
| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
|
||||
| ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) )
|
||||
/* 0x029028c7 */
|
||||
#define CONFIG_SYS_DDR_INTERVAL ( ( 0x320 << SDRAM_INTERVAL_REFINT_SHIFT ) \
|
||||
| ( 0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
|
||||
/* 0x03202000 */
|
||||
#define CONFIG_SYS_SDRAM_CFG ( SDRAM_CFG_SREN \
|
||||
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
|
||||
| SDRAM_CFG_32_BE )
|
||||
/* 0x43080000 */
|
||||
#define CONFIG_SYS_SDRAM_CFG2 0x00401000
|
||||
#define CONFIG_SYS_DDR_MODE ( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \
|
||||
| ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
|
||||
/* 0x44400232 */
|
||||
#define CONFIG_SYS_DDR_MODE_2 0x8000C000
|
||||
|
||||
#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
|
||||
/*0x02000000*/
|
||||
#define CONFIG_SYS_DDRCDR_VALUE ( DDRCDR_EN \
|
||||
| DDRCDR_PZ_NOMZ \
|
||||
| DDRCDR_NZ_NOMZ \
|
||||
| DDRCDR_M_ODR )
|
||||
/* 0x73000002 */
|
||||
|
||||
/*
|
||||
* FLASH on the Local Bus
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
|
||||
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
|
||||
#define CONFIG_SYS_FLASH_BASE 0xFE000000
|
||||
#define CONFIG_SYS_FLASH_SIZE 32 /* size in MB */
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
|
||||
|
||||
#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE | \
|
||||
(2 << BR_PS_SHIFT) | /* 16 bit */ \
|
||||
BR_V) /* valid */
|
||||
#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_ACS_DIV4 \
|
||||
| OR_GPCM_SCY_5 \
|
||||
| OR_GPCM_TRLX \
|
||||
| OR_GPCM_EAD)
|
||||
/* 0xfe000c55 */
|
||||
|
||||
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per dev */
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
|
||||
|
||||
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK 1
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
|
||||
#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
|
||||
CONFIG_SYS_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
|
||||
#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
|
||||
#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
|
||||
|
||||
/*
|
||||
* Local Bus LCRR and LBCR regs
|
||||
*/
|
||||
#define CONFIG_SYS_LCRR_EADC LCRR_EADC_3
|
||||
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
|
||||
|
||||
#define CONFIG_SYS_LBC_LBCR 0x00040000
|
||||
|
||||
#define CONFIG_SYS_LBC_MRTPR 0x20000000
|
||||
|
||||
/*
|
||||
* NAND settings
|
||||
*/
|
||||
#define CONFIG_SYS_NAND_BASE 0x61000000
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_MTD_NAND_VERIFY_WRITE
|
||||
#define CONFIG_CMD_NAND 1
|
||||
#define CONFIG_NAND_FSL_ELBC 1
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
|
||||
|
||||
#define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \
|
||||
| BR_PS_8 \
|
||||
| BR_DECC_CHK_GEN \
|
||||
| BR_MS_FCM \
|
||||
| BR_V ) /* valid */
|
||||
/* 0x61000c21 */
|
||||
#define CONFIG_SYS_NAND_OR_PRELIM (0xffff8000 \
|
||||
| OR_FCM_BCTLD \
|
||||
| OR_FCM_CHT \
|
||||
| OR_FCM_SCY_2 \
|
||||
| OR_FCM_RST \
|
||||
| OR_FCM_TRLX)
|
||||
/* 0xffff90ac */
|
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
|
||||
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
|
||||
#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
|
||||
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
|
||||
|
||||
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
|
||||
#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
|
||||
|
||||
#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
|
||||
#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
|
||||
|
||||
/* CS2 NvRAM */
|
||||
#define CONFIG_SYS_BR2_PRELIM (0x60000000 \
|
||||
| BR_PS_8 \
|
||||
| BR_V)
|
||||
/* 0x60000801 */
|
||||
#define CONFIG_SYS_OR2_PRELIM (0xfffe0000 \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_3 \
|
||||
| OR_GPCM_TRLX \
|
||||
| OR_GPCM_EHTR \
|
||||
| OR_GPCM_EAD)
|
||||
/* 0xfffe0937 */
|
||||
/* local bus read write buffer mapping SRAM@0x64000000 */
|
||||
#define CONFIG_SYS_BR3_PRELIM (0x62000000 \
|
||||
| BR_PS_16 \
|
||||
| BR_V)
|
||||
/* 0x62001001 */
|
||||
|
||||
#define CONFIG_SYS_OR3_PRELIM (0xfe000000 \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_TRLX \
|
||||
| OR_GPCM_EHTR \
|
||||
| OR_GPCM_EAD)
|
||||
/* 0xfe0009f7 */
|
||||
|
||||
/* pass open firmware flat tree */
|
||||
#define CONFIG_OF_LIBFDT 1
|
||||
#define CONFIG_OF_BOARD_SETUP 1
|
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
|
||||
|
||||
/*
|
||||
* Serial Port
|
||||
*/
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
|
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
|
||||
|
||||
/* Use the HUSH parser */
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
/*
|
||||
* General PCI
|
||||
* Addresses are mapped 1-1.
|
||||
*/
|
||||
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
|
||||
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
|
||||
#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
|
||||
#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
|
||||
#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
|
||||
#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
|
||||
#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
|
||||
#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
|
||||
#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
|
||||
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* TSEC
|
||||
*/
|
||||
#define CONFIG_TSEC_ENET /* TSEC ethernet support */
|
||||
|
||||
#define CONFIG_NET_MULTI
|
||||
|
||||
#define CONFIG_TSEC1
|
||||
#ifdef CONFIG_TSEC1
|
||||
#define CONFIG_HAS_ETH0
|
||||
#define CONFIG_TSEC1_NAME "TSEC1"
|
||||
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
|
||||
#define TSEC1_PHY_ADDR 0x01
|
||||
#define TSEC1_FLAGS 0
|
||||
#define TSEC1_PHYIDX 0
|
||||
#endif
|
||||
|
||||
/* Options are: TSEC[0-1] */
|
||||
#define CONFIG_ETHPRIME "TSEC1"
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
|
||||
CONFIG_SYS_MONITOR_LEN)
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
|
||||
#define CONFIG_ENV_SIZE 0x4000
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
|
||||
CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_PCI
|
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1
|
||||
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
|
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg Buffer size */
|
||||
#define CONFIG_SYS_HZ 1000 /* 1ms ticks */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
|
||||
|
||||
/* 0x64050000 */
|
||||
#define CONFIG_SYS_HRCW_LOW (\
|
||||
0x20000000 /* reserved, must be set */ |\
|
||||
HRCWL_DDRCM |\
|
||||
HRCWL_CSB_TO_CLKIN_4X1 | \
|
||||
HRCWL_CORE_TO_CSB_2_5X1)
|
||||
|
||||
/* 0xa0600004 */
|
||||
#define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST | \
|
||||
HRCWH_PCI_ARBITER_ENABLE | \
|
||||
HRCWH_CORE_ENABLE | \
|
||||
HRCWH_FROM_0X00000100 | \
|
||||
HRCWH_BOOTSEQ_DISABLE |\
|
||||
HRCWH_SW_WATCHDOG_DISABLE |\
|
||||
HRCWH_ROM_LOC_LOCAL_16BIT | \
|
||||
HRCWH_TSEC1M_IN_MII | \
|
||||
HRCWH_BIG_ENDIAN | \
|
||||
HRCWH_LALE_EARLY)
|
||||
|
||||
/* System IO Config */
|
||||
#define CONFIG_SYS_SICRH (0x01000000 | \
|
||||
SICRH_ETSEC2_B | \
|
||||
SICRH_ETSEC2_C | \
|
||||
SICRH_ETSEC2_D | \
|
||||
SICRH_ETSEC2_E | \
|
||||
SICRH_ETSEC2_F | \
|
||||
SICRH_ETSEC2_G | \
|
||||
SICRH_TSOBI1 | \
|
||||
SICRH_TSOBI2)
|
||||
/* 0x010fff03 */
|
||||
#define CONFIG_SYS_SICRL (SICRL_LBC | \
|
||||
SICRL_SPI_A | \
|
||||
SICRL_SPI_B | \
|
||||
SICRL_SPI_C | \
|
||||
SICRL_SPI_D | \
|
||||
SICRL_ETSEC2_A)
|
||||
/* 0x33fc0003) */
|
||||
|
||||
#define CONFIG_SYS_HID0_INIT 0x000000000
|
||||
#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
|
||||
HID0_ENABLE_INSTRUCTION_CACHE)
|
||||
|
||||
#define CONFIG_SYS_HID2 HID2_HBE
|
||||
|
||||
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
|
||||
|
||||
/* DDR @ 0x00000000 */
|
||||
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10)
|
||||
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
|
||||
BATU_VS | BATU_VP)
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
/* PCI @ 0x80000000 */
|
||||
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10)
|
||||
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
|
||||
BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | \
|
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
|
||||
BATU_VS | BATU_VP)
|
||||
#else
|
||||
#define CONFIG_SYS_IBAT1L (0)
|
||||
#define CONFIG_SYS_IBAT1U (0)
|
||||
#define CONFIG_SYS_IBAT2L (0)
|
||||
#define CONFIG_SYS_IBAT2U (0)
|
||||
#endif
|
||||
|
||||
/* PCI2 not supported on 8313 */
|
||||
#define CONFIG_SYS_IBAT3L (0)
|
||||
#define CONFIG_SYS_IBAT3U (0)
|
||||
#define CONFIG_SYS_IBAT4L (0)
|
||||
#define CONFIG_SYS_IBAT4U (0)
|
||||
|
||||
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
|
||||
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | \
|
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | \
|
||||
BATU_VP)
|
||||
|
||||
/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
|
||||
#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
|
||||
/* FPGA, SRAM, NAND @ 0x60000000 */
|
||||
#define CONFIG_SYS_IBAT7L (0x60000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_IBAT7U (0x60000000 | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
|
||||
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
|
||||
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
|
||||
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
|
||||
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
|
||||
#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
|
||||
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
|
||||
#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
|
||||
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
|
||||
#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
|
||||
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
|
||||
#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
|
||||
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
|
||||
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
|
||||
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
|
||||
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
|
||||
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#define CONFIG_NETDEV eth0
|
||||
|
||||
#define CONFIG_HOSTNAME ve8313
|
||||
#define CONFIG_UBOOTPATH ve8313/u-boot.bin
|
||||
|
||||
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define XMK_STR(x) #x
|
||||
#define MK_STR(x) XMK_STR(x)
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=" MK_STR(CONFIG_NETDEV) "\0" \
|
||||
"ethprime=" MK_STR(CONFIG_TSEC1_NAME) "\0" \
|
||||
"u-boot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
|
||||
"u-boot_addr_r=100000\0" \
|
||||
"load=tftp ${u-boot_addr_r} ${u-boot}\0" \
|
||||
"update=protect off " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
|
||||
"erase " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
|
||||
"cp.b ${u-boot_addr_r} " MK_STR(CONFIG_SYS_FLASH_BASE) \
|
||||
" ${filesize};" \
|
||||
"protect on " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \
|
||||
|
||||
#undef MK_STR
|
||||
#undef XMK_STR
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* Copyright (C) 2004-2007, 2010 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
|
|
@ -65,6 +65,7 @@
|
|||
#define PARTID_NO_E(spridr) ((spridr & 0xFFFE0000) >> 16)
|
||||
#define SPR_FAMILY(spridr) ((spridr & 0xFFF00000) >> 20)
|
||||
|
||||
#define SPR_8308 0x8100
|
||||
#define SPR_831X_FAMILY 0x80B
|
||||
#define SPR_8311 0x80B2
|
||||
#define SPR_8313 0x80B0
|
||||
|
|
@ -115,8 +116,9 @@
|
|||
#define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority */
|
||||
#define SPCR_TSEC2EP_SHIFT (31-31)
|
||||
|
||||
#elif defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
|
||||
/* SPCR bits - MPC831x and MPC837x specific */
|
||||
#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
|
||||
defined(CONFIG_MPC837x)
|
||||
/* SPCR bits - MPC8308, MPC831x and MPC837x specific */
|
||||
#define SPCR_TSECDP 0x00003000 /* TSEC data priority */
|
||||
#define SPCR_TSECDP_SHIFT (31-19)
|
||||
#define SPCR_TSECBDP 0x00000C00 /* TSEC buffer descriptor priority */
|
||||
|
|
@ -473,7 +475,7 @@
|
|||
#define HRCWL_CE_TO_PLL_1X30 0x0000001E
|
||||
#define HRCWL_CE_TO_PLL_1X31 0x0000001F
|
||||
|
||||
#elif defined(CONFIG_MPC8315)
|
||||
#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
|
||||
#define HRCWL_SVCOD 0x30000000
|
||||
#define HRCWL_SVCOD_SHIFT 28
|
||||
#define HRCWL_SVCOD_DIV_2 0x00000000
|
||||
|
|
@ -541,7 +543,8 @@
|
|||
#define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000
|
||||
#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
|
||||
|
||||
#if defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
|
||||
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
|
||||
defined(CONFIG_MPC837x)
|
||||
#define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000
|
||||
#define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000
|
||||
#define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000
|
||||
|
|
@ -592,7 +595,8 @@
|
|||
|
||||
/* RSR - Reset Status Register
|
||||
*/
|
||||
#if defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
|
||||
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
|
||||
defined(CONFIG_MPC837x)
|
||||
#define RSR_RSTSRC 0xF0000000 /* Reset source */
|
||||
#define RSR_RSTSRC_SHIFT 28
|
||||
#else
|
||||
|
|
@ -734,8 +738,8 @@
|
|||
#define SCCR_USBDRCM_2 0x00200000
|
||||
#define SCCR_USBDRCM_3 0x00300000
|
||||
|
||||
#elif defined(CONFIG_MPC8315)
|
||||
/* SCCR bits - MPC8315 specific */
|
||||
#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
|
||||
/* SCCR bits - MPC8315/MPC8308 specific */
|
||||
#define SCCR_TSEC1CM 0xc0000000
|
||||
#define SCCR_TSEC1CM_SHIFT 30
|
||||
#define SCCR_TSEC1CM_0 0x00000000
|
||||
|
|
@ -750,6 +754,13 @@
|
|||
#define SCCR_TSEC2CM_2 0x20000000
|
||||
#define SCCR_TSEC2CM_3 0x30000000
|
||||
|
||||
#define SCCR_SDHCCM 0x0c000000
|
||||
#define SCCR_SDHCCM_SHIFT 26
|
||||
#define SCCR_SDHCCM_0 0x00000000
|
||||
#define SCCR_SDHCCM_1 0x04000000
|
||||
#define SCCR_SDHCCM_2 0x08000000
|
||||
#define SCCR_SDHCCM_3 0x0c000000
|
||||
|
||||
#define SCCR_USBDRCM 0x00c00000
|
||||
#define SCCR_USBDRCM_SHIFT 22
|
||||
#define SCCR_USBDRCM_0 0x00000000
|
||||
|
|
|
|||
Loading…
Reference in New Issue