83xx: add support for ve8313 board
This patch add support for the ve8313 board based on
Freescale MPC8313 CPU.
- serial console on UART 1
- 128 MB DDR RAM
- 32 MB NOR Flash
- 16 MB NAND Flash
- Ethernet MII Mode over on TSEC0
- micrel ksz804 phy
- Hardware WDT MAX824
changes since v1
- Environment size = sector size
- use red. environment
- add comments from Kim Phillips
- add MAKEALL, MAINTAINERS entry
- Codingstyle issues fixed
- inserted original Copyrights
- PCI subsys vendor ID changed from 0x1057 (Motorola)
to 0x1957 (Freescale)
changes since v2
- add comments from Wolfgang Denk
- fix Codingstyle and some comments
- reworked WDT reset (just toggling the WD_TRIG pin)
- Environment size now 16KiB
- fixed RAMBOOT version
- fixed CONFIG_SYS_LOAD_ADDR
- renamed CONFIG_TSEC1_NAME to TSEC1
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Heiko Schocher
Kim Phillips
parent
5fb17030d5
commit
4e43b2e861
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@ -428,6 +428,7 @@ Heiko Schocher <hs@denx.de>
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sc3 PPC405GP
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suen3 ARM926EJS (Kirkwood SoC)
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uc101 MPC5200
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ve8313 MPC8313
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Peter De Schrijver <p2@mind.be>
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1
MAKEALL
1
MAKEALL
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@ -381,6 +381,7 @@ LIST_83xx=" \
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sbc8349 \
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SIMPC8313_LP \
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TQM834x \
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ve8313 \
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vme8349 \
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"
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@ -0,0 +1,50 @@
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS := $(BOARD).o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,7 @@
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ifndef NAND_SPL
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sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
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endif
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ifndef TEXT_BASE
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TEXT_BASE = 0xfe000000
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endif
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@ -0,0 +1,215 @@
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/*
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* Copyright (C) Freescale Semiconductor, Inc. 2006-2007
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*
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* Author: Scott Wood <scottwood@freescale.com>
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*
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* (C) Copyright 2010
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <libfdt.h>
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#include <pci.h>
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#include <mpc83xx.h>
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#include <ns16550.h>
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#include <nand.h>
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#include <asm/bitops.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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extern void disable_addr_trans (void);
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extern void enable_addr_trans (void);
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int checkboard(void)
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{
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puts("Board: ve8313\n");
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return 0;
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}
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static long fixed_sdram(void)
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{
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u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
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#ifndef CONFIG_SYS_RAMBOOT
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volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
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u32 msize_log2 = __ilog2(msize);
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out_be32(&im->sysconf.ddrlaw[0].bar,
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(CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000));
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out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1)));
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out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
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/*
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* Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
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* or the DDR2 controller may fail to initialize correctly.
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*/
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__udelay(50000);
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out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
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out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CONFIG);
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/* Currently we use only one CS, so disable the other bank. */
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out_be32(&im->ddr.cs_config[1], 0);
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out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
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out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
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out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
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out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
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out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
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out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);
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out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);
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out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
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out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);
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out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
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sync();
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/* enable DDR controller */
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setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
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/* now check the real size */
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disable_addr_trans ();
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msize = get_ram_size (CONFIG_SYS_DDR_BASE, msize);
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enable_addr_trans ();
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#endif
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return msize;
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}
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phys_size_t initdram(int board_type)
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{
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volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
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volatile fsl_lbus_t *lbc = &im->lbus;
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u32 msize;
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
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return -1;
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/* DDR SDRAM - Main SODIMM */
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msize = fixed_sdram();
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/* Local Bus setup lbcr and mrtpr */
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out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
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out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
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sync();
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/* return total bus SDRAM size(bytes) -- DDR */
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return msize;
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}
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#define VE8313_WDT_EN 0x00020000
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#define VE8313_WDT_TRIG 0x00040000
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int board_early_init_f (void)
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{
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volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
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volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;
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#if defined(CONFIG_HW_WATCHDOG)
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/* enable WDT */
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clrbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG);
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#else
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/* disable WDT */
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setbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG);
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#endif
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/* set WDT pins as output */
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setbits_be32(&gpio->dir, VE8313_WDT_EN | VE8313_WDT_TRIG);
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return 0;
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}
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#if defined(CONFIG_HW_WATCHDOG)
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void hw_watchdog_reset(void)
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{
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volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
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volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;
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unsigned long reg;
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reg = in_be32(&gpio->dat);
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if (reg & VE8313_WDT_TRIG)
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clrbits_be32(&gpio->dat, VE8313_WDT_TRIG);
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else
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setbits_be32(&gpio->dat, VE8313_WDT_TRIG);
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}
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#endif
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#if defined(CONFIG_PCI)
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static struct pci_region pci_regions[] = {
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{
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bus_start: CONFIG_SYS_PCI1_MEM_BASE,
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phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
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size: CONFIG_SYS_PCI1_MEM_SIZE,
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flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
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},
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{
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bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
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phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
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size: CONFIG_SYS_PCI1_MMIO_SIZE,
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flags: PCI_REGION_MEM
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},
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{
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bus_start: CONFIG_SYS_PCI1_IO_BASE,
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phys_start: CONFIG_SYS_PCI1_IO_PHYS,
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size: CONFIG_SYS_PCI1_IO_SIZE,
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flags: PCI_REGION_IO
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}
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};
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void pci_init_board(void)
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{
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volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
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volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
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volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
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struct pci_region *reg[] = { pci_regions };
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int warmboot;
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/* Enable all 3 PCI_CLK_OUTPUTs. */
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setbits_be32(&clk->occr, 0xe0000000);
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/*
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* Configure PCI Local Access Windows
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*/
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out_be32(&pci_law[0].bar, CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR);
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out_be32(&pci_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
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out_be32(&pci_law[1].bar, CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR);
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out_be32(&pci_law[1].ar, LBLAWAR_EN | LBLAWAR_1MB);
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warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM;
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mpc83xx_pci_init(1, reg, warmboot);
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}
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#endif
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#if defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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#ifdef CONFIG_PCI
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ft_pci_setup(blob, bd);
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#endif
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}
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#endif
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@ -132,6 +132,7 @@ ZPC1900 powerpc mpc8260 zpc1900
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mgcoge powerpc mpc8260 - keymile
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SCM powerpc mpc8260 - siemens
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TQM8272 powerpc mpc8260 tqm8272 tqc
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ve8313 powerpc mpc83xx ve8313
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kmeter1 powerpc mpc83xx kmeter1 keymile
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MVBLM7 powerpc mpc83xx mvblm7 matrix_vision
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TQM834x powerpc mpc83xx tqm834x tqc
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@ -0,0 +1,511 @@
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/*
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* Copyright (C) Freescale Semiconductor, Inc. 2006.
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*
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* (C) Copyright 2010
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
|
||||
*
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* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* ve8313 board configuration file
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_E300 1
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#define CONFIG_MPC83xx 1
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#define CONFIG_MPC831x 1
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#define CONFIG_MPC8313 1
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#define CONFIG_VE8313 1
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#define CONFIG_PCI 1
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#define CONFIG_BOARD_EARLY_INIT_F 1
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/*
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* On-board devices
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*
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*/
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#define CONFIG_83XX_CLKIN 32000000 /* in Hz */
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#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
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#define CONFIG_SYS_IMMR 0xE0000000
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#define CONFIG_SYS_MEMTEST_START 0x00001000
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#define CONFIG_SYS_MEMTEST_END 0x07000000
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count */
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/*
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* Device configurations
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*/
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/*
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* DDR Setup
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*/
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#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
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/*
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* Manually set up DDR parameters, as this board does not
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* have the SPD connected to I2C.
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*/
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#define CONFIG_SYS_DDR_SIZE 128 /* MB */
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#define CONFIG_SYS_DDR_CONFIG ( CSCONFIG_EN \
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| CSCONFIG_AP \
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| 0x00040000 /* TODO */ \
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| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
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/* 0x80840102 */
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#define CONFIG_SYS_DDR_TIMING_3 0x00000000
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#define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
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| ( 0 << TIMING_CFG0_WRT_SHIFT ) \
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| ( 3 << TIMING_CFG0_RRT_SHIFT ) \
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| ( 2 << TIMING_CFG0_WWT_SHIFT ) \
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| ( 7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
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| ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
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| ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
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| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
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/* 0x0e720802 */
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#define CONFIG_SYS_DDR_TIMING_1 ( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \
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| ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
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| ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \
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| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
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| ( 6 << TIMING_CFG1_REFREC_SHIFT ) \
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| ( 2 << TIMING_CFG1_WRREC_SHIFT ) \
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| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
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| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
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/* 0x26256222 */
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#define CONFIG_SYS_DDR_TIMING_2 ( ( 0 << TIMING_CFG2_ADD_LAT_SHIFT ) \
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| ( 5 << TIMING_CFG2_CPO_SHIFT ) \
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| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
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| ( 1 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
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| ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
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| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
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| ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) )
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/* 0x029028c7 */
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#define CONFIG_SYS_DDR_INTERVAL ( ( 0x320 << SDRAM_INTERVAL_REFINT_SHIFT ) \
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| ( 0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
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/* 0x03202000 */
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#define CONFIG_SYS_SDRAM_CFG ( SDRAM_CFG_SREN \
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| SDRAM_CFG_SDRAM_TYPE_DDR2 \
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| SDRAM_CFG_32_BE )
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/* 0x43080000 */
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#define CONFIG_SYS_SDRAM_CFG2 0x00401000
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#define CONFIG_SYS_DDR_MODE ( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \
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| ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
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/* 0x44400232 */
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#define CONFIG_SYS_DDR_MODE_2 0x8000C000
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|
||||
#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
|
||||
/*0x02000000*/
|
||||
#define CONFIG_SYS_DDRCDR_VALUE ( DDRCDR_EN \
|
||||
| DDRCDR_PZ_NOMZ \
|
||||
| DDRCDR_NZ_NOMZ \
|
||||
| DDRCDR_M_ODR )
|
||||
/* 0x73000002 */
|
||||
|
||||
/*
|
||||
* FLASH on the Local Bus
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
|
||||
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
|
||||
#define CONFIG_SYS_FLASH_BASE 0xFE000000
|
||||
#define CONFIG_SYS_FLASH_SIZE 32 /* size in MB */
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
|
||||
|
||||
#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE | \
|
||||
(2 << BR_PS_SHIFT) | /* 16 bit */ \
|
||||
BR_V) /* valid */
|
||||
#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_ACS_DIV4 \
|
||||
| OR_GPCM_SCY_5 \
|
||||
| OR_GPCM_TRLX \
|
||||
| OR_GPCM_EAD)
|
||||
/* 0xfe000c55 */
|
||||
|
||||
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per dev */
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
|
||||
|
||||
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK 1
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
|
||||
#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
|
||||
CONFIG_SYS_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
|
||||
#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
|
||||
#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
|
||||
|
||||
/*
|
||||
* Local Bus LCRR and LBCR regs
|
||||
*/
|
||||
#define CONFIG_SYS_LCRR_EADC LCRR_EADC_3
|
||||
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
|
||||
|
||||
#define CONFIG_SYS_LBC_LBCR 0x00040000
|
||||
|
||||
#define CONFIG_SYS_LBC_MRTPR 0x20000000
|
||||
|
||||
/*
|
||||
* NAND settings
|
||||
*/
|
||||
#define CONFIG_SYS_NAND_BASE 0x61000000
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_MTD_NAND_VERIFY_WRITE
|
||||
#define CONFIG_CMD_NAND 1
|
||||
#define CONFIG_NAND_FSL_ELBC 1
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
|
||||
|
||||
#define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \
|
||||
| BR_PS_8 \
|
||||
| BR_DECC_CHK_GEN \
|
||||
| BR_MS_FCM \
|
||||
| BR_V ) /* valid */
|
||||
/* 0x61000c21 */
|
||||
#define CONFIG_SYS_NAND_OR_PRELIM (0xffff8000 \
|
||||
| OR_FCM_BCTLD \
|
||||
| OR_FCM_CHT \
|
||||
| OR_FCM_SCY_2 \
|
||||
| OR_FCM_RST \
|
||||
| OR_FCM_TRLX)
|
||||
/* 0xffff90ac */
|
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
|
||||
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
|
||||
#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
|
||||
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
|
||||
|
||||
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
|
||||
#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
|
||||
|
||||
#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
|
||||
#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
|
||||
|
||||
/* CS2 NvRAM */
|
||||
#define CONFIG_SYS_BR2_PRELIM (0x60000000 \
|
||||
| BR_PS_8 \
|
||||
| BR_V)
|
||||
/* 0x60000801 */
|
||||
#define CONFIG_SYS_OR2_PRELIM (0xfffe0000 \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_3 \
|
||||
| OR_GPCM_TRLX \
|
||||
| OR_GPCM_EHTR \
|
||||
| OR_GPCM_EAD)
|
||||
/* 0xfffe0937 */
|
||||
/* local bus read write buffer mapping SRAM@0x64000000 */
|
||||
#define CONFIG_SYS_BR3_PRELIM (0x62000000 \
|
||||
| BR_PS_16 \
|
||||
| BR_V)
|
||||
/* 0x62001001 */
|
||||
|
||||
#define CONFIG_SYS_OR3_PRELIM (0xfe000000 \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_TRLX \
|
||||
| OR_GPCM_EHTR \
|
||||
| OR_GPCM_EAD)
|
||||
/* 0xfe0009f7 */
|
||||
|
||||
/* pass open firmware flat tree */
|
||||
#define CONFIG_OF_LIBFDT 1
|
||||
#define CONFIG_OF_BOARD_SETUP 1
|
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
|
||||
|
||||
/*
|
||||
* Serial Port
|
||||
*/
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
|
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
|
||||
|
||||
/* Use the HUSH parser */
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
/*
|
||||
* General PCI
|
||||
* Addresses are mapped 1-1.
|
||||
*/
|
||||
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
|
||||
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
|
||||
#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
|
||||
#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
|
||||
#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
|
||||
#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
|
||||
#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
|
||||
#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
|
||||
#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
|
||||
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* TSEC
|
||||
*/
|
||||
#define CONFIG_TSEC_ENET /* TSEC ethernet support */
|
||||
|
||||
#define CONFIG_NET_MULTI
|
||||
|
||||
#define CONFIG_TSEC1
|
||||
#ifdef CONFIG_TSEC1
|
||||
#define CONFIG_HAS_ETH0
|
||||
#define CONFIG_TSEC1_NAME "TSEC1"
|
||||
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
|
||||
#define TSEC1_PHY_ADDR 0x01
|
||||
#define TSEC1_FLAGS 0
|
||||
#define TSEC1_PHYIDX 0
|
||||
#endif
|
||||
|
||||
/* Options are: TSEC[0-1] */
|
||||
#define CONFIG_ETHPRIME "TSEC1"
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
|
||||
CONFIG_SYS_MONITOR_LEN)
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
|
||||
#define CONFIG_ENV_SIZE 0x4000
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
|
||||
CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_PCI
|
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1
|
||||
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
|
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg Buffer size */
|
||||
#define CONFIG_SYS_HZ 1000 /* 1ms ticks */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
|
||||
|
||||
/* 0x64050000 */
|
||||
#define CONFIG_SYS_HRCW_LOW (\
|
||||
0x20000000 /* reserved, must be set */ |\
|
||||
HRCWL_DDRCM |\
|
||||
HRCWL_CSB_TO_CLKIN_4X1 | \
|
||||
HRCWL_CORE_TO_CSB_2_5X1)
|
||||
|
||||
/* 0xa0600004 */
|
||||
#define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST | \
|
||||
HRCWH_PCI_ARBITER_ENABLE | \
|
||||
HRCWH_CORE_ENABLE | \
|
||||
HRCWH_FROM_0X00000100 | \
|
||||
HRCWH_BOOTSEQ_DISABLE |\
|
||||
HRCWH_SW_WATCHDOG_DISABLE |\
|
||||
HRCWH_ROM_LOC_LOCAL_16BIT | \
|
||||
HRCWH_TSEC1M_IN_MII | \
|
||||
HRCWH_BIG_ENDIAN | \
|
||||
HRCWH_LALE_EARLY)
|
||||
|
||||
/* System IO Config */
|
||||
#define CONFIG_SYS_SICRH (0x01000000 | \
|
||||
SICRH_ETSEC2_B | \
|
||||
SICRH_ETSEC2_C | \
|
||||
SICRH_ETSEC2_D | \
|
||||
SICRH_ETSEC2_E | \
|
||||
SICRH_ETSEC2_F | \
|
||||
SICRH_ETSEC2_G | \
|
||||
SICRH_TSOBI1 | \
|
||||
SICRH_TSOBI2)
|
||||
/* 0x010fff03 */
|
||||
#define CONFIG_SYS_SICRL (SICRL_LBC | \
|
||||
SICRL_SPI_A | \
|
||||
SICRL_SPI_B | \
|
||||
SICRL_SPI_C | \
|
||||
SICRL_SPI_D | \
|
||||
SICRL_ETSEC2_A)
|
||||
/* 0x33fc0003) */
|
||||
|
||||
#define CONFIG_SYS_HID0_INIT 0x000000000
|
||||
#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
|
||||
HID0_ENABLE_INSTRUCTION_CACHE)
|
||||
|
||||
#define CONFIG_SYS_HID2 HID2_HBE
|
||||
|
||||
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
|
||||
|
||||
/* DDR @ 0x00000000 */
|
||||
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10)
|
||||
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
|
||||
BATU_VS | BATU_VP)
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
/* PCI @ 0x80000000 */
|
||||
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10)
|
||||
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
|
||||
BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | \
|
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
|
||||
BATU_VS | BATU_VP)
|
||||
#else
|
||||
#define CONFIG_SYS_IBAT1L (0)
|
||||
#define CONFIG_SYS_IBAT1U (0)
|
||||
#define CONFIG_SYS_IBAT2L (0)
|
||||
#define CONFIG_SYS_IBAT2U (0)
|
||||
#endif
|
||||
|
||||
/* PCI2 not supported on 8313 */
|
||||
#define CONFIG_SYS_IBAT3L (0)
|
||||
#define CONFIG_SYS_IBAT3U (0)
|
||||
#define CONFIG_SYS_IBAT4L (0)
|
||||
#define CONFIG_SYS_IBAT4U (0)
|
||||
|
||||
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
|
||||
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | \
|
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | \
|
||||
BATU_VP)
|
||||
|
||||
/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
|
||||
#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
|
||||
/* FPGA, SRAM, NAND @ 0x60000000 */
|
||||
#define CONFIG_SYS_IBAT7L (0x60000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_IBAT7U (0x60000000 | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
|
||||
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
|
||||
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
|
||||
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
|
||||
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
|
||||
#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
|
||||
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
|
||||
#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
|
||||
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
|
||||
#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
|
||||
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
|
||||
#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
|
||||
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
|
||||
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
|
||||
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
|
||||
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
|
||||
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#define CONFIG_NETDEV eth0
|
||||
|
||||
#define CONFIG_HOSTNAME ve8313
|
||||
#define CONFIG_UBOOTPATH ve8313/u-boot.bin
|
||||
|
||||
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define XMK_STR(x) #x
|
||||
#define MK_STR(x) XMK_STR(x)
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=" MK_STR(CONFIG_NETDEV) "\0" \
|
||||
"ethprime=" MK_STR(CONFIG_TSEC1_NAME) "\0" \
|
||||
"u-boot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
|
||||
"u-boot_addr_r=100000\0" \
|
||||
"load=tftp ${u-boot_addr_r} ${u-boot}\0" \
|
||||
"update=protect off " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
|
||||
"erase " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
|
||||
"cp.b ${u-boot_addr_r} " MK_STR(CONFIG_SYS_FLASH_BASE) \
|
||||
" ${filesize};" \
|
||||
"protect on " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \
|
||||
|
||||
#undef MK_STR
|
||||
#undef XMK_STR
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue