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Merge branch 'master' of git://git.denx.de/u-boot-net

This commit is contained in:
Wolfgang Denk 2010-07-14 22:04:30 +02:00
parent cb8f031729 ab9164d0de
commit 50298d37e6
40 changed files with 1897 additions and 906 deletions
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4
arch/arm/cpu/arm926ejs/kirkwood/cpu.c
View File

@ -378,10 +378,10 @@ int arch_misc_init(void)
}
#endif /* CONFIG_ARCH_MISC_INIT */
#ifdef CONFIG_KIRKWOOD_EGIGA
#ifdef CONFIG_MVGBE
int cpu_eth_init(bd_t *bis)
{
kirkwood_egiga_initialize(bis);
mvgbe_initialize(bis);
return 0;
}
#endif

8
arch/arm/cpu/arm926ejs/orion5x/cpu.c
View File

@ -268,3 +268,11 @@ int arch_misc_init(void)
return 0;
}
#endif /* CONFIG_ARCH_MISC_INIT */
#ifdef CONFIG_MVGBE
int cpu_eth_init(bd_t *bis)
{
mvgbe_initialize(bis);
return 0;
}
#endif

5
arch/arm/include/asm/arch-kirkwood/kirkwood.h
View File

@ -60,6 +60,11 @@
#define KW_EGIGA0_BASE (KW_REGISTER(0x72000))
#define KW_EGIGA1_BASE (KW_REGISTER(0x76000))
/* Kirkwood GbE controller has two ports */
#define MAX_MVGBE_DEVS 2
#define MVGBE0_BASE KW_EGIGA0_BASE
#define MVGBE1_BASE KW_EGIGA1_BASE
#if defined (CONFIG_KW88F6281)
#include <asm/arch/kw88f6281.h>
#elif defined (CONFIG_KW88F6192)

4
arch/arm/include/asm/arch-orion5x/orion5x.h
View File

@ -56,6 +56,10 @@
#define ORION5X_USB20_PORT1_BASE (ORION5X_REGISTER(0xA0000))
#define ORION5X_EGIGA_BASE (ORION5X_REGISTER(0x72000))
/* Orion5x GbE controller has a single port */
#define MAX_MVGBE_DEVS 1
#define MVGBE0_BASE ORION5X_EGIGA_BASE
#define CONFIG_MAX_RAM_BANK_SIZE (64*1024*1024)
/* include here SoC variants. 5181, 5281, 6183 should go here when

36
board/LaCie/edminiv2/edminiv2.c
View File

@ -27,6 +27,7 @@
#include <common.h>
#include <miiphy.h>
#include <asm/arch/orion5x.h>
#include "edminiv2.h"
DECLARE_GLOBAL_DATA_PTR;
@ -90,3 +91,38 @@ int board_init(void)
return 0;
}
#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
/* Configure and enable MV88E1116 PHY */
void reset_phy(void)
{
u16 reg;
u16 devadr;
char *name = "egiga0";
if (miiphy_set_current_dev(name))
return;
/* command to read PHY dev address */
if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
printf("Err..%s could not read PHY dev address\n",
__func__);
return;
}
/*
* Enable RGMII delay on Tx and Rx for CPU port
* Ref: sec 4.7.2 of chip datasheet
*/
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
/* reset the phy */
miiphy_reset(name, devadr);
printf("88E1116 Initialized on %s\n", name);
}
#endif /* CONFIG_RESET_PHY_R */

41
board/LaCie/edminiv2/edminiv2.h Normal file
View File

@ -0,0 +1,41 @@
/*
* (C) Copyright 2009
* Net Insight <www.netinsight.net>
* Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
*
* Based on sheevaplug.h:
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef __EDMINIV2_BASE_H
#define __EDMINIV2_BASE_H
/* PHY related */
#define MV88E1116_LED_FCTRL_REG 10
#define MV88E1116_CPRSP_CR3_REG 21
#define MV88E1116_MAC_CTRL_REG 21
#define MV88E1116_PGADR_REG 22
#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
#endif /* __EDMINIV2_BASE_H */

7
board/afeb9260/afeb9260.c
View File

@ -167,13 +167,6 @@ int dram_init(void)
#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
#ifdef CONFIG_MACB
/*
* Initialize ethernet HW addr prior to starting Linux,
* needed for nfsroot
*/
eth_init(gd->bd);
#endif
}
#endif

7
board/atmel/at91cap9adk/at91cap9adk.c
View File

@ -339,13 +339,6 @@ int dram_init(void)
#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
#ifdef CONFIG_MACB
/*
* Initialize ethernet HW addr prior to starting Linux,
* needed for nfsroot
*/
eth_init(gd->bd);
#endif
}
#endif

7
board/atmel/at91sam9260ek/at91sam9260ek.c
View File

@ -179,13 +179,6 @@ int dram_init(void)
#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
#ifdef CONFIG_MACB
/*
* Initialize ethernet HW addr prior to starting Linux,
* needed for nfsroot
*/
eth_init(gd->bd);
#endif
}
#endif

7
board/atmel/at91sam9263ek/at91sam9263ek.c
View File

@ -284,13 +284,6 @@ int dram_init(void)
#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
#ifdef CONFIG_MACB
/*
* Initialize ethernet HW addr prior to starting Linux,
* needed for nfsroot
*/
eth_init(gd->bd);
#endif
}
#endif

7
board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
View File

@ -291,13 +291,6 @@ int dram_init(void)
#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
#ifdef CONFIG_MACB
/*
* Initialize ethernet HW addr prior to starting Linux,
* needed for nfsroot
*/
eth_init(gd->bd);
#endif
}
#endif

7
board/calao/sbc35_a9g20/sbc35_a9g20.c
View File

@ -177,13 +177,6 @@ int dram_init(void)
#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
#ifdef CONFIG_MACB
/*
* Initialize ethernet HW addr prior to starting Linux,
* needed for nfsroot
*/
eth_init(gd->bd);
#endif
}
#endif

7
board/eukrea/cpu9260/cpu9260.c
View File

@ -200,13 +200,6 @@ int dram_init(void)
#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
#ifdef CONFIG_MACB
/*
* Initialize ethernet HW addr prior to starting Linux,
* needed for nfsroot
*/
eth_init(gd->bd);
#endif
}
#endif

7
board/ronetix/pm9263/pm9263.c
View File

@ -387,13 +387,6 @@ int dram_init(void)
#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
#ifdef CONFIG_MACB
/*
* Initialize ethernet HW addr prior to starting Linux,
* needed for nfsroot
*/
eth_init(gd->bd);
#endif
}
#endif

25
doc/README.designware_eth Normal file
View File

@ -0,0 +1,25 @@
This driver supports Designware Ethernet Controller provided by Synopsis.
The driver is enabled by CONFIG_DESIGNWARE_ETH.
The driver has been developed and tested on SPEAr platforms. By default, the
MDIO interface works at 100/Full. #defining the below options in board
configuration file changes this behavior.
Call an subroutine from respective board/.../board.c
designware_initialize(u32 id, ulong base_addr, u32 phy_addr);
The various options suported by the driver are
1. CONFIG_DW_ALTDESCRIPTOR
Define this to use the Alternate/Enhanced Descriptor configurations.
1. CONFIG_DW_AUTONEG
Define this to autonegotiate with the host before proceeding with mac
level configuration. This obviates the definitions of CONFIG_DW_SPEED10M
and CONFIG_DW_DUPLEXHALF.
2. CONFIG_DW_SPEED10M
Define this to change the default behavior from 100Mbps to 10Mbps.
3. CONFIG_DW_DUPLEXHALF
Define this to change the default behavior from Full Duplex to Half.
4. CONFIG_DW_SEARCH_PHY
Define this to search the phy address. This would overwrite the value
passed as 3rd arg from designware_initialize routine.

5
drivers/net/4xx_enet.c
View File

@ -1095,6 +1095,11 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
miiphy_write (dev->name, reg, 0x18, 0x4101);
miiphy_write (dev->name, reg, 0x09, 0x0e00);
miiphy_write (dev->name, reg, 0x04, 0x01e1);
#if defined(CONFIG_M88E1111_DISABLE_FIBER)
miiphy_read(dev->name, reg, 0x1b, &reg_short);
reg_short |= 0x8000;
miiphy_write(dev->name, reg, 0x1b, reg_short);
#endif
#endif
#if defined(CONFIG_M88E1112_PHY)
if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) {

3
drivers/net/Makefile
View File

@ -34,6 +34,7 @@ COBJS-$(CONFIG_BCM570x) += bcm570x.o bcm570x_autoneg.o 5701rls.o
COBJS-$(CONFIG_BFIN_MAC) += bfin_mac.o
COBJS-$(CONFIG_CS8900) += cs8900.o
COBJS-$(CONFIG_TULIP) += dc2114x.o
COBJS-$(CONFIG_DESIGNWARE_ETH) += designware.o
COBJS-$(CONFIG_DRIVER_DM9000) += dm9000x.o
COBJS-$(CONFIG_DNET) += dnet.o
COBJS-$(CONFIG_E1000) += e1000.o
@ -46,13 +47,13 @@ COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o
COBJS-$(CONFIG_FTMAC100) += ftmac100.o
COBJS-$(CONFIG_GRETH) += greth.o
COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o
COBJS-$(CONFIG_KIRKWOOD_EGIGA) += kirkwood_egiga.o
COBJS-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o
COBJS-$(CONFIG_LAN91C96) += lan91c96.o
COBJS-$(CONFIG_MACB) += macb.o
COBJS-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
COBJS-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o
COBJS-$(CONFIG_MPC512x_FEC) += mpc512x_fec.o
COBJS-$(CONFIG_MVGBE) += mvgbe.o
COBJS-$(CONFIG_NATSEMI) += natsemi.o
COBJS-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o
COBJS-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o

60
drivers/net/at91_emac.c
View File

@ -53,6 +53,10 @@
Please decrease the CONFIG_SYS_RX_ETH_BUFFER value
#endif
#ifndef CONFIG_DRIVER_AT91EMAC_PHYADDR
#define CONFIG_DRIVER_AT91EMAC_PHYADDR 0
#endif
/* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */
#if (AT91C_MASTER_CLOCK > 80000000)
#define HCLK_DIV AT91_EMAC_CFG_MCLK_64
@ -198,12 +202,15 @@ static int at91emac_phy_reset(struct eth_device *netdev)
emac = (at91_emac_t *) netdev->iobase;
adv = ADVERTISE_CSMA | ADVERTISE_ALL;
at91emac_write(emac, 0, MII_ADVERTISE, adv);
at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
MII_ADVERTISE, adv);
VERBOSEP("%s: Starting autonegotiation...\n", netdev->name);
at91emac_write(emac, 0, MII_BMCR, (BMCR_ANENABLE | BMCR_ANRESTART));
at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMCR,
(BMCR_ANENABLE | BMCR_ANRESTART));
for (i = 0; i < 100000 / 100; i++) {
at91emac_read(emac, 0, MII_BMSR, &status);
at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
MII_BMSR, &status);
if (status & BMSR_ANEGCOMPLETE)
break;
udelay(100);
@ -229,13 +236,15 @@ static int at91emac_phy_init(struct eth_device *netdev)
emac = (at91_emac_t *) netdev->iobase;
/* Check if the PHY is up to snuff... */
at91emac_read(emac, 0, MII_PHYSID1, &phy_id);
at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
MII_PHYSID1, &phy_id);
if (phy_id == 0xffff) {
printf("%s: No PHY present\n", netdev->name);
return 1;
}
at91emac_read(emac, 0, MII_BMSR, &status);
at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
MII_BMSR, &status);
if (!(status & BMSR_LSTATUS)) {
/* Try to re-negotiate if we don't have link already. */
@ -243,7 +252,8 @@ static int at91emac_phy_init(struct eth_device *netdev)
return 2;
for (i = 0; i < 100000 / 100; i++) {
at91emac_read(emac, 0, MII_BMSR, &status);
at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
MII_BMSR, &status);
if (status & BMSR_LSTATUS)
break;
udelay(100);
@ -253,8 +263,10 @@ static int at91emac_phy_init(struct eth_device *netdev)
VERBOSEP("%s: link down\n", netdev->name);
return 3;
} else {
at91emac_read(emac, 0, MII_ADVERTISE, &adv);
at91emac_read(emac, 0, MII_LPA, &lpa);
at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
MII_ADVERTISE, &adv);
at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
MII_LPA, &lpa);
media = mii_nway_result(lpa & adv);
speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
? 1 : 0);
@ -271,7 +283,7 @@ int at91emac_UpdateLinkSpeed(at91_emac_t *emac)
{
unsigned short stat1;
at91emac_read(emac, 0, MII_BMSR, &stat1);
at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMSR, &stat1);
if (!(stat1 & BMSR_LSTATUS)) /* link status up? */
return 1;
@ -348,14 +360,6 @@ static int at91emac_init(struct eth_device *netdev, bd_t *bd)
writel(1 << AT91_ID_EMAC, &pmc->pcer);
writel(readl(&emac->ctl) | AT91_EMAC_CTL_CSR, &emac->ctl);
DEBUG_AT91EMAC("init MAC-ADDR %x%x \n",
cpu_to_le16(*((u16 *)(netdev->enetaddr + 4))),
cpu_to_le32(*((u32 *)netdev->enetaddr)));
writel(cpu_to_le32(*((u32 *)netdev->enetaddr)), &emac->sa2l);
writel(cpu_to_le16(*((u16 *)(netdev->enetaddr + 4))), &emac->sa2h);
DEBUG_AT91EMAC("init MAC-ADDR %x%x \n",
readl(&emac->sa2h), readl(&emac->sa2l));
/* Init Ethernet buffers */
for (i = 0; i < RBF_FRAMEMAX; i++) {
dev->rbfdt[i].addr = (unsigned long) NetRxPackets[i];
@ -372,7 +376,7 @@ static int at91emac_init(struct eth_device *netdev, bd_t *bd)
value = AT91_EMAC_CFG_CAF | AT91_EMAC_CFG_NBC |
HCLK_DIV;
#ifdef CONFIG_RMII
value |= AT91C_EMAC_RMII;
value |= AT91_EMAC_CFG_RMII;
#endif
writel(value, &emac->cfg);
@ -456,6 +460,25 @@ static int at91emac_recv(struct eth_device *netdev)
return 0;
}
static int at91emac_write_hwaddr(struct eth_device *netdev)
{
emac_device *dev;
at91_emac_t *emac;
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
emac = (at91_emac_t *) netdev->iobase;
dev = (emac_device *) netdev->priv;
writel(1 << AT91_ID_EMAC, &pmc->pcer);
DEBUG_AT91EMAC("init MAC-ADDR %x%x \n",
cpu_to_le16(*((u16 *)(netdev->enetaddr + 4))),
cpu_to_le32(*((u32 *)netdev->enetaddr)));
writel(cpu_to_le32(*((u32 *)netdev->enetaddr)), &emac->sa2l);
writel(cpu_to_le16(*((u16 *)(netdev->enetaddr + 4))), &emac->sa2h);
DEBUG_AT91EMAC("init MAC-ADDR %x%x \n",
readl(&emac->sa2h), readl(&emac->sa2l));
return 0;
}
int at91emac_register(bd_t *bis, unsigned long iobase)
{
emac_device *emac;
@ -488,6 +511,7 @@ int at91emac_register(bd_t *bis, unsigned long iobase)
dev->halt = at91emac_halt;
dev->send = at91emac_send;
dev->recv = at91emac_recv;
dev->write_hwaddr = at91emac_write_hwaddr;
eth_register(dev);

133
drivers/net/ax88180.c
View File

@ -41,6 +41,7 @@
#include <command.h>
#include <net.h>
#include <malloc.h>
#include <linux/mii.h>
#include "ax88180.h"
/*
@ -50,9 +51,9 @@
*/
static void ax88180_rx_handler (struct eth_device *dev);
static int ax88180_phy_initial (struct eth_device *dev);
static void ax88180_meidia_config (struct eth_device *dev);
static unsigned long get_CicadaPHY_meida_mode (struct eth_device *dev);
static unsigned long get_MarvellPHY_meida_mode (struct eth_device *dev);
static void ax88180_media_config (struct eth_device *dev);
static unsigned long get_CicadaPHY_media_mode (struct eth_device *dev);
static unsigned long get_MarvellPHY_media_mode (struct eth_device *dev);
static unsigned short ax88180_mdio_read (struct eth_device *dev,
unsigned long regaddr);
static void ax88180_mdio_write (struct eth_device *dev,
@ -112,10 +113,10 @@ static int ax88180_phy_reset (struct eth_device *dev)
{
unsigned short delay_cnt = 500;
ax88180_mdio_write (dev, BMCR, (PHY_RESET | AUTONEG_EN));
ax88180_mdio_write (dev, MII_BMCR, (BMCR_RESET | BMCR_ANENABLE));
/* Wait for the reset to complete, or time out (500 ms) */
while (ax88180_mdio_read (dev, BMCR) & PHY_RESET) {
while (ax88180_mdio_read (dev, MII_BMCR) & BMCR_RESET) {
udelay (1000);
if (--delay_cnt == 0) {
printf ("Failed to reset PHY!\n");
@ -255,52 +256,78 @@ static int ax88180_phy_initial (struct eth_device *dev)
{
struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
unsigned long tmp_regval;
unsigned short phyaddr;
/* Check avaliable PHY chipset */
priv->PhyAddr = MARVELL_88E1111_PHYADDR;
priv->PhyID0 = ax88180_mdio_read (dev, PHYIDR0);
/* Search for first avaliable PHY chipset */
#ifdef CONFIG_PHY_ADDR
phyaddr = CONFIG_PHY_ADDR;
#else
for (phyaddr = 0; phyaddr < 32; ++phyaddr)
#endif
{
priv->PhyAddr = phyaddr;
priv->PhyID0 = ax88180_mdio_read(dev, MII_PHYSID1);
priv->PhyID1 = ax88180_mdio_read(dev, MII_PHYSID2);
if (priv->PhyID0 == MARVELL_88E1111_PHYIDR0) {
switch (priv->PhyID0) {
case MARVELL_ALASKA_PHYSID0:
debug("ax88180: Found Marvell Alaska PHY family."
" (PHY Addr=0x%x)\n", priv->PhyAddr);
debug ("ax88180: Found Marvell 88E1111 PHY."
" (PHY Addr=0x%x)\n", priv->PhyAddr);
switch (priv->PhyID1) {
case MARVELL_88E1118_PHYSID1:
ax88180_mdio_write(dev, M88E1118_PAGE_SEL, 2);
ax88180_mdio_write(dev, M88E1118_CR,
M88E1118_CR_DEFAULT);
ax88180_mdio_write(dev, M88E1118_PAGE_SEL, 3);
ax88180_mdio_write(dev, M88E1118_LEDCTL,
M88E1118_LEDCTL_DEFAULT);
ax88180_mdio_write(dev, M88E1118_LEDMIX,
M88E1118_LEDMIX_LED050 | M88E1118_LEDMIX_LED150 | 0x15);
ax88180_mdio_write(dev, M88E1118_PAGE_SEL, 0);
default: /* Default to 88E1111 Phy */
tmp_regval = ax88180_mdio_read(dev, M88E1111_EXT_SSR);
if ((tmp_regval & HWCFG_MODE_MASK) != RGMII_COPPER_MODE)
ax88180_mdio_write(dev, M88E1111_EXT_SCR,
DEFAULT_EXT_SCR);
}
tmp_regval = ax88180_mdio_read (dev, M88_EXT_SSR);
if ((tmp_regval & HWCFG_MODE_MASK) == RGMII_COPPER_MODE) {
ax88180_mdio_write (dev, M88_EXT_SCR, DEFAULT_EXT_SCR);
if (ax88180_phy_reset (dev) < 0)
if (ax88180_phy_reset(dev) < 0)
return 0;
ax88180_mdio_write (dev, M88_IER, LINK_CHANGE_INT);
}
} else {
ax88180_mdio_write(dev, M88_IER, LINK_CHANGE_INT);
priv->PhyAddr = CICADA_CIS8201_PHYADDR;
priv->PhyID0 = ax88180_mdio_read (dev, PHYIDR0);
return 1;
if (priv->PhyID0 == CICADA_CIS8201_PHYIDR0) {
case CICADA_CIS8201_PHYSID0:
debug("ax88180: Found CICADA CIS8201 PHY"
" chipset. (PHY Addr=0x%x)\n", priv->PhyAddr);
debug ("ax88180: Found CICADA CIS8201 PHY"
" chipset. (PHY Addr=0x%x)\n", priv->PhyAddr);
ax88180_mdio_write (dev, CIS_IMR,
ax88180_mdio_write(dev, CIS_IMR,
(CIS_INT_ENABLE | LINK_CHANGE_INT));
/* Set CIS_SMI_PRIORITY bit before force the media mode */
tmp_regval =
ax88180_mdio_read (dev, CIS_AUX_CTRL_STATUS);
tmp_regval = ax88180_mdio_read(dev, CIS_AUX_CTRL_STATUS);
tmp_regval &= ~CIS_SMI_PRIORITY;
ax88180_mdio_write (dev, CIS_AUX_CTRL_STATUS,
tmp_regval);
} else {
printf ("ax88180: Unknown PHY chipset!!\n");
return 0;
ax88180_mdio_write(dev, CIS_AUX_CTRL_STATUS, tmp_regval);
return 1;
case 0xffff:
/* No PHY at this addr */
break;
default:
printf("ax88180: Unknown PHY chipset %#x at addr %#x\n",
priv->PhyID0, priv->PhyAddr);
break;
}
}
return 1;
printf("ax88180: Unknown PHY chipset!!\n");
return 0;
}
static void ax88180_meidia_config (struct eth_device *dev)
static void ax88180_media_config (struct eth_device *dev)
{
struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
unsigned long bmcr_val, bmsr_val;
@ -310,20 +337,20 @@ static void ax88180_meidia_config (struct eth_device *dev)
/* Waiting 2 seconds for PHY link stable */
for (i = 0; i < 20000; i++) {
bmsr_val = ax88180_mdio_read (dev, BMSR);
if (bmsr_val & LINKOK) {
bmsr_val = ax88180_mdio_read (dev, MII_BMSR);
if (bmsr_val & BMSR_LSTATUS) {
break;
}
udelay (100);
}
bmsr_val = ax88180_mdio_read (dev, BMSR);
bmsr_val = ax88180_mdio_read (dev, MII_BMSR);
debug ("ax88180: BMSR=0x%04x\n", (unsigned int)bmsr_val);
if (bmsr_val & LINKOK) {
bmcr_val = ax88180_mdio_read (dev, BMCR);
if (bmsr_val & BMSR_LSTATUS) {
bmcr_val = ax88180_mdio_read (dev, MII_BMCR);
if (bmcr_val & AUTONEG_EN) {
if (bmcr_val & BMCR_ANENABLE) {
/*
* Waiting for Auto-negotiation completion, this may
@ -332,8 +359,8 @@ static void ax88180_meidia_config (struct eth_device *dev)
debug ("ax88180: Auto-negotiation is "
"enabled. Waiting for NWay completion..\n");
for (i = 0; i < 50000; i++) {
bmsr_val = ax88180_mdio_read (dev, BMSR);
if (bmsr_val & AUTONEG_COMPLETE) {
bmsr_val = ax88180_mdio_read (dev, MII_BMSR);
if (bmsr_val & BMSR_ANEGCOMPLETE) {
break;
}
udelay (100);
@ -345,12 +372,16 @@ static void ax88180_meidia_config (struct eth_device *dev)
(unsigned int)bmcr_val, (unsigned int)bmsr_val);
/* Get real media mode here */
if (priv->PhyID0 == MARVELL_88E1111_PHYIDR0) {
RealMediaMode = get_MarvellPHY_meida_mode (dev);
} else if (priv->PhyID0 == CICADA_CIS8201_PHYIDR0) {
RealMediaMode = get_CicadaPHY_meida_mode (dev);
} else {
switch (priv->PhyID0) {
case MARVELL_ALASKA_PHYSID0:
RealMediaMode = get_MarvellPHY_media_mode(dev);
break;
case CICADA_CIS8201_PHYSID0:
RealMediaMode = get_CicadaPHY_media_mode(dev);
break;
default:
RealMediaMode = MEDIA_1000FULL;
break;
}
priv->LinkState = INS_LINK_UP;
@ -424,7 +455,7 @@ static void ax88180_meidia_config (struct eth_device *dev)
return;
}
static unsigned long get_MarvellPHY_meida_mode (struct eth_device *dev)
static unsigned long get_MarvellPHY_media_mode (struct eth_device *dev)
{
unsigned long m88_ssr;
unsigned long MediaMode;
@ -457,7 +488,7 @@ static unsigned long get_MarvellPHY_meida_mode (struct eth_device *dev)
return MediaMode;
}
static unsigned long get_CicadaPHY_meida_mode (struct eth_device *dev)
static unsigned long get_CicadaPHY_media_mode (struct eth_device *dev)
{
unsigned long tmp_regval;
unsigned long MediaMode;
@ -522,7 +553,7 @@ static int ax88180_init (struct eth_device *dev, bd_t * bd)
dev->enetaddr[4] | (((unsigned short)dev->enetaddr[5]) << 8);
OUTW (dev, tmp_regval, MACID2);
ax88180_meidia_config (dev);
ax88180_media_config (dev);
OUTW (dev, DEFAULT_RXFILTER, RXFILTER);
@ -558,7 +589,7 @@ static int ax88180_recv (struct eth_device *dev)
if (ISR_Status & ISR_PHY) {
/* Read ISR register once to clear PHY interrupt bit */
tmp_regval = ax88180_mdio_read (dev, M88_ISR);
ax88180_meidia_config (dev);
ax88180_media_config (dev);
}
if ((ISR_Status & ISR_RX) || (ISR_Status & ISR_RXBUFFOVR)) {

104
drivers/net/ax88180.h
View File

@ -19,6 +19,7 @@
#ifndef _AX88180_H_
#define _AX88180_H_
#include <asm/io.h>
#include <asm/types.h>
#include <config.h>
@ -33,6 +34,7 @@ struct ax88180_private {
unsigned char PadSize;
unsigned short PhyAddr;
unsigned short PhyID0;
unsigned short PhyID1;
unsigned short FirstTxDesc;
unsigned short NextTxDesc;
ax88180_link_state LinkState;
@ -63,11 +65,10 @@ struct ax88180_private {
/* Max Rx Jumbo size is 15K Bytes */
#define MAX_RX_SIZE 0x3C00
#define MARVELL_88E1111_PHYADDR 0x18
#define MARVELL_88E1111_PHYIDR0 0x0141
#define MARVELL_ALASKA_PHYSID0 0x141
#define MARVELL_88E1118_PHYSID1 0xE40
#define CICADA_CIS8201_PHYADDR 0x01
#define CICADA_CIS8201_PHYIDR0 0x000F
#define CICADA_CIS8201_PHYSID0 0x000F
#define MEDIA_AUTO 0
#define MEDIA_1000FULL 1
@ -278,50 +279,6 @@ struct ax88180_private {
#define SOFTRST_NORMAL 0x00000003
#define SOFTRST_RESET_MAC 0x00000002
/* External PHY Register Definition */
#define BMCR 0x0000
#define LINE_SPEED_MSB 0x0040
#define DUPLEX_MODE 0x0100
#define RESTART_AUTONEG 0x0200
#define POWER_DOWN 0x0800
#define AUTONEG_EN 0x1000
#define LINE_SPEED_LSB 0x2000
#define PHY_RESET 0x8000
#define MEDIAMODE_MASK (LINE_SPEED_MSB | LINE_SPEED_LSB |\
DUPLEX_MODE)
#define BMCR_SPEED_1000 LINE_SPEED_MSB
#define BMCR_SPEED_100 LINE_SPEED_LSB
#define BMCR_SPEED_10 0x0000
#define BMCR_1000FULL (BMCR_SPEED_1000 | DUPLEX_MODE)
#define BMCR_100FULL (BMCR_SPEED_100 | DUPLEX_MODE)
#define BMCR_100HALF BMCR_SPEED_100
#define BMCR_10FULL DUPLEX_MODE
#define BMCR_10HALF 0x0000
#define BMSR 0x0001
#define LINKOK 0x0004
#define AUTONEG_ENABLE_STS 0x0008
#define AUTONEG_COMPLETE 0x0020
#define PHYIDR0 0x0002
#define PHYIDR1 0x0003
#define ANAR 0x0004
#define ANAR_PAUSE 0x0400
#define ANAR_100FULL 0x0100
#define ANAR_100HALF 0x0080
#define ANAR_10FULL 0x0040
#define ANAR_10HALF 0x0020
#define ANAR_8023BIT 0x0001
#define ANLPAR 0x0005
#define ANER 0x0006
#define AUX_1000_CTRL 0x0009
#define ENABLE_1000HALF 0x0100
#define ENABLE_1000FULL 0x0200
#define DEFAULT_AUX_1000_CTRL (ENABLE_1000HALF | ENABLE_1000FULL)
#define AUX_1000_STATUS 0x000A
#define LP_1000HALF 0x0400
#define LP_1000FULL 0x0800
/* Marvell 88E1111 Gigabit PHY Register Definition */
#define M88_SSR 0x0011
#define SSR_SPEED_MASK 0xC000
@ -342,14 +299,36 @@ struct ax88180_private {
#define LINK_CHANGE_INT 0x0400
#define M88_ISR 0x0013
#define LINK_CHANGE_STATUS 0x0400
#define M88_EXT_SCR 0x0014
#define M88E1111_EXT_SCR 0x0014
#define RGMII_RXCLK_DELAY 0x0080
#define RGMII_TXCLK_DELAY 0x0002
#define DEFAULT_EXT_SCR (RGMII_TXCLK_DELAY | RGMII_RXCLK_DELAY)
#define M88_EXT_SSR 0x001B
#define M88E1111_EXT_SSR 0x001B
#define HWCFG_MODE_MASK 0x000F
#define RGMII_COPPER_MODE 0x000B
/* Marvell 88E1118 Gigabit PHY Register Definition */
#define M88E1118_CR 0x14
#define M88E1118_CR_RGMII_RXCLK_DELAY 0x0020
#define M88E1118_CR_RGMII_TXCLK_DELAY 0x0010
#define M88E1118_CR_DEFAULT (M88E1118_CR_RGMII_TXCLK_DELAY | \
M88E1118_CR_RGMII_RXCLK_DELAY)
#define M88E1118_LEDCTL 0x10 /* Reg 16 on page 3 */
#define M88E1118_LEDCTL_LED2INT 0x200
#define M88E1118_LEDCTL_LED2BLNK 0x400
#define M88E1118_LEDCTL_LED0DUALMODE1 0xc
#define M88E1118_LEDCTL_LED0DUALMODE2 0xd
#define M88E1118_LEDCTL_LED0DUALMODE3 0xe
#define M88E1118_LEDCTL_LED0DUALMODE4 0xf
#define M88E1118_LEDCTL_DEFAULT (M88E1118_LEDCTL_LED2BLNK | \
M88E1118_LEDCTL_LED0DUALMODE4)
#define M88E1118_LEDMIX 0x11 /* Reg 17 on page 3 */
#define M88E1118_LEDMIX_LED050 0x4
#define M88E1118_LEDMIX_LED150 0x8
#define M88E1118_PAGE_SEL 0x16 /* Reg page select */
/* CICADA CIS8201 Gigabit PHY Register Definition */
#define CIS_IMR 0x0019
#define CIS_INT_ENABLE 0x8000
@ -376,36 +355,41 @@ struct ax88180_private {
static inline unsigned short INW (struct eth_device *dev, unsigned long addr)
{
return le16_to_cpu (*(volatile unsigned short *) (addr + dev->iobase));
}
static inline void OUTW (struct eth_device *dev, unsigned short command, unsigned long addr)
{
*(volatile unsigned short *) ((addr + dev->iobase)) = cpu_to_le16 (command);
return le16_to_cpu(readw(addr + (void *)dev->iobase));
}
/*
Access RXBUFFER_START/TXBUFFER_START to read RX buffer/write TX buffer
*/
#if defined (CONFIG_DRIVER_AX88180_16BIT)
static inline void OUTW (struct eth_device *dev, unsigned short command, unsigned long addr)
{
writew(cpu_to_le16(command), addr + (void *)dev->iobase);
}
static inline unsigned short READ_RXBUF (struct eth_device *dev)
{
return le16_to_cpu (*(volatile unsigned short *) (RXBUFFER_START + dev->iobase));
return le16_to_cpu(readw(RXBUFFER_START + (void *)dev->iobase));
}
static inline void WRITE_TXBUF (struct eth_device *dev, unsigned short data)
{
*(volatile unsigned short *) ((TXBUFFER_START + dev->iobase)) = cpu_to_le16 (data);
writew(cpu_to_le16(data), TXBUFFER_START + (void *)dev->iobase);
}
#else
static inline void OUTW (struct eth_device *dev, unsigned short command, unsigned long addr)
{
writel(cpu_to_le32(command), addr + (void *)dev->iobase);
}
static inline unsigned long READ_RXBUF (struct eth_device *dev)
{
return le32_to_cpu (*(volatile unsigned long *) (RXBUFFER_START + dev->iobase));
return le32_to_cpu(readl(RXBUFFER_START + (void *)dev->iobase));
}
static inline void WRITE_TXBUF (struct eth_device *dev, unsigned long data)
{
*(volatile unsigned long *) ((TXBUFFER_START + dev->iobase)) = cpu_to_le32 (data);
writel(cpu_to_le32(data), TXBUFFER_START + (void *)dev->iobase);
}
#endif

531
drivers/net/designware.c Normal file
View File

@ -0,0 +1,531 @@
/*
* (C) Copyright 2010
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Designware ethernet IP driver for u-boot
*/
#include <common.h>
#include <miiphy.h>
#include <malloc.h>
#include <linux/err.h>
#include <asm/io.h>
#include "designware.h"
static void tx_descs_init(struct eth_device *dev)
{
struct dw_eth_dev *priv = dev->priv;
struct eth_dma_regs *dma_p = priv->dma_regs_p;
struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
char *txbuffs = &priv->txbuffs[0];
struct dmamacdescr *desc_p;
u32 idx;
for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
desc_p = &desc_table_p[idx];
desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE];
desc_p->dmamac_next = &desc_table_p[idx + 1];
#if defined(CONFIG_DW_ALTDESCRIPTOR)
desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | \
DESC_TXSTS_TXCHECKINSCTRL | \
DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
desc_p->dmamac_cntl = 0;
desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
#else
desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
desc_p->txrx_status = 0;
#endif
}
/* Correcting the last pointer of the chain */
desc_p->dmamac_next = &desc_table_p[0];
writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
}
static void rx_descs_init(struct eth_device *dev)
{
struct dw_eth_dev *priv = dev->priv;
struct eth_dma_regs *dma_p = priv->dma_regs_p;
struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
char *rxbuffs = &priv->rxbuffs[0];
struct dmamacdescr *desc_p;
u32 idx;
for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
desc_p = &desc_table_p[idx];
desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE];
desc_p->dmamac_next = &desc_table_p[idx + 1];
desc_p->dmamac_cntl =
(MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | \
DESC_RXCTRL_RXCHAIN;
desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
}
/* Correcting the last pointer of the chain */
desc_p->dmamac_next = &desc_table_p[0];
writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
}
static void descs_init(struct eth_device *dev)
{
tx_descs_init(dev);
rx_descs_init(dev);
}
static int mac_reset(struct eth_device *dev)
{
struct dw_eth_dev *priv = dev->priv;
struct eth_mac_regs *mac_p = priv->mac_regs_p;
struct eth_dma_regs *dma_p = priv->dma_regs_p;
int timeout = CONFIG_MACRESET_TIMEOUT;
writel(DMAMAC_SRST, &dma_p->busmode);
writel(MII_PORTSELECT, &mac_p->conf);
do {
if (!(readl(&dma_p->busmode) & DMAMAC_SRST))
return 0;
udelay(1000);
} while (timeout--);
return -1;
}
static int dw_write_hwaddr(struct eth_device *dev)
{
struct dw_eth_dev *priv = dev->priv;
struct eth_mac_regs *mac_p = priv->mac_regs_p;
u32 macid_lo, macid_hi;
u8 *mac_id = &dev->enetaddr[0];
macid_lo = mac_id[0] + (mac_id[1] << 8) + \
(mac_id[2] << 16) + (mac_id[3] << 24);
macid_hi = mac_id[4] + (mac_id[5] << 8);
writel(macid_hi, &mac_p->macaddr0hi);
writel(macid_lo, &mac_p->macaddr0lo);
return 0;
}
static int dw_eth_init(struct eth_device *dev, bd_t *bis)
{
struct dw_eth_dev *priv = dev->priv;
struct eth_mac_regs *mac_p = priv->mac_regs_p;
struct eth_dma_regs *dma_p = priv->dma_regs_p;
u32 conf;
/* Reset ethernet hardware */
if (mac_reset(dev) < 0)
return -1;
writel(FIXEDBURST | PRIORXTX_41 | BURST_16,
&dma_p->busmode);
writel(FLUSHTXFIFO | readl(&dma_p->opmode), &dma_p->opmode);
writel(STOREFORWARD | TXSECONDFRAME, &dma_p->opmode);
conf = FRAMEBURSTENABLE | DISABLERXOWN;
if (priv->speed != SPEED_1000M)
conf |= MII_PORTSELECT;
if (priv->duplex == FULL_DUPLEX)
conf |= FULLDPLXMODE;
writel(conf, &mac_p->conf);
descs_init(dev);
/*
* Start/Enable xfer at dma as well as mac level
*/
writel(readl(&dma_p->opmode) | RXSTART, &dma_p->opmode);
writel(readl(&dma_p->opmode) | TXSTART, &dma_p->opmode);
writel(readl(&mac_p->conf) | RXENABLE, &mac_p->conf);
writel(readl(&mac_p->conf) | TXENABLE, &mac_p->conf);
return 0;
}
static int dw_eth_send(struct eth_device *dev, volatile void *packet,
int length)
{
struct dw_eth_dev *priv = dev->priv;
struct eth_dma_regs *dma_p = priv->dma_regs_p;
u32 desc_num = priv->tx_currdescnum;
struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
/* Check if the descriptor is owned by CPU */
if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
printf("CPU not owner of tx frame\n");
return -1;
}
memcpy((void *)desc_p->dmamac_addr, (void *)packet, length);
#if defined(CONFIG_DW_ALTDESCRIPTOR)
desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \
DESC_TXCTRL_SIZE1MASK;
desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
#else
desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & \
DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | \
DESC_TXCTRL_TXFIRST;
desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
#endif
/* Test the wrap-around condition. */
if (++desc_num >= CONFIG_TX_DESCR_NUM)
desc_num = 0;
priv->tx_currdescnum = desc_num;
/* Start the transmission */
writel(POLL_DATA, &dma_p->txpolldemand);
return 0;
}
static int dw_eth_recv(struct eth_device *dev)
{
struct dw_eth_dev *priv = dev->priv;
u32 desc_num = priv->rx_currdescnum;
struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
u32 status = desc_p->txrx_status;
int length = 0;
/* Check if the owner is the CPU */
if (!(status & DESC_RXSTS_OWNBYDMA)) {
length = (status & DESC_RXSTS_FRMLENMSK) >> \
DESC_RXSTS_FRMLENSHFT;
NetReceive(desc_p->dmamac_addr, length);
/*
* Make the current descriptor valid again and go to
* the next one
*/
desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
/* Test the wrap-around condition. */
if (++desc_num >= CONFIG_RX_DESCR_NUM)
desc_num = 0;
}
priv->rx_currdescnum = desc_num;
return length;
}
static void dw_eth_halt(struct eth_device *dev)
{
struct dw_eth_dev *priv = dev->priv;
mac_reset(dev);
priv->tx_currdescnum = priv->rx_currdescnum = 0;
}
static int eth_mdio_read(struct eth_device *dev, u8 addr, u8 reg, u16 *val)
{
struct dw_eth_dev *priv = dev->priv;
struct eth_mac_regs *mac_p = priv->mac_regs_p;
u32 miiaddr;
int timeout = CONFIG_MDIO_TIMEOUT;
miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \
((reg << MIIREGSHIFT) & MII_REGMSK);
writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
do {
if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
*val = readl(&mac_p->miidata);
return 0;
}
udelay(1000);
} while (timeout--);
return -1;
}
static int eth_mdio_write(struct eth_device *dev, u8 addr, u8 reg, u16 val)
{
struct dw_eth_dev *priv = dev->priv;
struct eth_mac_regs *mac_p = priv->mac_regs_p;
u32 miiaddr;
int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
u16 value;
writel(val, &mac_p->miidata);
miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \
((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
do {
if (!(readl(&mac_p->miiaddr) & MII_BUSY))
ret = 0;
udelay(1000);
} while (timeout--);
/* Needed as a fix for ST-Phy */
eth_mdio_read(dev, addr, reg, &value);
return ret;
}
#if defined(CONFIG_DW_SEARCH_PHY)
static int find_phy(struct eth_device *dev)
{
int phy_addr = 0;
u16 ctrl, oldctrl;
do {
eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl);
oldctrl = ctrl & PHY_BMCR_AUTON;
ctrl ^= PHY_BMCR_AUTON;
eth_mdio_write(dev, phy_addr, PHY_BMCR, ctrl);
eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl);
ctrl &= PHY_BMCR_AUTON;
if (ctrl == oldctrl) {
phy_addr++;
} else {
ctrl ^= PHY_BMCR_AUTON;
eth_mdio_write(dev, phy_addr, PHY_BMCR, ctrl);
return phy_addr;
}
} while (phy_addr < 32);
return -1;
}
#endif
static int dw_reset_phy(struct eth_device *dev)
{
struct dw_eth_dev *priv = dev->priv;
u16 ctrl;
int timeout = CONFIG_PHYRESET_TIMEOUT;
u32 phy_addr = priv->address;
eth_mdio_write(dev, phy_addr, PHY_BMCR, PHY_BMCR_RESET);
do {
eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl);
if (!(ctrl & PHY_BMCR_RESET))
break;
udelay(1000);
} while (timeout--);
if (timeout < 0)
return -1;
#ifdef CONFIG_PHY_RESET_DELAY
udelay(CONFIG_PHY_RESET_DELAY);
#endif
return 0;
}
static int configure_phy(struct eth_device *dev)
{
struct dw_eth_dev *priv = dev->priv;
int phy_addr;
u16 bmcr, ctrl;
#if defined(CONFIG_DW_AUTONEG)
u16 bmsr;
u32 timeout;
u16 anlpar, btsr;
#endif
#if defined(CONFIG_DW_SEARCH_PHY)
phy_addr = find_phy(dev);
if (phy_addr > 0)
priv->address = phy_addr;
else
return -1;
#endif
if (dw_reset_phy(dev) < 0)
return -1;
#if defined(CONFIG_DW_AUTONEG)
bmcr = PHY_BMCR_AUTON | PHY_BMCR_RST_NEG | PHY_BMCR_100MB | \
PHY_BMCR_DPLX | PHY_BMCR_1000_MBPS;
#else
bmcr = PHY_BMCR_100MB | PHY_BMCR_DPLX;
#if defined(CONFIG_DW_SPEED10M)
bmcr &= ~PHY_BMCR_100MB;
#endif
#if defined(CONFIG_DW_DUPLEXHALF)
bmcr &= ~PHY_BMCR_DPLX;
#endif
#endif
if (eth_mdio_write(dev, phy_addr, PHY_BMCR, bmcr) < 0)
return -1;
/* Read the phy status register and populate priv structure */
#if defined(CONFIG_DW_AUTONEG)
timeout = CONFIG_AUTONEG_TIMEOUT;
do {
eth_mdio_read(dev, phy_addr, PHY_BMSR, &bmsr);
if (bmsr & PHY_BMSR_AUTN_COMP)
break;
udelay(1000);
} while (timeout--);
eth_mdio_read(dev, phy_addr, PHY_ANLPAR, &anlpar);
eth_mdio_read(dev, phy_addr, PHY_1000BTSR, &btsr);
if (btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) {
priv->speed = SPEED_1000M;
if (btsr & PHY_1000BTSR_1000FD)
priv->duplex = FULL_DUPLEX;
else
priv->duplex = HALF_DUPLEX;
} else {
if (anlpar & PHY_ANLPAR_100)
priv->speed = SPEED_100M;
else
priv->speed = SPEED_10M;
if (anlpar & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD))
priv->duplex = FULL_DUPLEX;
else
priv->duplex = HALF_DUPLEX;
}
#else
if (eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl) < 0)
return -1;
if (ctrl & PHY_BMCR_DPLX)
priv->duplex = FULL_DUPLEX;
else
priv->duplex = HALF_DUPLEX;
if (ctrl & PHY_BMCR_1000_MBPS)
priv->speed = SPEED_1000M;
else if (ctrl & PHY_BMCR_100_MBPS)
priv->speed = SPEED_100M;
else
priv->speed = SPEED_10M;
#endif
return 0;
}
#if defined(CONFIG_MII)
static int dw_mii_read(char *devname, u8 addr, u8 reg, u16 *val)
{
struct eth_device *dev;
dev = eth_get_dev_by_name(devname);
if (dev)
eth_mdio_read(dev, addr, reg, val);
return 0;
}
static int dw_mii_write(char *devname, u8 addr, u8 reg, u16 val)
{
struct eth_device *dev;
dev = eth_get_dev_by_name(devname);
if (dev)
eth_mdio_write(dev, addr, reg, val);
return 0;
}
#endif
int designware_initialize(u32 id, ulong base_addr, u32 phy_addr)
{
struct eth_device *dev;
struct dw_eth_dev *priv;
dev = (struct eth_device *) malloc(sizeof(struct eth_device));
if (!dev)
return -ENOMEM;
/*
* Since the priv structure contains the descriptors which need a strict
* buswidth alignment, memalign is used to allocate memory
*/
priv = (struct dw_eth_dev *) memalign(16, sizeof(struct dw_eth_dev));
if (!priv) {
free(dev);
return -ENOMEM;
}
memset(dev, 0, sizeof(struct eth_device));
memset(priv, 0, sizeof(struct dw_eth_dev));
sprintf(dev->name, "mii%d", id);
dev->iobase = (int)base_addr;
dev->priv = priv;
eth_getenv_enetaddr_by_index(id, &dev->enetaddr[0]);
priv->dev = dev;
priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
DW_DMA_BASE_OFFSET);
priv->address = phy_addr;
if (mac_reset(dev) < 0)
return -1;
if (configure_phy(dev) < 0) {
printf("Phy could not be configured\n");
return -1;
}
dev->init = dw_eth_init;
dev->send = dw_eth_send;
dev->recv = dw_eth_recv;
dev->halt = dw_eth_halt;
dev->write_hwaddr = dw_write_hwaddr;
eth_register(dev);
#if defined(CONFIG_MII)
miiphy_register(dev->name, dw_mii_read, dw_mii_write);
#endif
return 1;
}

264
drivers/net/designware.h Normal file
View File

@ -0,0 +1,264 @@
/*
* (C) Copyright 2010
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _DW_ETH_H
#define _DW_ETH_H
#define CONFIG_TX_DESCR_NUM 16
#define CONFIG_RX_DESCR_NUM 16
#define CONFIG_ETH_BUFSIZE 2048
#define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
#define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
#define CONFIG_MACRESET_TIMEOUT (3 * CONFIG_SYS_HZ)
#define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
#define CONFIG_PHYRESET_TIMEOUT (3 * CONFIG_SYS_HZ)
#define CONFIG_AUTONEG_TIMEOUT (5 * CONFIG_SYS_HZ)
struct eth_mac_regs {
u32 conf; /* 0x00 */
u32 framefilt; /* 0x04 */
u32 hashtablehigh; /* 0x08 */
u32 hashtablelow; /* 0x0c */
u32 miiaddr; /* 0x10 */
u32 miidata; /* 0x14 */
u32 flowcontrol; /* 0x18 */
u32 vlantag; /* 0x1c */
u32 version; /* 0x20 */
u8 reserved_1[20];
u32 intreg; /* 0x38 */
u32 intmask; /* 0x3c */
u32 macaddr0hi; /* 0x40 */
u32 macaddr0lo; /* 0x44 */
};
/* MAC configuration register definitions */
#define FRAMEBURSTENABLE (1 << 21)
#define MII_PORTSELECT (1 << 15)
#define FES_100 (1 << 14)
#define DISABLERXOWN (1 << 13)
#define FULLDPLXMODE (1 << 11)
#define RXENABLE (1 << 2)
#define TXENABLE (1 << 3)
/* MII address register definitions */
#define MII_BUSY (1 << 0)
#define MII_WRITE (1 << 1)
#define MII_CLKRANGE_60_100M (0)
#define MII_CLKRANGE_100_150M (0x4)
#define MII_CLKRANGE_20_35M (0x8)
#define MII_CLKRANGE_35_60M (0xC)
#define MII_CLKRANGE_150_250M (0x10)
#define MII_CLKRANGE_250_300M (0x14)
#define MIIADDRSHIFT (11)
#define MIIREGSHIFT (6)
#define MII_REGMSK (0x1F << 6)
#define MII_ADDRMSK (0x1F << 11)
struct eth_dma_regs {
u32 busmode; /* 0x00 */
u32 txpolldemand; /* 0x04 */
u32 rxpolldemand; /* 0x08 */
u32 rxdesclistaddr; /* 0x0c */
u32 txdesclistaddr; /* 0x10 */
u32 status; /* 0x14 */
u32 opmode; /* 0x18 */
u32 intenable; /* 0x1c */
u8 reserved[40];
u32 currhosttxdesc; /* 0x48 */
u32 currhostrxdesc; /* 0x4c */
u32 currhosttxbuffaddr; /* 0x50 */
u32 currhostrxbuffaddr; /* 0x54 */
};
#define DW_DMA_BASE_OFFSET (0x1000)
/* Bus mode register definitions */
#define FIXEDBURST (1 << 16)
#define PRIORXTX_41 (3 << 14)
#define PRIORXTX_31 (2 << 14)
#define PRIORXTX_21 (1 << 14)
#define PRIORXTX_11 (0 << 14)
#define BURST_1 (1 << 8)
#define BURST_2 (2 << 8)
#define BURST_4 (4 << 8)
#define BURST_8 (8 << 8)
#define BURST_16 (16 << 8)
#define BURST_32 (32 << 8)
#define RXHIGHPRIO (1 << 1)
#define DMAMAC_SRST (1 << 0)
/* Poll demand definitions */
#define POLL_DATA (0xFFFFFFFF)
/* Operation mode definitions */
#define STOREFORWARD (1 << 21)
#define FLUSHTXFIFO (1 << 20)
#define TXSTART (1 << 13)
#define TXSECONDFRAME (1 << 2)
#define RXSTART (1 << 1)
/* Descriptior related definitions */
#define MAC_MAX_FRAME_SZ (2048)
struct dmamacdescr {
u32 txrx_status;
u32 dmamac_cntl;
void *dmamac_addr;
struct dmamacdescr *dmamac_next;
};
/*
* txrx_status definitions
*/
/* tx status bits definitions */
#if defined(CONFIG_DW_ALTDESCRIPTOR)
#define DESC_TXSTS_OWNBYDMA (1 << 31)
#define DESC_TXSTS_TXINT (1 << 30)
#define DESC_TXSTS_TXLAST (1 << 29)
#define DESC_TXSTS_TXFIRST (1 << 28)
#define DESC_TXSTS_TXCRCDIS (1 << 27)
#define DESC_TXSTS_TXPADDIS (1 << 26)
#define DESC_TXSTS_TXCHECKINSCTRL (3 << 22)
#define DESC_TXSTS_TXRINGEND (1 << 21)
#define DESC_TXSTS_TXCHAIN (1 << 20)
#define DESC_TXSTS_MSK (0x1FFFF << 0)
#else
#define DESC_TXSTS_OWNBYDMA (1 << 31)
#define DESC_TXSTS_MSK (0x1FFFF << 0)
#endif
/* rx status bits definitions */
#define DESC_RXSTS_OWNBYDMA (1 << 31)
#define DESC_RXSTS_DAFILTERFAIL (1 << 30)
#define DESC_RXSTS_FRMLENMSK (0x3FFF << 16)
#define DESC_RXSTS_FRMLENSHFT (16)
#define DESC_RXSTS_ERROR (1 << 15)
#define DESC_RXSTS_RXTRUNCATED (1 << 14)
#define DESC_RXSTS_SAFILTERFAIL (1 << 13)
#define DESC_RXSTS_RXIPC_GIANTFRAME (1 << 12)
#define DESC_RXSTS_RXDAMAGED (1 << 11)
#define DESC_RXSTS_RXVLANTAG (1 << 10)
#define DESC_RXSTS_RXFIRST (1 << 9)
#define DESC_RXSTS_RXLAST (1 << 8)
#define DESC_RXSTS_RXIPC_GIANT (1 << 7)
#define DESC_RXSTS_RXCOLLISION (1 << 6)
#define DESC_RXSTS_RXFRAMEETHER (1 << 5)
#define DESC_RXSTS_RXWATCHDOG (1 << 4)
#define DESC_RXSTS_RXMIIERROR (1 << 3)
#define DESC_RXSTS_RXDRIBBLING (1 << 2)
#define DESC_RXSTS_RXCRC (1 << 1)
/*
* dmamac_cntl definitions
*/
/* tx control bits definitions */
#if defined(CONFIG_DW_ALTDESCRIPTOR)
#define DESC_TXCTRL_SIZE1MASK (0x1FFF << 0)
#define DESC_TXCTRL_SIZE1SHFT (0)
#define DESC_TXCTRL_SIZE2MASK (0x1FFF << 16)
#define DESC_TXCTRL_SIZE2SHFT (16)
#else
#define DESC_TXCTRL_TXINT (1 << 31)
#define DESC_TXCTRL_TXLAST (1 << 30)
#define DESC_TXCTRL_TXFIRST (1 << 29)
#define DESC_TXCTRL_TXCHECKINSCTRL (3 << 27)
#define DESC_TXCTRL_TXCRCDIS (1 << 26)
#define DESC_TXCTRL_TXRINGEND (1 << 25)
#define DESC_TXCTRL_TXCHAIN (1 << 24)
#define DESC_TXCTRL_SIZE1MASK (0x7FF << 0)
#define DESC_TXCTRL_SIZE1SHFT (0)
#define DESC_TXCTRL_SIZE2MASK (0x7FF << 11)
#define DESC_TXCTRL_SIZE2SHFT (11)
#endif
/* rx control bits definitions */
#if defined(CONFIG_DW_ALTDESCRIPTOR)
#define DESC_RXCTRL_RXINTDIS (1 << 31)
#define DESC_RXCTRL_RXRINGEND (1 << 15)
#define DESC_RXCTRL_RXCHAIN (1 << 14)
#define DESC_RXCTRL_SIZE1MASK (0x1FFF << 0)
#define DESC_RXCTRL_SIZE1SHFT (0)
#define DESC_RXCTRL_SIZE2MASK (0x1FFF << 16)
#define DESC_RXCTRL_SIZE2SHFT (16)
#else
#define DESC_RXCTRL_RXINTDIS (1 << 31)
#define DESC_RXCTRL_RXRINGEND (1 << 25)
#define DESC_RXCTRL_RXCHAIN (1 << 24)
#define DESC_RXCTRL_SIZE1MASK (0x7FF << 0)
#define DESC_RXCTRL_SIZE1SHFT (0)
#define DESC_RXCTRL_SIZE2MASK (0x7FF << 11)
#define DESC_RXCTRL_SIZE2SHFT (11)
#endif
struct dw_eth_dev {
u32 address;
u32 speed;
u32 duplex;
u32 tx_currdescnum;
u32 rx_currdescnum;
u32 padding;
struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
char txbuffs[TX_TOTAL_BUFSIZE];
char rxbuffs[RX_TOTAL_BUFSIZE];
struct eth_mac_regs *mac_regs_p;
struct eth_dma_regs *dma_regs_p;
struct eth_device *dev;
} __attribute__ ((aligned(8)));
/* Speed specific definitions */
#define SPEED_10M 1
#define SPEED_100M 2
#define SPEED_1000M 3
/* Duplex mode specific definitions */
#define HALF_DUPLEX 1
#define FULL_DUPLEX 2
#endif

12
drivers/net/dm9000x.c
View File

@ -117,12 +117,12 @@ static void DM9000_iow(int reg, u8 value);
/* DM9000 network board routine ---------------------------- */
#define DM9000_outb(d,r) writeb(d, r)
#define DM9000_outw(d,r) writew(d, r)
#define DM9000_outl(d,r) writel(d, r)
#define DM9000_inb(r) readb(r)
#define DM9000_inw(r) readw(r)
#define DM9000_inl(r) readl(r)
#define DM9000_outb(d,r) writeb(d, (volatile u8 *)(r))
#define DM9000_outw(d,r) writew(d, (volatile u16 *)(r))
#define DM9000_outl(d,r) writel(d, (volatile u32 *)(r))
#define DM9000_inb(r) readb((volatile u8 *)(r))
#define DM9000_inw(r) readw((volatile u16 *)(r))
#define DM9000_inl(r) readl((volatile u32 *)(r))
#ifdef CONFIG_DM9000_DEBUG
static void

505
drivers/net/kirkwood_egiga.h
View File

@ -1,505 +0,0 @@
/*
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
* based on - Driver for MV64360X ethernet ports
* Copyright (C) 2002 rabeeh@galileo.co.il
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef __EGIGA_H__
#define __EGIGA_H__
#define MAX_KWGBE_DEVS 2 /*controller has two ports */
/* PHY_BASE_ADR is board specific and can be configured */
#if defined (CONFIG_PHY_BASE_ADR)
#define PHY_BASE_ADR CONFIG_PHY_BASE_ADR
#else
#define PHY_BASE_ADR 0x08 /* default phy base addr */
#endif
/* Constants */
#define INT_CAUSE_UNMASK_ALL 0x0007ffff
#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
#define MRU_MASK 0xfff1ffff
#define PHYADR_MASK 0x0000001f
#define PHYREG_MASK 0x0000001f
#define QTKNBKT_DEF_VAL 0x3fffffff
#define QMTBS_DEF_VAL 0x000003ff
#define QTKNRT_DEF_VAL 0x0000fcff
#define RXUQ 0 /* Used Rx queue */
#define TXUQ 0 /* Used Rx queue */
#define to_dkwgbe(_kd) container_of(_kd, struct kwgbe_device, dev)
#define KWGBEREG_WR(adr, val) writel(val, &adr)
#define KWGBEREG_RD(adr) readl(&adr)
#define KWGBEREG_BITS_RESET(adr, val) writel(readl(&adr) & ~(val), &adr)
#define KWGBEREG_BITS_SET(adr, val) writel(readl(&adr) | val, &adr)
/* Default port configuration value */
#define PRT_CFG_VAL ( \
KWGBE_UCAST_MOD_NRML | \
KWGBE_DFLT_RXQ(RXUQ) | \
KWGBE_DFLT_RX_ARPQ(RXUQ) | \
KWGBE_RX_BC_IF_NOT_IP_OR_ARP | \
KWGBE_RX_BC_IF_IP | \
KWGBE_RX_BC_IF_ARP | \
KWGBE_CPTR_TCP_FRMS_DIS | \
KWGBE_CPTR_UDP_FRMS_DIS | \
KWGBE_DFLT_RX_TCPQ(RXUQ) | \
KWGBE_DFLT_RX_UDPQ(RXUQ) | \
KWGBE_DFLT_RX_BPDUQ(RXUQ))
/* Default port extend configuration value */
#define PORT_CFG_EXTEND_VALUE \
KWGBE_SPAN_BPDU_PACKETS_AS_NORMAL | \
KWGBE_PARTITION_DIS | \
KWGBE_TX_CRC_GENERATION_EN
#define GT_KWGBE_IPG_INT_RX(value) ((value & 0x3fff) << 8)
/* Default sdma control value */
#define PORT_SDMA_CFG_VALUE ( \
KWGBE_RX_BURST_SIZE_16_64BIT | \
KWGBE_BLM_RX_NO_SWAP | \
KWGBE_BLM_TX_NO_SWAP | \
GT_KWGBE_IPG_INT_RX(RXUQ) | \
KWGBE_TX_BURST_SIZE_16_64BIT)
/* Default port serial control value */
#define PORT_SERIAL_CONTROL_VALUE ( \
KWGBE_FORCE_LINK_PASS | \
KWGBE_DIS_AUTO_NEG_FOR_DUPLX | \
KWGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
KWGBE_ADV_NO_FLOW_CTRL | \
KWGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
KWGBE_FORCE_BP_MODE_NO_JAM | \
(1 << 9) /* Reserved bit has to be 1 */ | \
KWGBE_DO_NOT_FORCE_LINK_FAIL | \
KWGBE_EN_AUTO_NEG_SPEED_GMII | \
KWGBE_DTE_ADV_0 | \
KWGBE_MIIPHY_MAC_MODE | \
KWGBE_AUTO_NEG_NO_CHANGE | \
KWGBE_MAX_RX_PACKET_1552BYTE | \
KWGBE_CLR_EXT_LOOPBACK | \
KWGBE_SET_FULL_DUPLEX_MODE | \
KWGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX)
/* Tx WRR confoguration macros */
#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */
#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_FFFF /* PMTBS reg (default) */
#define PORT_TOKEN_RATE 1023 /* PTTBRC reg (default) */
/* MAC accepet/reject macros */
#define ACCEPT_MAC_ADDR 0
#define REJECT_MAC_ADDR 1
/* Size of a Tx/Rx descriptor used in chain list data structure */
#define KW_RXQ_DESC_ALIGNED_SIZE \
(((sizeof(struct kwgbe_rxdesc) / PKTALIGN) + 1) * PKTALIGN)
/* Buffer offset from buffer pointer */
#define RX_BUF_OFFSET 0x2
/* Port serial status reg (PSR) */
#define KWGBE_INTERFACE_GMII_MII 0
#define KWGBE_INTERFACE_PCM 1
#define KWGBE_LINK_IS_DOWN 0
#define KWGBE_LINK_IS_UP (1 << 1)
#define KWGBE_PORT_AT_HALF_DUPLEX 0
#define KWGBE_PORT_AT_FULL_DUPLEX (1 << 2)
#define KWGBE_RX_FLOW_CTRL_DISD 0
#define KWGBE_RX_FLOW_CTRL_ENBALED (1 << 3)
#define KWGBE_GMII_SPEED_100_10 0
#define KWGBE_GMII_SPEED_1000 (1 << 4)
#define KWGBE_MII_SPEED_10 0
#define KWGBE_MII_SPEED_100 (1 << 5)
#define KWGBE_NO_TX 0
#define KWGBE_TX_IN_PROGRESS (1 << 7)
#define KWGBE_BYPASS_NO_ACTIVE 0
#define KWGBE_BYPASS_ACTIVE (1 << 8)
#define KWGBE_PORT_NOT_AT_PARTN_STT 0
#define KWGBE_PORT_AT_PARTN_STT (1 << 9)
#define KWGBE_PORT_TX_FIFO_NOT_EMPTY 0
#define KWGBE_PORT_TX_FIFO_EMPTY (1 << 10)
/* These macros describes the Port configuration reg (Px_cR) bits */
#define KWGBE_UCAST_MOD_NRML 0
#define KWGBE_UNICAST_PROMISCUOUS_MODE 1
#define KWGBE_DFLT_RXQ(_x) (_x << 1)
#define KWGBE_DFLT_RX_ARPQ(_x) (_x << 4)
#define KWGBE_RX_BC_IF_NOT_IP_OR_ARP 0
#define KWGBE_REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7)
#define KWGBE_RX_BC_IF_IP 0
#define KWGBE_REJECT_BC_IF_IP (1 << 8)
#define KWGBE_RX_BC_IF_ARP 0
#define KWGBE_REJECT_BC_IF_ARP (1 << 9)
#define KWGBE_TX_AM_NO_UPDATE_ERR_SMRY (1 << 12)
#define KWGBE_CPTR_TCP_FRMS_DIS 0
#define KWGBE_CPTR_TCP_FRMS_EN (1 << 14)
#define KWGBE_CPTR_UDP_FRMS_DIS 0
#define KWGBE_CPTR_UDP_FRMS_EN (1 << 15)
#define KWGBE_DFLT_RX_TCPQ(_x) (_x << 16)
#define KWGBE_DFLT_RX_UDPQ(_x) (_x << 19)
#define KWGBE_DFLT_RX_BPDUQ(_x) (_x << 22)
#define KWGBE_DFLT_RX_TCP_CHKSUM_MODE (1 << 25)
/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
#define KWGBE_CLASSIFY_EN 1
#define KWGBE_SPAN_BPDU_PACKETS_AS_NORMAL 0
#define KWGBE_SPAN_BPDU_PACKETS_TO_RX_Q7 (1 << 1)
#define KWGBE_PARTITION_DIS 0
#define KWGBE_PARTITION_EN (1 << 2)
#define KWGBE_TX_CRC_GENERATION_EN 0
#define KWGBE_TX_CRC_GENERATION_DIS (1 << 3)
/* These macros describes the Port Sdma configuration reg (SDCR) bits */
#define KWGBE_RIFB 1
#define KWGBE_RX_BURST_SIZE_1_64BIT 0
#define KWGBE_RX_BURST_SIZE_2_64BIT (1 << 1)
#define KWGBE_RX_BURST_SIZE_4_64BIT (1 << 2)
#define KWGBE_RX_BURST_SIZE_8_64BIT ((1 << 2) | (1 << 1))
#define KWGBE_RX_BURST_SIZE_16_64BIT (1 << 3)
#define KWGBE_BLM_RX_NO_SWAP (1 << 4)
#define KWGBE_BLM_RX_BYTE_SWAP 0
#define KWGBE_BLM_TX_NO_SWAP (1 << 5)
#define KWGBE_BLM_TX_BYTE_SWAP 0
#define KWGBE_DESCRIPTORS_BYTE_SWAP (1 << 6)
#define KWGBE_DESCRIPTORS_NO_SWAP 0
#define KWGBE_TX_BURST_SIZE_1_64BIT 0
#define KWGBE_TX_BURST_SIZE_2_64BIT (1 << 22)
#define KWGBE_TX_BURST_SIZE_4_64BIT (1 << 23)
#define KWGBE_TX_BURST_SIZE_8_64BIT ((1 << 23) | (1 << 22))
#define KWGBE_TX_BURST_SIZE_16_64BIT (1 << 24)
/* These macros describes the Port serial control reg (PSCR) bits */
#define KWGBE_SERIAL_PORT_DIS 0
#define KWGBE_SERIAL_PORT_EN 1
#define KWGBE_FORCE_LINK_PASS (1 << 1)
#define KWGBE_DO_NOT_FORCE_LINK_PASS 0
#define KWGBE_EN_AUTO_NEG_FOR_DUPLX 0
#define KWGBE_DIS_AUTO_NEG_FOR_DUPLX (1 << 2)
#define KWGBE_EN_AUTO_NEG_FOR_FLOW_CTRL 0
#define KWGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
#define KWGBE_ADV_NO_FLOW_CTRL 0
#define KWGBE_ADV_SYMMETRIC_FLOW_CTRL (1 << 4)
#define KWGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
#define KWGBE_FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5)
#define KWGBE_FORCE_BP_MODE_NO_JAM 0
#define KWGBE_FORCE_BP_MODE_JAM_TX (1 << 7)
#define KWGBE_FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1 << 8)
#define KWGBE_FORCE_LINK_FAIL 0
#define KWGBE_DO_NOT_FORCE_LINK_FAIL (1 << 10)
#define KWGBE_DIS_AUTO_NEG_SPEED_GMII (1 << 13)
#define KWGBE_EN_AUTO_NEG_SPEED_GMII 0
#define KWGBE_DTE_ADV_0 0
#define KWGBE_DTE_ADV_1 (1 << 14)
#define KWGBE_MIIPHY_MAC_MODE 0
#define KWGBE_MIIPHY_PHY_MODE (1 << 15)
#define KWGBE_AUTO_NEG_NO_CHANGE 0
#define KWGBE_RESTART_AUTO_NEG (1 << 16)
#define KWGBE_MAX_RX_PACKET_1518BYTE 0
#define KWGBE_MAX_RX_PACKET_1522BYTE (1 << 17)
#define KWGBE_MAX_RX_PACKET_1552BYTE (1 << 18)
#define KWGBE_MAX_RX_PACKET_9022BYTE ((1 << 18) | (1 << 17))
#define KWGBE_MAX_RX_PACKET_9192BYTE (1 << 19)
#define KWGBE_MAX_RX_PACKET_9700BYTE ((1 << 19) | (1 << 17))
#define KWGBE_SET_EXT_LOOPBACK (1 << 20)
#define KWGBE_CLR_EXT_LOOPBACK 0
#define KWGBE_SET_FULL_DUPLEX_MODE (1 << 21)
#define KWGBE_SET_HALF_DUPLEX_MODE 0
#define KWGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22)
#define KWGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
#define KWGBE_SET_GMII_SPEED_TO_10_100 0
#define KWGBE_SET_GMII_SPEED_TO_1000 (1 << 23)
#define KWGBE_SET_MII_SPEED_TO_10 0
#define KWGBE_SET_MII_SPEED_TO_100 (1 << 24)
/* SMI register fields */
#define KWGBE_PHY_SMI_TIMEOUT 10000
#define KWGBE_PHY_SMI_DATA_OFFS 0 /* Data */
#define KWGBE_PHY_SMI_DATA_MASK (0xffff << KWGBE_PHY_SMI_DATA_OFFS)
#define KWGBE_PHY_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
#define KWGBE_PHY_SMI_DEV_ADDR_MASK (PHYADR_MASK << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
#define KWGBE_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr */
#define KWGBE_SMI_REG_ADDR_MASK (PHYADR_MASK << KWGBE_SMI_REG_ADDR_OFFS)
#define KWGBE_PHY_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
#define KWGBE_PHY_SMI_OPCODE_MASK (3 << KWGBE_PHY_SMI_OPCODE_OFFS)
#define KWGBE_PHY_SMI_OPCODE_WRITE (0 << KWGBE_PHY_SMI_OPCODE_OFFS)
#define KWGBE_PHY_SMI_OPCODE_READ (1 << KWGBE_PHY_SMI_OPCODE_OFFS)
#define KWGBE_PHY_SMI_READ_VALID_MASK (1 << 27) /* Read Valid */
#define KWGBE_PHY_SMI_BUSY_MASK (1 << 28) /* Busy */
/* SDMA command status fields macros */
/* Tx & Rx descriptors status */
#define KWGBE_ERROR_SUMMARY 1
/* Tx & Rx descriptors command */
#define KWGBE_BUFFER_OWNED_BY_DMA (1 << 31)
/* Tx descriptors status */
#define KWGBE_LC_ERROR 0
#define KWGBE_UR_ERROR (1 << 1)
#define KWGBE_RL_ERROR (1 << 2)
#define KWGBE_LLC_SNAP_FORMAT (1 << 9)
#define KWGBE_TX_LAST_FRAME (1 << 20)
/* Rx descriptors status */
#define KWGBE_CRC_ERROR 0
#define KWGBE_OVERRUN_ERROR (1 << 1)
#define KWGBE_MAX_FRAME_LENGTH_ERROR (1 << 2)
#define KWGBE_RESOURCE_ERROR ((1 << 2) | (1 << 1))
#define KWGBE_VLAN_TAGGED (1 << 19)
#define KWGBE_BPDU_FRAME (1 << 20)
#define KWGBE_TCP_FRAME_OVER_IP_V_4 0
#define KWGBE_UDP_FRAME_OVER_IP_V_4 (1 << 21)
#define KWGBE_OTHER_FRAME_TYPE (1 << 22)
#define KWGBE_LAYER_2_IS_KWGBE_V_2 (1 << 23)
#define KWGBE_FRAME_TYPE_IP_V_4 (1 << 24)
#define KWGBE_FRAME_HEADER_OK (1 << 25)
#define KWGBE_RX_LAST_DESC (1 << 26)
#define KWGBE_RX_FIRST_DESC (1 << 27)
#define KWGBE_UNKNOWN_DESTINATION_ADDR (1 << 28)
#define KWGBE_RX_EN_INTERRUPT (1 << 29)
#define KWGBE_LAYER_4_CHECKSUM_OK (1 << 30)
/* Rx descriptors byte count */
#define KWGBE_FRAME_FRAGMENTED (1 << 2)
/* Tx descriptors command */
#define KWGBE_LAYER_4_CHECKSUM_FIRST_DESC (1 << 10)
#define KWGBE_FRAME_SET_TO_VLAN (1 << 15)
#define KWGBE_TCP_FRAME 0
#define KWGBE_UDP_FRAME (1 << 16)
#define KWGBE_GEN_TCP_UDP_CHECKSUM (1 << 17)
#define KWGBE_GEN_IP_V_4_CHECKSUM (1 << 18)
#define KWGBE_ZERO_PADDING (1 << 19)
#define KWGBE_TX_LAST_DESC (1 << 20)
#define KWGBE_TX_FIRST_DESC (1 << 21)
#define KWGBE_GEN_CRC (1 << 22)
#define KWGBE_TX_EN_INTERRUPT (1 << 23)
#define KWGBE_AUTO_MODE (1 << 30)
/* Address decode parameters */
/* Ethernet Base Address Register bits */
#define EBAR_TARGET_DRAM 0x00000000
#define EBAR_TARGET_DEVICE 0x00000001
#define EBAR_TARGET_CBS 0x00000002
#define EBAR_TARGET_PCI0 0x00000003
#define EBAR_TARGET_PCI1 0x00000004
#define EBAR_TARGET_CUNIT 0x00000005
#define EBAR_TARGET_AUNIT 0x00000006
#define EBAR_TARGET_GUNIT 0x00000007
/* Window attrib */
#define EBAR_DRAM_CS0 0x00000E00
#define EBAR_DRAM_CS1 0x00000D00
#define EBAR_DRAM_CS2 0x00000B00
#define EBAR_DRAM_CS3 0x00000700
/* DRAM Target interface */
#define EBAR_DRAM_NO_CACHE_COHERENCY 0x00000000
#define EBAR_DRAM_CACHE_COHERENCY_WT 0x00001000
#define EBAR_DRAM_CACHE_COHERENCY_WB 0x00002000
/* Device Bus Target interface */
#define EBAR_DEVICE_DEVCS0 0x00001E00
#define EBAR_DEVICE_DEVCS1 0x00001D00
#define EBAR_DEVICE_DEVCS2 0x00001B00
#define EBAR_DEVICE_DEVCS3 0x00001700
#define EBAR_DEVICE_BOOTCS3 0x00000F00
/* PCI Target interface */
#define EBAR_PCI_BYTE_SWAP 0x00000000
#define EBAR_PCI_NO_SWAP 0x00000100
#define EBAR_PCI_BYTE_WORD_SWAP 0x00000200
#define EBAR_PCI_WORD_SWAP 0x00000300
#define EBAR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000
#define EBAR_PCI_NO_SNOOP_ASSERT 0x00000400
#define EBAR_PCI_IO_SPACE 0x00000000
#define EBAR_PCI_MEMORY_SPACE 0x00000800
#define EBAR_PCI_REQ64_FORCE 0x00000000
#define EBAR_PCI_REQ64_SIZE 0x00001000
/* Window access control */
#define EWIN_ACCESS_NOT_ALLOWED 0
#define EWIN_ACCESS_READ_ONLY 1
#define EWIN_ACCESS_FULL ((1 << 1) | 1)
/* structures represents Controller registers */
struct kwgbe_barsz {
u32 bar;
u32 size;
};
struct kwgbe_rxcdp {
struct kwgbe_rxdesc *rxcdp;
u32 rxcdp_pad[3];
};
struct kwgbe_tqx {
u32 qxttbc;
u32 tqxtbc;
u32 tqxac;
u32 tqxpad;
};
struct kwgbe_registers {
u32 phyadr;
u32 smi;
u32 euda;
u32 eudid;
u8 pad1[0x080 - 0x00c - 4];
u32 euic;
u32 euim;
u8 pad2[0x094 - 0x084 - 4];
u32 euea;
u32 euiae;
u8 pad3[0x0b0 - 0x098 - 4];
u32 euc;
u8 pad3a[0x200 - 0x0b0 - 4];
struct kwgbe_barsz barsz[6];
u8 pad4[0x280 - 0x22c - 4];
u32 ha_remap[4];
u32 bare;
u32 epap;
u8 pad5[0x400 - 0x294 - 4];
u32 pxc;
u32 pxcx;
u32 mii_ser_params;
u8 pad6[0x410 - 0x408 - 4];
u32 evlane;
u32 macal;
u32 macah;
u32 sdc;
u32 dscp[7];
u32 psc0;
u32 vpt2p;
u32 ps0;
u32 tqc;
u32 psc1;
u32 ps1;
u32 mrvl_header;
u8 pad7[0x460 - 0x454 - 4];
u32 ic;
u32 ice;
u32 pim;
u32 peim;
u8 pad8[0x474 - 0x46c - 4];
u32 pxtfut;
u32 pad9;
u32 pxmfs;
u32 pad10;
u32 pxdfc;
u32 pxofc;
u8 pad11[0x494 - 0x488 - 4];
u32 peuiae;
u8 pad12[0x4bc - 0x494 - 4];
u32 eth_type_prio;
u8 pad13[0x4dc - 0x4bc - 4];
u32 tqfpc;
u32 pttbrc;
u32 tqc1;
u32 pmtu;
u32 pmtbs;
u8 pad14[0x60c - 0x4ec - 4];
struct kwgbe_rxcdp rxcdp[7];
struct kwgbe_rxdesc *rxcdp7;
u32 rqc;
struct kwgbe_txdesc *tcsdp;
u8 pad15[0x6c0 - 0x684 - 4];
struct kwgbe_txdesc *tcqdp[8];
u8 pad16[0x700 - 0x6dc - 4];
struct kwgbe_tqx tqx[8];
u32 pttbc;
u8 pad17[0x7a8 - 0x780 - 4];
u32 tqxipg0;
u32 pad18[3];
u32 tqxipg1;
u8 pad19[0x7c0 - 0x7b8 - 4];
u32 hitkninlopkt;
u32 hitkninasyncpkt;
u32 lotkninasyncpkt;
u32 pad20;
u32 ts;
u8 pad21[0x3000 - 0x27d0 - 4];
u32 pad20_1[32]; /* mib counter registes */
u8 pad22[0x3400 - 0x3000 - sizeof(u32) * 32];
u32 dfsmt[64];
u32 dfomt[64];
u32 dfut[4];
u8 pad23[0xe20c0 - 0x7360c - 4];
u32 pmbus_top_arbiter;
};
/* structures/enums needed by driver */
enum kwgbe_adrwin {
KWGBE_WIN0,
KWGBE_WIN1,
KWGBE_WIN2,
KWGBE_WIN3,
KWGBE_WIN4,
KWGBE_WIN5
};
enum kwgbe_target {
KWGBE_TARGET_DRAM,
KWGBE_TARGET_DEV,
KWGBE_TARGET_CBS,
KWGBE_TARGET_PCI0,
KWGBE_TARGET_PCI1
};
struct kwgbe_winparam {
enum kwgbe_adrwin win; /* Window number */
enum kwgbe_target target; /* System targets */
u16 attrib; /* BAR attrib. See above macros */
u32 base_addr; /* Window base address in u32 form */
u32 high_addr; /* Window high address in u32 form */
u32 size; /* Size in MBytes. Must be % 64Kbyte. */
int enable; /* Enable/disable access to the window. */
u16 access_ctrl; /*Access ctrl register. see above macros */
};
struct kwgbe_rxdesc {
u32 cmd_sts; /* Descriptor command status */
u16 buf_size; /* Buffer size */
u16 byte_cnt; /* Descriptor buffer byte count */
u8 *buf_ptr; /* Descriptor buffer pointer */
struct kwgbe_rxdesc *nxtdesc_p; /* Next descriptor pointer */
};
struct kwgbe_txdesc {
u32 cmd_sts; /* Descriptor command status */
u16 l4i_chk; /* CPU provided TCP Checksum */
u16 byte_cnt; /* Descriptor buffer byte count */
u8 *buf_ptr; /* Descriptor buffer ptr */
struct kwgbe_txdesc *nxtdesc_p; /* Next descriptor ptr */
};
/* port device data struct */
struct kwgbe_device {
struct eth_device dev;
struct kwgbe_registers *regs;
struct kwgbe_txdesc *p_txdesc;
struct kwgbe_rxdesc *p_rxdesc;
struct kwgbe_rxdesc *p_rxdesc_curr;
u8 *p_rxbuf;
u8 *p_aligned_txbuf;
};
#endif /* __EGIGA_H__ */

23
drivers/net/macb.c
View File

@ -439,8 +439,6 @@ static int macb_init(struct eth_device *netdev, bd_t *bd)
{
struct macb_device *macb = to_macb(netdev);
unsigned long paddr;
u32 hwaddr_bottom;
u16 hwaddr_top;
int i;
/*
@ -469,12 +467,6 @@ static int macb_init(struct eth_device *netdev, bd_t *bd)
macb_writel(macb, RBQP, macb->rx_ring_dma);
macb_writel(macb, TBQP, macb->tx_ring_dma);
/* set hardware address */
hwaddr_bottom = cpu_to_le32(*((u32 *)netdev->enetaddr));
macb_writel(macb, SA1B, hwaddr_bottom);
hwaddr_top = cpu_to_le16(*((u16 *)(netdev->enetaddr + 4)));
macb_writel(macb, SA1T, hwaddr_top);
/* choose RMII or MII mode. This depends on the board */
#ifdef CONFIG_RMII
#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
@ -521,6 +513,20 @@ static void macb_halt(struct eth_device *netdev)
macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
}
static int macb_write_hwaddr(struct eth_device *dev)
{
struct macb_device *macb = to_macb(dev);
u32 hwaddr_bottom;
u16 hwaddr_top;
/* set hardware address */
hwaddr_bottom = cpu_to_le32(*((u32 *)dev->enetaddr));
macb_writel(macb, SA1B, hwaddr_bottom);
hwaddr_top = cpu_to_le16(*((u16 *)(dev->enetaddr + 4)));
macb_writel(macb, SA1T, hwaddr_top);
return 0;
}
int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
{
struct macb_device *macb;
@ -554,6 +560,7 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
netdev->halt = macb_halt;
netdev->send = macb_send;
netdev->recv = macb_recv;
netdev->write_hwaddr = macb_write_hwaddr;
/*
* Do some basic initialization so that we at least can talk

379
drivers/net/kirkwood_egiga.c → drivers/net/mvgbe.c
View File

@ -35,11 +35,19 @@
#include <asm/errno.h>
#include <asm/types.h>
#include <asm/byteorder.h>
#include <asm/arch/kirkwood.h>
#include "kirkwood_egiga.h"
#define KIRKWOOD_PHY_ADR_REQUEST 0xee
#define KWGBE_SMI_REG (((struct kwgbe_registers *)KW_EGIGA0_BASE)->smi)
#if defined(CONFIG_KIRKWOOD)
#include <asm/arch/kirkwood.h>
#elif defined(CONFIG_ORION5X)
#include <asm/arch/orion5x.h>
#endif
#include "mvgbe.h"
DECLARE_GLOBAL_DATA_PTR;
#define MV_PHY_ADR_REQUEST 0xee
#define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi)
/*
* smi_reg_read - miiphy_read callback function.
@ -49,16 +57,16 @@
static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
{
struct eth_device *dev = eth_get_dev_by_name(devname);
struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
struct kwgbe_registers *regs = dkwgbe->regs;
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
struct mvgbe_registers *regs = dmvgbe->regs;
u32 smi_reg;
u32 timeout;
/* Phyadr read request */
if (phy_adr == KIRKWOOD_PHY_ADR_REQUEST &&
reg_ofs == KIRKWOOD_PHY_ADR_REQUEST) {
if (phy_adr == MV_PHY_ADR_REQUEST &&
reg_ofs == MV_PHY_ADR_REQUEST) {
/* */
*data = (u16) (KWGBEREG_RD(regs->phyadr) & PHYADR_MASK);
*data = (u16) (MVGBE_REG_RD(regs->phyadr) & PHYADR_MASK);
return 0;
}
/* check parameters */
@ -73,42 +81,43 @@ static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
return -EFAULT;
}
timeout = KWGBE_PHY_SMI_TIMEOUT;
timeout = MVGBE_PHY_SMI_TIMEOUT;
/* wait till the SMI is not busy */
do {
/* read smi register */
smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
if (timeout-- == 0) {
printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
return -EFAULT;
}
} while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK);
} while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK);
/* fill the phy address and regiser offset and read opcode */
smi_reg = (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
| (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS)
| KWGBE_PHY_SMI_OPCODE_READ;
smi_reg = (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
| (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS)
| MVGBE_PHY_SMI_OPCODE_READ;
/* write the smi register */
KWGBEREG_WR(KWGBE_SMI_REG, smi_reg);
MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg);
/*wait till read value is ready */
timeout = KWGBE_PHY_SMI_TIMEOUT;
timeout = MVGBE_PHY_SMI_TIMEOUT;
do {
/* read smi register */
smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
if (timeout-- == 0) {
printf("Err..(%s) SMI read ready timeout\n",
__FUNCTION__);
return -EFAULT;
}
} while (!(smi_reg & KWGBE_PHY_SMI_READ_VALID_MASK));
} while (!(smi_reg & MVGBE_PHY_SMI_READ_VALID_MASK));
/* Wait for the data to update in the SMI register */
for (timeout = 0; timeout < KWGBE_PHY_SMI_TIMEOUT; timeout++) ;
for (timeout = 0; timeout < MVGBE_PHY_SMI_TIMEOUT; timeout++)
;
*data = (u16) (KWGBEREG_RD(KWGBE_SMI_REG) & KWGBE_PHY_SMI_DATA_MASK);
*data = (u16) (MVGBE_REG_RD(MVGBE_SMI_REG) & MVGBE_PHY_SMI_DATA_MASK);
debug("%s:(adr %d, off %d) value= %04x\n", __FUNCTION__, phy_adr,
reg_ofs, *data);
@ -125,15 +134,15 @@ static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
static int smi_reg_write(char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
{
struct eth_device *dev = eth_get_dev_by_name(devname);
struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
struct kwgbe_registers *regs = dkwgbe->regs;
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
struct mvgbe_registers *regs = dmvgbe->regs;
u32 smi_reg;
u32 timeout;
/* Phyadr write request*/
if (phy_adr == KIRKWOOD_PHY_ADR_REQUEST &&
reg_ofs == KIRKWOOD_PHY_ADR_REQUEST) {
KWGBEREG_WR(regs->phyadr, data);
if (phy_adr == MV_PHY_ADR_REQUEST &&
reg_ofs == MV_PHY_ADR_REQUEST) {
MVGBE_REG_WR(regs->phyadr, data);
return 0;
}
@ -148,24 +157,24 @@ static int smi_reg_write(char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
}
/* wait till the SMI is not busy */
timeout = KWGBE_PHY_SMI_TIMEOUT;
timeout = MVGBE_PHY_SMI_TIMEOUT;
do {
/* read smi register */
smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
if (timeout-- == 0) {
printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
return -ETIME;
}
} while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK);
} while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK);
/* fill the phy addr and reg offset and write opcode and data */
smi_reg = (data << KWGBE_PHY_SMI_DATA_OFFS);
smi_reg |= (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
| (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS);
smi_reg &= ~KWGBE_PHY_SMI_OPCODE_READ;
smi_reg = (data << MVGBE_PHY_SMI_DATA_OFFS);
smi_reg |= (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
| (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS);
smi_reg &= ~MVGBE_PHY_SMI_OPCODE_READ;
/* write the smi register */
KWGBEREG_WR(KWGBE_SMI_REG, smi_reg);
MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg);
return 0;
}
@ -202,52 +211,52 @@ static void stop_queue(u32 * qreg)
* @regs Register struct pointer.
* @param Address decode parameter struct.
*/
static void set_access_control(struct kwgbe_registers *regs,
struct kwgbe_winparam *param)
static void set_access_control(struct mvgbe_registers *regs,
struct mvgbe_winparam *param)
{
u32 access_prot_reg;
/* Set access control register */
access_prot_reg = KWGBEREG_RD(regs->epap);
access_prot_reg = MVGBE_REG_RD(regs->epap);
/* clear window permission */
access_prot_reg &= (~(3 << (param->win * 2)));
access_prot_reg |= (param->access_ctrl << (param->win * 2));
KWGBEREG_WR(regs->epap, access_prot_reg);
MVGBE_REG_WR(regs->epap, access_prot_reg);
/* Set window Size reg (SR) */
KWGBEREG_WR(regs->barsz[param->win].size,
MVGBE_REG_WR(regs->barsz[param->win].size,
(((param->size / 0x10000) - 1) << 16));
/* Set window Base address reg (BA) */
KWGBEREG_WR(regs->barsz[param->win].bar,
MVGBE_REG_WR(regs->barsz[param->win].bar,
(param->target | param->attrib | param->base_addr));
/* High address remap reg (HARR) */
if (param->win < 4)
KWGBEREG_WR(regs->ha_remap[param->win], param->high_addr);
MVGBE_REG_WR(regs->ha_remap[param->win], param->high_addr);
/* Base address enable reg (BARER) */
if (param->enable == 1)
KWGBEREG_BITS_RESET(regs->bare, (1 << param->win));
MVGBE_REG_BITS_RESET(regs->bare, (1 << param->win));
else
KWGBEREG_BITS_SET(regs->bare, (1 << param->win));
MVGBE_REG_BITS_SET(regs->bare, (1 << param->win));
}
static void set_dram_access(struct kwgbe_registers *regs)
static void set_dram_access(struct mvgbe_registers *regs)
{
struct kwgbe_winparam win_param;
struct mvgbe_winparam win_param;
int i;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
/* Set access parameters for DRAM bank i */
win_param.win = i; /* Use Ethernet window i */
/* Window target - DDR */
win_param.target = KWGBE_TARGET_DRAM;
win_param.target = MVGBE_TARGET_DRAM;
/* Enable full access */
win_param.access_ctrl = EWIN_ACCESS_FULL;
win_param.high_addr = 0;
/* Get bank base */
win_param.base_addr = kw_sdram_bar(i);
win_param.size = kw_sdram_bs(i); /* Get bank size */
/* Get bank base and size */
win_param.base_addr = gd->bd->bi_dram[i].start;
win_param.size = gd->bd->bi_dram[i].size;
if (win_param.size == 0)
win_param.enable = 0;
else
@ -268,7 +277,7 @@ static void set_dram_access(struct kwgbe_registers *regs)
win_param.attrib = EBAR_DRAM_CS3;
break;
default:
/* invalide bank, disable access */
/* invalid bank, disable access */
win_param.enable = 0;
win_param.attrib = 0;
break;
@ -284,19 +293,19 @@ static void set_dram_access(struct kwgbe_registers *regs)
* Go through all the DA filter tables (Unicast, Special Multicast & Other
* Multicast) and set each entry to 0.
*/
static void port_init_mac_tables(struct kwgbe_registers *regs)
static void port_init_mac_tables(struct mvgbe_registers *regs)
{
int table_index;
/* Clear DA filter unicast table (Ex_dFUT) */
for (table_index = 0; table_index < 4; ++table_index)
KWGBEREG_WR(regs->dfut[table_index], 0);
MVGBE_REG_WR(regs->dfut[table_index], 0);
for (table_index = 0; table_index < 64; ++table_index) {
/* Clear DA filter special multicast table (Ex_dFSMT) */
KWGBEREG_WR(regs->dfsmt[table_index], 0);
MVGBE_REG_WR(regs->dfsmt[table_index], 0);
/* Clear DA filter other multicast table (Ex_dFOMT) */
KWGBEREG_WR(regs->dfomt[table_index], 0);
MVGBE_REG_WR(regs->dfomt[table_index], 0);
}
}
@ -314,7 +323,7 @@ static void port_init_mac_tables(struct kwgbe_registers *regs)
*
* RETURN: 1 if output succeeded. 0 if option parameter is invalid.
*/
static int port_uc_addr(struct kwgbe_registers *regs, u8 uc_nibble,
static int port_uc_addr(struct mvgbe_registers *regs, u8 uc_nibble,
int option)
{
u32 unicast_reg;
@ -334,16 +343,16 @@ static int port_uc_addr(struct kwgbe_registers *regs, u8 uc_nibble,
* Clear accepts frame bit at specified unicast
* DA table entry
*/
unicast_reg = KWGBEREG_RD(regs->dfut[tbl_offset]);
unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]);
unicast_reg &= (0xFF << (8 * reg_offset));
KWGBEREG_WR(regs->dfut[tbl_offset], unicast_reg);
MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg);
break;
case ACCEPT_MAC_ADDR:
/* Set accepts frame bit at unicast DA filter table entry */
unicast_reg = KWGBEREG_RD(regs->dfut[tbl_offset]);
unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]);
unicast_reg &= (0xFF << (8 * reg_offset));
unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset));
KWGBEREG_WR(regs->dfut[tbl_offset], unicast_reg);
MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg);
break;
default:
return 0;
@ -354,7 +363,7 @@ static int port_uc_addr(struct kwgbe_registers *regs, u8 uc_nibble,
/*
* port_uc_addr_set - This function Set the port Unicast address.
*/
static void port_uc_addr_set(struct kwgbe_registers *regs, u8 * p_addr)
static void port_uc_addr_set(struct mvgbe_registers *regs, u8 * p_addr)
{
u32 mac_h;
u32 mac_l;
@ -363,92 +372,95 @@ static void port_uc_addr_set(struct kwgbe_registers *regs, u8 * p_addr)
mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
(p_addr[3] << 0);
KWGBEREG_WR(regs->macal, mac_l);
KWGBEREG_WR(regs->macah, mac_h);
MVGBE_REG_WR(regs->macal, mac_l);
MVGBE_REG_WR(regs->macah, mac_h);
/* Accept frames of this address */
port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR);
}
/*
* kwgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
* mvgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
*/
static void kwgbe_init_rx_desc_ring(struct kwgbe_device *dkwgbe)
static void mvgbe_init_rx_desc_ring(struct mvgbe_device *dmvgbe)
{
struct kwgbe_rxdesc *p_rx_desc;
struct mvgbe_rxdesc *p_rx_desc;
int i;
/* initialize the Rx descriptors ring */
p_rx_desc = dkwgbe->p_rxdesc;
p_rx_desc = dmvgbe->p_rxdesc;
for (i = 0; i < RINGSZ; i++) {
p_rx_desc->cmd_sts =
KWGBE_BUFFER_OWNED_BY_DMA | KWGBE_RX_EN_INTERRUPT;
MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT;
p_rx_desc->buf_size = PKTSIZE_ALIGN;
p_rx_desc->byte_cnt = 0;
p_rx_desc->buf_ptr = dkwgbe->p_rxbuf + i * PKTSIZE_ALIGN;
p_rx_desc->buf_ptr = dmvgbe->p_rxbuf + i * PKTSIZE_ALIGN;
if (i == (RINGSZ - 1))
p_rx_desc->nxtdesc_p = dkwgbe->p_rxdesc;
p_rx_desc->nxtdesc_p = dmvgbe->p_rxdesc;
else {
p_rx_desc->nxtdesc_p = (struct kwgbe_rxdesc *)
((u32) p_rx_desc + KW_RXQ_DESC_ALIGNED_SIZE);
p_rx_desc->nxtdesc_p = (struct mvgbe_rxdesc *)
((u32) p_rx_desc + MV_RXQ_DESC_ALIGNED_SIZE);
p_rx_desc = p_rx_desc->nxtdesc_p;
}
}
dkwgbe->p_rxdesc_curr = dkwgbe->p_rxdesc;
dmvgbe->p_rxdesc_curr = dmvgbe->p_rxdesc;
}
static int kwgbe_init(struct eth_device *dev)
static int mvgbe_init(struct eth_device *dev)
{
struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
struct kwgbe_registers *regs = dkwgbe->regs;
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
struct mvgbe_registers *regs = dmvgbe->regs;
#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
&& defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
int i;
#endif
/* setup RX rings */
kwgbe_init_rx_desc_ring(dkwgbe);
mvgbe_init_rx_desc_ring(dmvgbe);
/* Clear the ethernet port interrupts */
KWGBEREG_WR(regs->ic, 0);
KWGBEREG_WR(regs->ice, 0);
MVGBE_REG_WR(regs->ic, 0);
MVGBE_REG_WR(regs->ice, 0);
/* Unmask RX buffer and TX end interrupt */
KWGBEREG_WR(regs->pim, INT_CAUSE_UNMASK_ALL);
MVGBE_REG_WR(regs->pim, INT_CAUSE_UNMASK_ALL);
/* Unmask phy and link status changes interrupts */
KWGBEREG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT);
MVGBE_REG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT);
set_dram_access(regs);
port_init_mac_tables(regs);
port_uc_addr_set(regs, dkwgbe->dev.enetaddr);
port_uc_addr_set(regs, dmvgbe->dev.enetaddr);
/* Assign port configuration and command. */
KWGBEREG_WR(regs->pxc, PRT_CFG_VAL);
KWGBEREG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE);
KWGBEREG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE);
MVGBE_REG_WR(regs->pxc, PRT_CFG_VAL);
MVGBE_REG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE);
MVGBE_REG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE);
/* Assign port SDMA configuration */
KWGBEREG_WR(regs->sdc, PORT_SDMA_CFG_VALUE);
KWGBEREG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL);
KWGBEREG_WR(regs->tqx[0].tqxtbc, (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL);
MVGBE_REG_WR(regs->sdc, PORT_SDMA_CFG_VALUE);
MVGBE_REG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL);
MVGBE_REG_WR(regs->tqx[0].tqxtbc,
(QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL);
/* Turn off the port/RXUQ bandwidth limitation */
KWGBEREG_WR(regs->pmtu, 0);
MVGBE_REG_WR(regs->pmtu, 0);
/* Set maximum receive buffer to 9700 bytes */
KWGBEREG_WR(regs->psc0, KWGBE_MAX_RX_PACKET_9700BYTE
| (KWGBEREG_RD(regs->psc0) & MRU_MASK));
MVGBE_REG_WR(regs->psc0, MVGBE_MAX_RX_PACKET_9700BYTE
| (MVGBE_REG_RD(regs->psc0) & MRU_MASK));
/* Enable port initially */
KWGBEREG_BITS_SET(regs->psc0, KWGBE_SERIAL_PORT_EN);
MVGBE_REG_BITS_SET(regs->psc0, MVGBE_SERIAL_PORT_EN);
/*
* Set ethernet MTU for leaky bucket mechanism to 0 - this will
* disable the leaky bucket mechanism .
*/
KWGBEREG_WR(regs->pmtu, 0);
MVGBE_REG_WR(regs->pmtu, 0);
/* Assignment of Rx CRDB of given RXUQ */
KWGBEREG_WR(regs->rxcdp[RXUQ], (u32) dkwgbe->p_rxdesc_curr);
MVGBE_REG_WR(regs->rxcdp[RXUQ], (u32) dmvgbe->p_rxdesc_curr);
/* ensure previous write is done before enabling Rx DMA */
isb();
/* Enable port Rx. */
KWGBEREG_WR(regs->rqc, (1 << RXUQ));
MVGBE_REG_WR(regs->rqc, (1 << RXUQ));
#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
&& defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
@ -456,8 +468,8 @@ static int kwgbe_init(struct eth_device *dev)
for (i = 0; i < 5; i++) {
u16 phyadr;
miiphy_read(dev->name, KIRKWOOD_PHY_ADR_REQUEST,
KIRKWOOD_PHY_ADR_REQUEST, &phyadr);
miiphy_read(dev->name, MV_PHY_ADR_REQUEST,
MV_PHY_ADR_REQUEST, &phyadr);
/* Return if we get link up */
if (miiphy_link(dev->name, phyadr))
return 0;
@ -470,50 +482,50 @@ static int kwgbe_init(struct eth_device *dev)
return 0;
}
static int kwgbe_halt(struct eth_device *dev)
static int mvgbe_halt(struct eth_device *dev)
{
struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
struct kwgbe_registers *regs = dkwgbe->regs;
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
struct mvgbe_registers *regs = dmvgbe->regs;
/* Disable all gigE address decoder */
KWGBEREG_WR(regs->bare, 0x3f);
MVGBE_REG_WR(regs->bare, 0x3f);
stop_queue(&regs->tqc);
stop_queue(&regs->rqc);
/* Disable port */
KWGBEREG_BITS_RESET(regs->psc0, KWGBE_SERIAL_PORT_EN);
MVGBE_REG_BITS_RESET(regs->psc0, MVGBE_SERIAL_PORT_EN);
/* Set port is not reset */
KWGBEREG_BITS_RESET(regs->psc1, 1 << 4);
MVGBE_REG_BITS_RESET(regs->psc1, 1 << 4);
#ifdef CONFIG_SYS_MII_MODE
/* Set MMI interface up */
KWGBEREG_BITS_RESET(regs->psc1, 1 << 3);
MVGBE_REG_BITS_RESET(regs->psc1, 1 << 3);
#endif
/* Disable & mask ethernet port interrupts */
KWGBEREG_WR(regs->ic, 0);
KWGBEREG_WR(regs->ice, 0);
KWGBEREG_WR(regs->pim, 0);
KWGBEREG_WR(regs->peim, 0);
MVGBE_REG_WR(regs->ic, 0);
MVGBE_REG_WR(regs->ice, 0);
MVGBE_REG_WR(regs->pim, 0);
MVGBE_REG_WR(regs->peim, 0);
return 0;
}
static int kwgbe_write_hwaddr(struct eth_device *dev)
static int mvgbe_write_hwaddr(struct eth_device *dev)
{
struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
struct kwgbe_registers *regs = dkwgbe->regs;
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
struct mvgbe_registers *regs = dmvgbe->regs;
/* Programs net device MAC address after initialization */
port_uc_addr_set(regs, dkwgbe->dev.enetaddr);
port_uc_addr_set(regs, dmvgbe->dev.enetaddr);
return 0;
}
static int kwgbe_send(struct eth_device *dev, volatile void *dataptr,
static int mvgbe_send(struct eth_device *dev, void *dataptr,
int datasize)
{
struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
struct kwgbe_registers *regs = dkwgbe->regs;
struct kwgbe_txdesc *p_txdesc = dkwgbe->p_txdesc;
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
struct mvgbe_registers *regs = dmvgbe->regs;
struct mvgbe_txdesc *p_txdesc = dmvgbe->p_txdesc;
void *p = (void *)dataptr;
u32 cmd_sts;
@ -525,30 +537,35 @@ static int kwgbe_send(struct eth_device *dev, volatile void *dataptr,
return -1;
}
memcpy(dkwgbe->p_aligned_txbuf, p, datasize);
p = dkwgbe->p_aligned_txbuf;
memcpy(dmvgbe->p_aligned_txbuf, p, datasize);
p = dmvgbe->p_aligned_txbuf;
}
p_txdesc->cmd_sts = KWGBE_ZERO_PADDING | KWGBE_GEN_CRC;
p_txdesc->cmd_sts |= KWGBE_TX_FIRST_DESC | KWGBE_TX_LAST_DESC;
p_txdesc->cmd_sts |= KWGBE_BUFFER_OWNED_BY_DMA;
p_txdesc->cmd_sts |= KWGBE_TX_EN_INTERRUPT;
p_txdesc->cmd_sts = MVGBE_ZERO_PADDING | MVGBE_GEN_CRC;
p_txdesc->cmd_sts |= MVGBE_TX_FIRST_DESC | MVGBE_TX_LAST_DESC;
p_txdesc->cmd_sts |= MVGBE_BUFFER_OWNED_BY_DMA;
p_txdesc->cmd_sts |= MVGBE_TX_EN_INTERRUPT;
p_txdesc->buf_ptr = (u8 *) p;
p_txdesc->byte_cnt = datasize;
/* Set this tc desc as zeroth TXUQ */
MVGBE_REG_WR(regs->tcqdp[TXUQ], (u32) p_txdesc);
/* ensure tx desc writes above are performed before we start Tx DMA */
isb();
/* Apply send command using zeroth TXUQ */
KWGBEREG_WR(regs->tcqdp[TXUQ], (u32) p_txdesc);
KWGBEREG_WR(regs->tqc, (1 << TXUQ));
MVGBE_REG_WR(regs->tqc, (1 << TXUQ));
/*
* wait for packet xmit completion
*/
cmd_sts = readl(&p_txdesc->cmd_sts);
while (cmd_sts & KWGBE_BUFFER_OWNED_BY_DMA) {
while (cmd_sts & MVGBE_BUFFER_OWNED_BY_DMA) {
/* return fail if error is detected */
if ((cmd_sts & (KWGBE_ERROR_SUMMARY | KWGBE_TX_LAST_FRAME)) ==
(KWGBE_ERROR_SUMMARY | KWGBE_TX_LAST_FRAME) &&
cmd_sts & (KWGBE_UR_ERROR | KWGBE_RL_ERROR)) {
if ((cmd_sts & (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME)) ==
(MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME) &&
cmd_sts & (MVGBE_UR_ERROR | MVGBE_RL_ERROR)) {
printf("Err..(%s) in xmit packet\n", __FUNCTION__);
return -1;
}
@ -557,22 +574,22 @@ static int kwgbe_send(struct eth_device *dev, volatile void *dataptr,
return 0;
}
static int kwgbe_recv(struct eth_device *dev)
static int mvgbe_recv(struct eth_device *dev)
{
struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
struct kwgbe_rxdesc *p_rxdesc_curr = dkwgbe->p_rxdesc_curr;
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
struct mvgbe_rxdesc *p_rxdesc_curr = dmvgbe->p_rxdesc_curr;
u32 cmd_sts;
u32 timeout = 0;
/* wait untill rx packet available or timeout */
do {
if (timeout < KWGBE_PHY_SMI_TIMEOUT)
if (timeout < MVGBE_PHY_SMI_TIMEOUT)
timeout++;
else {
debug("%s time out...\n", __FUNCTION__);
return -1;
}
} while (readl(&p_rxdesc_curr->cmd_sts) & KWGBE_BUFFER_OWNED_BY_DMA);
} while (readl(&p_rxdesc_curr->cmd_sts) & MVGBE_BUFFER_OWNED_BY_DMA);
if (p_rxdesc_curr->byte_cnt != 0) {
debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n",
@ -589,13 +606,13 @@ static int kwgbe_recv(struct eth_device *dev)
cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
if ((cmd_sts &
(KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC))
!= (KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC)) {
(MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC))
!= (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC)) {
printf("Err..(%s) Dropping packet spread on"
" multiple descriptors\n", __FUNCTION__);
} else if (cmd_sts & KWGBE_ERROR_SUMMARY) {
} else if (cmd_sts & MVGBE_ERROR_SUMMARY) {
printf("Err..(%s) Dropping packet with errors\n",
__FUNCTION__);
@ -613,62 +630,72 @@ static int kwgbe_recv(struct eth_device *dev)
* free these descriptors and point next in the ring
*/
p_rxdesc_curr->cmd_sts =
KWGBE_BUFFER_OWNED_BY_DMA | KWGBE_RX_EN_INTERRUPT;
MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT;
p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
p_rxdesc_curr->byte_cnt = 0;
writel((unsigned)p_rxdesc_curr->nxtdesc_p, (u32) &dkwgbe->p_rxdesc_curr);
writel((unsigned)p_rxdesc_curr->nxtdesc_p,
(u32) &dmvgbe->p_rxdesc_curr);
return 0;
}
int kirkwood_egiga_initialize(bd_t * bis)
int mvgbe_initialize(bd_t *bis)
{
struct kwgbe_device *dkwgbe;
struct mvgbe_device *dmvgbe;
struct eth_device *dev;
int devnum;
char *s;
u8 used_ports[MAX_KWGBE_DEVS] = CONFIG_KIRKWOOD_EGIGA_PORTS;
u8 used_ports[MAX_MVGBE_DEVS] = CONFIG_MVGBE_PORTS;
for (devnum = 0; devnum < MAX_KWGBE_DEVS; devnum++) {
for (devnum = 0; devnum < MAX_MVGBE_DEVS; devnum++) {
/*skip if port is configured not to use */
if (used_ports[devnum] == 0)
continue;
if (!(dkwgbe = malloc(sizeof(struct kwgbe_device))))
dmvgbe = malloc(sizeof(struct mvgbe_device));
if (!dmvgbe)
goto error1;
memset(dkwgbe, 0, sizeof(struct kwgbe_device));
memset(dmvgbe, 0, sizeof(struct mvgbe_device));
if (!(dkwgbe->p_rxdesc =
(struct kwgbe_rxdesc *)memalign(PKTALIGN,
KW_RXQ_DESC_ALIGNED_SIZE
* RINGSZ + 1)))
dmvgbe->p_rxdesc =
(struct mvgbe_rxdesc *)memalign(PKTALIGN,
MV_RXQ_DESC_ALIGNED_SIZE*RINGSZ + 1);
if (!dmvgbe->p_rxdesc)
goto error2;
if (!(dkwgbe->p_rxbuf = (u8 *) memalign(PKTALIGN, RINGSZ
* PKTSIZE_ALIGN + 1)))
dmvgbe->p_rxbuf = (u8 *) memalign(PKTALIGN,
RINGSZ*PKTSIZE_ALIGN + 1);
if (!dmvgbe->p_rxbuf)
goto error3;
if (!(dkwgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN)))
dmvgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN);
if (!dmvgbe->p_aligned_txbuf)
goto error4;
if (!(dkwgbe->p_txdesc = (struct kwgbe_txdesc *)
memalign(PKTALIGN, sizeof(struct kwgbe_txdesc) + 1))) {
free(dkwgbe->p_aligned_txbuf);
error4:
free(dkwgbe->p_rxbuf);
error3:
free(dkwgbe->p_rxdesc);
error2:
free(dkwgbe);
error1:
dmvgbe->p_txdesc = (struct mvgbe_txdesc *) memalign(
PKTALIGN, sizeof(struct mvgbe_txdesc) + 1);
if (!dmvgbe->p_txdesc) {
free(dmvgbe->p_aligned_txbuf);
error4:
free(dmvgbe->p_rxbuf);
error3:
free(dmvgbe->p_rxdesc);
error2:
free(dmvgbe);
error1:
printf("Err.. %s Failed to allocate memory\n",
__FUNCTION__);
return -1;
}
dev = &dkwgbe->dev;
dev = &dmvgbe->dev;
/* must be less than NAMESIZE (16) */
sprintf(dev->name, "egiga%d", devnum);
@ -676,13 +703,15 @@ int kirkwood_egiga_initialize(bd_t * bis)
/* Extract the MAC address from the environment */
switch (devnum) {
case 0:
dkwgbe->regs = (void *)KW_EGIGA0_BASE;
dmvgbe->regs = (void *)MVGBE0_BASE;
s = "ethaddr";
break;
#if defined(MVGBE1_BASE)
case 1:
dkwgbe->regs = (void *)KW_EGIGA1_BASE;
dmvgbe->regs = (void *)MVGBE1_BASE;
s = "eth1addr";
break;
#endif
default: /* this should never happen */
printf("Err..(%s) Invalid device number %d\n",
__FUNCTION__, devnum);
@ -690,29 +719,37 @@ int kirkwood_egiga_initialize(bd_t * bis)
}
while (!eth_getenv_enetaddr(s, dev->enetaddr)) {
/* Generate Random Private MAC addr if not set */
/* Generate Private MAC addr if not set */
dev->enetaddr[0] = 0x02;
dev->enetaddr[1] = 0x50;
dev->enetaddr[2] = 0x43;
#if defined (CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION)
/* Generate fixed lower MAC half using devnum */
dev->enetaddr[3] = 0;
dev->enetaddr[4] = 0;
dev->enetaddr[5] = devnum;
#else
/* Generate random lower MAC half */
dev->enetaddr[3] = get_random_hex();
dev->enetaddr[4] = get_random_hex();
dev->enetaddr[5] = get_random_hex();
#endif
eth_setenv_enetaddr(s, dev->enetaddr);
}
dev->init = (void *)kwgbe_init;
dev->halt = (void *)kwgbe_halt;
dev->send = (void *)kwgbe_send;
dev->recv = (void *)kwgbe_recv;
dev->write_hwaddr = (void *)kwgbe_write_hwaddr;
dev->init = (void *)mvgbe_init;
dev->halt = (void *)mvgbe_halt;
dev->send = (void *)mvgbe_send;
dev->recv = (void *)mvgbe_recv;
dev->write_hwaddr = (void *)mvgbe_write_hwaddr;
eth_register(dev);
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
miiphy_register(dev->name, smi_reg_read, smi_reg_write);
/* Set phy address of the port */
miiphy_write(dev->name, KIRKWOOD_PHY_ADR_REQUEST,
KIRKWOOD_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum);
miiphy_write(dev->name, MV_PHY_ADR_REQUEST,
MV_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum);
#endif
}
return 0;

505
drivers/net/mvgbe.h Normal file
View File

@ -0,0 +1,505 @@
/*
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
* based on - Driver for MV64360X ethernet ports
* Copyright (C) 2002 rabeeh@galileo.co.il
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef __MVGBE_H__
#define __MVGBE_H__
/* PHY_BASE_ADR is board specific and can be configured */
#if defined (CONFIG_PHY_BASE_ADR)
#define PHY_BASE_ADR CONFIG_PHY_BASE_ADR
#else
#define PHY_BASE_ADR 0x08 /* default phy base addr */
#endif
/* Constants */
#define INT_CAUSE_UNMASK_ALL 0x0007ffff
#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
#define MRU_MASK 0xfff1ffff
#define PHYADR_MASK 0x0000001f
#define PHYREG_MASK 0x0000001f
#define QTKNBKT_DEF_VAL 0x3fffffff
#define QMTBS_DEF_VAL 0x000003ff
#define QTKNRT_DEF_VAL 0x0000fcff
#define RXUQ 0 /* Used Rx queue */
#define TXUQ 0 /* Used Rx queue */
#define to_mvgbe(_d) container_of(_d, struct mvgbe_device, dev)
#define MVGBE_REG_WR(adr, val) writel(val, &adr)
#define MVGBE_REG_RD(adr) readl(&adr)
#define MVGBE_REG_BITS_RESET(adr, val) writel(readl(&adr) & ~(val), &adr)
#define MVGBE_REG_BITS_SET(adr, val) writel(readl(&adr) | val, &adr)
/* Default port configuration value */
#define PRT_CFG_VAL ( \
MVGBE_UCAST_MOD_NRML | \
MVGBE_DFLT_RXQ(RXUQ) | \
MVGBE_DFLT_RX_ARPQ(RXUQ) | \
MVGBE_RX_BC_IF_NOT_IP_OR_ARP | \
MVGBE_RX_BC_IF_IP | \
MVGBE_RX_BC_IF_ARP | \
MVGBE_CPTR_TCP_FRMS_DIS | \
MVGBE_CPTR_UDP_FRMS_DIS | \
MVGBE_DFLT_RX_TCPQ(RXUQ) | \
MVGBE_DFLT_RX_UDPQ(RXUQ) | \
MVGBE_DFLT_RX_BPDUQ(RXUQ))
/* Default port extend configuration value */
#define PORT_CFG_EXTEND_VALUE \
MVGBE_SPAN_BPDU_PACKETS_AS_NORMAL | \
MVGBE_PARTITION_DIS | \
MVGBE_TX_CRC_GENERATION_EN
#define GT_MVGBE_IPG_INT_RX(value) ((value & 0x3fff) << 8)
/* Default sdma control value */
#define PORT_SDMA_CFG_VALUE ( \
MVGBE_RX_BURST_SIZE_16_64BIT | \
MVGBE_BLM_RX_NO_SWAP | \
MVGBE_BLM_TX_NO_SWAP | \
GT_MVGBE_IPG_INT_RX(RXUQ) | \
MVGBE_TX_BURST_SIZE_16_64BIT)
/* Default port serial control value */
#define PORT_SERIAL_CONTROL_VALUE ( \
MVGBE_FORCE_LINK_PASS | \
MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \
MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
MVGBE_ADV_NO_FLOW_CTRL | \
MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
MVGBE_FORCE_BP_MODE_NO_JAM | \
(1 << 9) /* Reserved bit has to be 1 */ | \
MVGBE_DO_NOT_FORCE_LINK_FAIL | \
MVGBE_EN_AUTO_NEG_SPEED_GMII | \
MVGBE_DTE_ADV_0 | \
MVGBE_MIIPHY_MAC_MODE | \
MVGBE_AUTO_NEG_NO_CHANGE | \
MVGBE_MAX_RX_PACKET_1552BYTE | \
MVGBE_CLR_EXT_LOOPBACK | \
MVGBE_SET_FULL_DUPLEX_MODE | \
MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX)
/* Tx WRR confoguration macros */
#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */
#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_FFFF /* PMTBS reg (default) */
#define PORT_TOKEN_RATE 1023 /* PTTBRC reg (default) */
/* MAC accepet/reject macros */
#define ACCEPT_MAC_ADDR 0
#define REJECT_MAC_ADDR 1
/* Size of a Tx/Rx descriptor used in chain list data structure */
#define MV_RXQ_DESC_ALIGNED_SIZE \
(((sizeof(struct mvgbe_rxdesc) / PKTALIGN) + 1) * PKTALIGN)
/* Buffer offset from buffer pointer */
#define RX_BUF_OFFSET 0x2
/* Port serial status reg (PSR) */
#define MVGBE_INTERFACE_GMII_MII 0
#define MVGBE_INTERFACE_PCM 1
#define MVGBE_LINK_IS_DOWN 0
#define MVGBE_LINK_IS_UP (1 << 1)
#define MVGBE_PORT_AT_HALF_DUPLEX 0
#define MVGBE_PORT_AT_FULL_DUPLEX (1 << 2)
#define MVGBE_RX_FLOW_CTRL_DISD 0
#define MVGBE_RX_FLOW_CTRL_ENBALED (1 << 3)
#define MVGBE_GMII_SPEED_100_10 0
#define MVGBE_GMII_SPEED_1000 (1 << 4)
#define MVGBE_MII_SPEED_10 0
#define MVGBE_MII_SPEED_100 (1 << 5)
#define MVGBE_NO_TX 0
#define MVGBE_TX_IN_PROGRESS (1 << 7)
#define MVGBE_BYPASS_NO_ACTIVE 0
#define MVGBE_BYPASS_ACTIVE (1 << 8)
#define MVGBE_PORT_NOT_AT_PARTN_STT 0
#define MVGBE_PORT_AT_PARTN_STT (1 << 9)
#define MVGBE_PORT_TX_FIFO_NOT_EMPTY 0
#define MVGBE_PORT_TX_FIFO_EMPTY (1 << 10)
/* These macros describes the Port configuration reg (Px_cR) bits */
#define MVGBE_UCAST_MOD_NRML 0
#define MVGBE_UNICAST_PROMISCUOUS_MODE 1
#define MVGBE_DFLT_RXQ(_x) (_x << 1)
#define MVGBE_DFLT_RX_ARPQ(_x) (_x << 4)
#define MVGBE_RX_BC_IF_NOT_IP_OR_ARP 0
#define MVGBE_REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7)
#define MVGBE_RX_BC_IF_IP 0
#define MVGBE_REJECT_BC_IF_IP (1 << 8)
#define MVGBE_RX_BC_IF_ARP 0
#define MVGBE_REJECT_BC_IF_ARP (1 << 9)
#define MVGBE_TX_AM_NO_UPDATE_ERR_SMRY (1 << 12)
#define MVGBE_CPTR_TCP_FRMS_DIS 0
#define MVGBE_CPTR_TCP_FRMS_EN (1 << 14)
#define MVGBE_CPTR_UDP_FRMS_DIS 0
#define MVGBE_CPTR_UDP_FRMS_EN (1 << 15)
#define MVGBE_DFLT_RX_TCPQ(_x) (_x << 16)
#define MVGBE_DFLT_RX_UDPQ(_x) (_x << 19)
#define MVGBE_DFLT_RX_BPDUQ(_x) (_x << 22)
#define MVGBE_DFLT_RX_TCP_CHKSUM_MODE (1 << 25)
/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
#define MVGBE_CLASSIFY_EN 1
#define MVGBE_SPAN_BPDU_PACKETS_AS_NORMAL 0
#define MVGBE_SPAN_BPDU_PACKETS_TO_RX_Q7 (1 << 1)
#define MVGBE_PARTITION_DIS 0
#define MVGBE_PARTITION_EN (1 << 2)
#define MVGBE_TX_CRC_GENERATION_EN 0
#define MVGBE_TX_CRC_GENERATION_DIS (1 << 3)
/* These macros describes the Port Sdma configuration reg (SDCR) bits */
#define MVGBE_RIFB 1
#define MVGBE_RX_BURST_SIZE_1_64BIT 0
#define MVGBE_RX_BURST_SIZE_2_64BIT (1 << 1)
#define MVGBE_RX_BURST_SIZE_4_64BIT (1 << 2)
#define MVGBE_RX_BURST_SIZE_8_64BIT ((1 << 2) | (1 << 1))
#define MVGBE_RX_BURST_SIZE_16_64BIT (1 << 3)
#define MVGBE_BLM_RX_NO_SWAP (1 << 4)
#define MVGBE_BLM_RX_BYTE_SWAP 0
#define MVGBE_BLM_TX_NO_SWAP (1 << 5)
#define MVGBE_BLM_TX_BYTE_SWAP 0
#define MVGBE_DESCRIPTORS_BYTE_SWAP (1 << 6)
#define MVGBE_DESCRIPTORS_NO_SWAP 0
#define MVGBE_TX_BURST_SIZE_1_64BIT 0
#define MVGBE_TX_BURST_SIZE_2_64BIT (1 << 22)
#define MVGBE_TX_BURST_SIZE_4_64BIT (1 << 23)
#define MVGBE_TX_BURST_SIZE_8_64BIT ((1 << 23) | (1 << 22))
#define MVGBE_TX_BURST_SIZE_16_64BIT (1 << 24)
/* These macros describes the Port serial control reg (PSCR) bits */
#define MVGBE_SERIAL_PORT_DIS 0
#define MVGBE_SERIAL_PORT_EN 1
#define MVGBE_FORCE_LINK_PASS (1 << 1)
#define MVGBE_DO_NOT_FORCE_LINK_PASS 0
#define MVGBE_EN_AUTO_NEG_FOR_DUPLX 0
#define MVGBE_DIS_AUTO_NEG_FOR_DUPLX (1 << 2)
#define MVGBE_EN_AUTO_NEG_FOR_FLOW_CTRL 0
#define MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
#define MVGBE_ADV_NO_FLOW_CTRL 0
#define MVGBE_ADV_SYMMETRIC_FLOW_CTRL (1 << 4)
#define MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
#define MVGBE_FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5)
#define MVGBE_FORCE_BP_MODE_NO_JAM 0
#define MVGBE_FORCE_BP_MODE_JAM_TX (1 << 7)
#define MVGBE_FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1 << 8)
#define MVGBE_FORCE_LINK_FAIL 0
#define MVGBE_DO_NOT_FORCE_LINK_FAIL (1 << 10)
#define MVGBE_DIS_AUTO_NEG_SPEED_GMII (1 << 13)
#define MVGBE_EN_AUTO_NEG_SPEED_GMII 0
#define MVGBE_DTE_ADV_0 0
#define MVGBE_DTE_ADV_1 (1 << 14)
#define MVGBE_MIIPHY_MAC_MODE 0
#define MVGBE_MIIPHY_PHY_MODE (1 << 15)
#define MVGBE_AUTO_NEG_NO_CHANGE 0
#define MVGBE_RESTART_AUTO_NEG (1 << 16)
#define MVGBE_MAX_RX_PACKET_1518BYTE 0
#define MVGBE_MAX_RX_PACKET_1522BYTE (1 << 17)
#define MVGBE_MAX_RX_PACKET_1552BYTE (1 << 18)
#define MVGBE_MAX_RX_PACKET_9022BYTE ((1 << 18) | (1 << 17))
#define MVGBE_MAX_RX_PACKET_9192BYTE (1 << 19)
#define MVGBE_MAX_RX_PACKET_9700BYTE ((1 << 19) | (1 << 17))
#define MVGBE_SET_EXT_LOOPBACK (1 << 20)
#define MVGBE_CLR_EXT_LOOPBACK 0
#define MVGBE_SET_FULL_DUPLEX_MODE (1 << 21)
#define MVGBE_SET_HALF_DUPLEX_MODE 0
#define MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22)
#define MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
#define MVGBE_SET_GMII_SPEED_TO_10_100 0
#define MVGBE_SET_GMII_SPEED_TO_1000 (1 << 23)
#define MVGBE_SET_MII_SPEED_TO_10 0
#define MVGBE_SET_MII_SPEED_TO_100 (1 << 24)
/* SMI register fields */
#define MVGBE_PHY_SMI_TIMEOUT 10000
#define MVGBE_PHY_SMI_DATA_OFFS 0 /* Data */
#define MVGBE_PHY_SMI_DATA_MASK (0xffff << MVGBE_PHY_SMI_DATA_OFFS)
#define MVGBE_PHY_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
#define MVGBE_PHY_SMI_DEV_ADDR_MASK \
(PHYADR_MASK << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
#define MVGBE_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr */
#define MVGBE_SMI_REG_ADDR_MASK \
(PHYADR_MASK << MVGBE_SMI_REG_ADDR_OFFS)
#define MVGBE_PHY_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
#define MVGBE_PHY_SMI_OPCODE_MASK (3 << MVGBE_PHY_SMI_OPCODE_OFFS)
#define MVGBE_PHY_SMI_OPCODE_WRITE (0 << MVGBE_PHY_SMI_OPCODE_OFFS)
#define MVGBE_PHY_SMI_OPCODE_READ (1 << MVGBE_PHY_SMI_OPCODE_OFFS)
#define MVGBE_PHY_SMI_READ_VALID_MASK (1 << 27) /* Read Valid */
#define MVGBE_PHY_SMI_BUSY_MASK (1 << 28) /* Busy */
/* SDMA command status fields macros */
/* Tx & Rx descriptors status */
#define MVGBE_ERROR_SUMMARY 1
/* Tx & Rx descriptors command */
#define MVGBE_BUFFER_OWNED_BY_DMA (1 << 31)
/* Tx descriptors status */
#define MVGBE_LC_ERROR 0
#define MVGBE_UR_ERROR (1 << 1)
#define MVGBE_RL_ERROR (1 << 2)
#define MVGBE_LLC_SNAP_FORMAT (1 << 9)
#define MVGBE_TX_LAST_FRAME (1 << 20)
/* Rx descriptors status */
#define MVGBE_CRC_ERROR 0
#define MVGBE_OVERRUN_ERROR (1 << 1)
#define MVGBE_MAX_FRAME_LENGTH_ERROR (1 << 2)
#define MVGBE_RESOURCE_ERROR ((1 << 2) | (1 << 1))
#define MVGBE_VLAN_TAGGED (1 << 19)
#define MVGBE_BPDU_FRAME (1 << 20)
#define MVGBE_TCP_FRAME_OVER_IP_V_4 0
#define MVGBE_UDP_FRAME_OVER_IP_V_4 (1 << 21)
#define MVGBE_OTHER_FRAME_TYPE (1 << 22)
#define MVGBE_LAYER_2_IS_MVGBE_V_2 (1 << 23)
#define MVGBE_FRAME_TYPE_IP_V_4 (1 << 24)
#define MVGBE_FRAME_HEADER_OK (1 << 25)
#define MVGBE_RX_LAST_DESC (1 << 26)
#define MVGBE_RX_FIRST_DESC (1 << 27)
#define MVGBE_UNKNOWN_DESTINATION_ADDR (1 << 28)
#define MVGBE_RX_EN_INTERRUPT (1 << 29)
#define MVGBE_LAYER_4_CHECKSUM_OK (1 << 30)
/* Rx descriptors byte count */
#define MVGBE_FRAME_FRAGMENTED (1 << 2)
/* Tx descriptors command */
#define MVGBE_LAYER_4_CHECKSUM_FIRST_DESC (1 << 10)
#define MVGBE_FRAME_SET_TO_VLAN (1 << 15)
#define MVGBE_TCP_FRAME 0
#define MVGBE_UDP_FRAME (1 << 16)
#define MVGBE_GEN_TCP_UDP_CHECKSUM (1 << 17)
#define MVGBE_GEN_IP_V_4_CHECKSUM (1 << 18)
#define MVGBE_ZERO_PADDING (1 << 19)
#define MVGBE_TX_LAST_DESC (1 << 20)
#define MVGBE_TX_FIRST_DESC (1 << 21)
#define MVGBE_GEN_CRC (1 << 22)
#define MVGBE_TX_EN_INTERRUPT (1 << 23)
#define MVGBE_AUTO_MODE (1 << 30)
/* Address decode parameters */
/* Ethernet Base Address Register bits */
#define EBAR_TARGET_DRAM 0x00000000
#define EBAR_TARGET_DEVICE 0x00000001
#define EBAR_TARGET_CBS 0x00000002
#define EBAR_TARGET_PCI0 0x00000003
#define EBAR_TARGET_PCI1 0x00000004
#define EBAR_TARGET_CUNIT 0x00000005
#define EBAR_TARGET_AUNIT 0x00000006
#define EBAR_TARGET_GUNIT 0x00000007
/* Window attrib */
#define EBAR_DRAM_CS0 0x00000E00
#define EBAR_DRAM_CS1 0x00000D00
#define EBAR_DRAM_CS2 0x00000B00
#define EBAR_DRAM_CS3 0x00000700
/* DRAM Target interface */
#define EBAR_DRAM_NO_CACHE_COHERENCY 0x00000000
#define EBAR_DRAM_CACHE_COHERENCY_WT 0x00001000
#define EBAR_DRAM_CACHE_COHERENCY_WB 0x00002000
/* Device Bus Target interface */
#define EBAR_DEVICE_DEVCS0 0x00001E00
#define EBAR_DEVICE_DEVCS1 0x00001D00
#define EBAR_DEVICE_DEVCS2 0x00001B00
#define EBAR_DEVICE_DEVCS3 0x00001700
#define EBAR_DEVICE_BOOTCS3 0x00000F00
/* PCI Target interface */
#define EBAR_PCI_BYTE_SWAP 0x00000000
#define EBAR_PCI_NO_SWAP 0x00000100
#define EBAR_PCI_BYTE_WORD_SWAP 0x00000200
#define EBAR_PCI_WORD_SWAP 0x00000300
#define EBAR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000
#define EBAR_PCI_NO_SNOOP_ASSERT 0x00000400
#define EBAR_PCI_IO_SPACE 0x00000000
#define EBAR_PCI_MEMORY_SPACE 0x00000800
#define EBAR_PCI_REQ64_FORCE 0x00000000
#define EBAR_PCI_REQ64_SIZE 0x00001000
/* Window access control */
#define EWIN_ACCESS_NOT_ALLOWED 0
#define EWIN_ACCESS_READ_ONLY 1
#define EWIN_ACCESS_FULL ((1 << 1) | 1)
/* structures represents Controller registers */
struct mvgbe_barsz {
u32 bar;
u32 size;
};
struct mvgbe_rxcdp {
struct mvgbe_rxdesc *rxcdp;
u32 rxcdp_pad[3];
};
struct mvgbe_tqx {
u32 qxttbc;
u32 tqxtbc;
u32 tqxac;
u32 tqxpad;
};
struct mvgbe_registers {
u32 phyadr;
u32 smi;
u32 euda;
u32 eudid;
u8 pad1[0x080 - 0x00c - 4];
u32 euic;
u32 euim;
u8 pad2[0x094 - 0x084 - 4];
u32 euea;
u32 euiae;
u8 pad3[0x0b0 - 0x098 - 4];
u32 euc;
u8 pad3a[0x200 - 0x0b0 - 4];
struct mvgbe_barsz barsz[6];
u8 pad4[0x280 - 0x22c - 4];
u32 ha_remap[4];
u32 bare;
u32 epap;
u8 pad5[0x400 - 0x294 - 4];
u32 pxc;
u32 pxcx;
u32 mii_ser_params;
u8 pad6[0x410 - 0x408 - 4];
u32 evlane;
u32 macal;
u32 macah;
u32 sdc;
u32 dscp[7];
u32 psc0;
u32 vpt2p;
u32 ps0;
u32 tqc;
u32 psc1;
u32 ps1;
u32 mrvl_header;
u8 pad7[0x460 - 0x454 - 4];
u32 ic;
u32 ice;
u32 pim;
u32 peim;
u8 pad8[0x474 - 0x46c - 4];
u32 pxtfut;
u32 pad9;
u32 pxmfs;
u32 pad10;
u32 pxdfc;
u32 pxofc;
u8 pad11[0x494 - 0x488 - 4];
u32 peuiae;
u8 pad12[0x4bc - 0x494 - 4];
u32 eth_type_prio;
u8 pad13[0x4dc - 0x4bc - 4];
u32 tqfpc;
u32 pttbrc;
u32 tqc1;
u32 pmtu;
u32 pmtbs;
u8 pad14[0x60c - 0x4ec - 4];
struct mvgbe_rxcdp rxcdp[7];
struct mvgbe_rxdesc *rxcdp7;
u32 rqc;
struct mvgbe_txdesc *tcsdp;
u8 pad15[0x6c0 - 0x684 - 4];
struct mvgbe_txdesc *tcqdp[8];
u8 pad16[0x700 - 0x6dc - 4];
struct mvgbe_tqx tqx[8];
u32 pttbc;
u8 pad17[0x7a8 - 0x780 - 4];
u32 tqxipg0;
u32 pad18[3];
u32 tqxipg1;
u8 pad19[0x7c0 - 0x7b8 - 4];
u32 hitkninlopkt;
u32 hitkninasyncpkt;
u32 lotkninasyncpkt;
u32 pad20;
u32 ts;
u8 pad21[0x3000 - 0x27d0 - 4];
u32 pad20_1[32]; /* mib counter registes */
u8 pad22[0x3400 - 0x3000 - sizeof(u32) * 32];
u32 dfsmt[64];
u32 dfomt[64];
u32 dfut[4];
u8 pad23[0xe20c0 - 0x7360c - 4];
u32 pmbus_top_arbiter;
};
/* structures/enums needed by driver */
enum mvgbe_adrwin {
MVGBE_WIN0,
MVGBE_WIN1,
MVGBE_WIN2,
MVGBE_WIN3,
MVGBE_WIN4,
MVGBE_WIN5
};
enum mvgbe_target {
MVGBE_TARGET_DRAM,
MVGBE_TARGET_DEV,
MVGBE_TARGET_CBS,
MVGBE_TARGET_PCI0,
MVGBE_TARGET_PCI1
};
struct mvgbe_winparam {
enum mvgbe_adrwin win; /* Window number */
enum mvgbe_target target; /* System targets */
u16 attrib; /* BAR attrib. See above macros */
u32 base_addr; /* Window base address in u32 form */
u32 high_addr; /* Window high address in u32 form */
u32 size; /* Size in MBytes. Must be % 64Kbyte. */
int enable; /* Enable/disable access to the window. */
u16 access_ctrl; /*Access ctrl register. see above macros */
};
struct mvgbe_rxdesc {
u32 cmd_sts; /* Descriptor command status */
u16 buf_size; /* Buffer size */
u16 byte_cnt; /* Descriptor buffer byte count */
u8 *buf_ptr; /* Descriptor buffer pointer */
struct mvgbe_rxdesc *nxtdesc_p; /* Next descriptor pointer */
};
struct mvgbe_txdesc {
u32 cmd_sts; /* Descriptor command status */
u16 l4i_chk; /* CPU provided TCP Checksum */
u16 byte_cnt; /* Descriptor buffer byte count */
u8 *buf_ptr; /* Descriptor buffer ptr */
struct mvgbe_txdesc *nxtdesc_p; /* Next descriptor ptr */
};
/* port device data struct */
struct mvgbe_device {
struct eth_device dev;
struct mvgbe_registers *regs;
struct mvgbe_txdesc *p_txdesc;
struct mvgbe_rxdesc *p_rxdesc;
struct mvgbe_rxdesc *p_rxdesc_curr;
u8 *p_rxbuf;
u8 *p_aligned_txbuf;
};
#endif /* __MVGBE_H__ */

37
drivers/net/tsec.c
View File

@ -95,14 +95,23 @@ static struct tsec_info_struct tsec_info[] = {
#endif
};
/*
* Initialize all the TSEC devices
*
* Returns the number of TSEC devices that were initialized
*/
int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
{
int i;
int ret, count = 0;
for (i = 0; i < num; i++)
tsec_initialize(bis, &tsecs[i]);
for (i = 0; i < num; i++) {
ret = tsec_initialize(bis, &tsecs[i]);
if (ret > 0)
count += ret;
}
return 0;
return count;
}
int tsec_standard_init(bd_t *bis)
@ -1631,6 +1640,27 @@ static struct phy_info phy_info_dm9161 = {
},
};
/* micrel KSZ804 */
static struct phy_info phy_info_ksz804 = {
0x0022151,
"Micrel KSZ804 PHY",
4,
(struct phy_cmd[]) { /* config */
{PHY_BMCR, PHY_BMCR_RESET, NULL},
{PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL},
{miim_end,}
},
(struct phy_cmd[]) { /* startup */
{PHY_BMSR, miim_read, NULL},
{PHY_BMSR, miim_read, &mii_parse_sr},
{PHY_BMSR, miim_read, &mii_parse_link},
{miim_end,}
},
(struct phy_cmd[]) { /* shutdown */
{miim_end,}
}
};
/* a generic flavor. */
static struct phy_info phy_info_generic = {
0,
@ -1794,6 +1824,7 @@ static struct phy_info *phy_info[] = {
&phy_info_M88E1145,
&phy_info_M88E1149S,
&phy_info_dm9161,
&phy_info_ksz804,
&phy_info_lxt971,
&phy_info_VSC8211,
&phy_info_VSC8244,

2
drivers/net/uli526x.c
View File

@ -225,7 +225,7 @@ int uli526x_initialize(bd_t *bis)
iobase &= ~0xf;
dev = (struct eth_device *)malloc(sizeof *dev);
sprintf(dev->name, "uli526x#%d\n", card_number);
sprintf(dev->name, "uli526x#%d", card_number);
db = (struct uli526x_board_info *)
malloc(sizeof(struct uli526x_board_info));

2
examples/standalone/smc911x_eeprom.c
View File

@ -240,7 +240,7 @@ static void dump_eeprom(struct eth_device *dev)
static int smc911x_init(struct eth_device *dev)
{
/* See if there is anything there */
if (!smc911x_detect_chip(dev))
if (smc911x_detect_chip(dev))
return 1;
smc911x_reset(dev);

9
include/configs/cpuat91.h
View File

@ -131,15 +131,12 @@
(CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 512 * 1024)
#define CONFIG_NET_MULTI 1
#ifdef CONFIG_NET_MULTI
#define CONFIG_DRIVER_AT91EMAC 1
#define CONFIG_SYS_RX_ETH_BUFFER 8
#else
#define CONFIG_DRIVER_ETHER 1
#endif
#define CONFIG_RMII 1
#define CONFIG_MII 1
#define CONFIG_DRIVER_AT91EMAC_PHYADDR 1
#define CONFIG_NET_RETRY_COUNT 20
#define CONFIG_AT91C_USE_RMII 1
#define CONFIG_PHY_ADDRESS (1 << 5)
#define CONFIG_KS8721_PHY 1
#define CONFIG_SYS_FLASH_CFI 1

19
include/configs/edminiv2.h
View File

@ -131,12 +131,23 @@
* Commands configuration - using default command set for now
*/
#include <config_cmd_default.h>
/*
* Disabling some default commands for staggered bring-up
* Network
*/
#undef CONFIG_CMD_BOOTD /* no bootd since no net */
#undef CONFIG_CMD_NET /* no net since no eth */
#undef CONFIG_CMD_NFS /* no NFS since no net */
#ifdef CONFIG_CMD_NET
#define CONFIG_MVGBE /* Enable Marvell GbE Driver */
#define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */
#define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */
#define CONFIG_PHY_BASE_ADR 0x8
#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_NET_MULTI /* specify more that one ports available */
#define CONFIG_MII /* expose smi ove miiphy interface */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#endif
/*
* Environment variables configurations

4
include/configs/guruplug.h
View File

@ -172,9 +172,9 @@
#define CONFIG_NET_MULTI /* specify more that one ports available */
#define CONFIG_MII /* expose smi ove miiphy interface */
#define CONFIG_CMD_MII
#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,1} /* enable both ports */
#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */
#define CONFIG_PHY_BASE_ADR 0
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv88e1121 PHY */

4
include/configs/km_arm.h
View File

@ -127,9 +127,9 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_NET_MULTI /* specify more that one ports available */
#define CONFIG_MII /* expose smi ove miiphy interface */
#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable port 0 only */
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
#define CONFIG_PHY_BASE_ADR 0
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#define CONFIG_RESET_PHY_R /* use reset_phy() to init 88E1118 PHY */

4
include/configs/mv88f6281gtw_ge.h
View File

@ -172,9 +172,9 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_NET_MULTI /* specify more that one ports available */
#define CONFIG_MII /* expose smi ove miiphy interface */
#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable port 0 only */
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#endif /* CONFIG_CMD_NET */

4
include/configs/openrd_base.h
View File

@ -183,9 +183,9 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_NET_MULTI /* specify more that one ports available */
#define CONFIG_MII /* expose smi ove miiphy interface */
#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable port 0 only */
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
#define CONFIG_PHY_BASE_ADR 0x8
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */

4
include/configs/rd6281a.h
View File

@ -171,8 +171,8 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_NET_MULTI /* specify more that one ports available */
#define CONFIG_MII /* expose smi ove miiphy interface */
#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,1} /* enable both ports */
#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */
#define CONFIG_MV88E61XX_MULTICHIP_ADRMODE
#define CONFIG_DIS_AUTO_NEG_SPEED_GMII /*Disable Auto speed negociation */
#define CONFIG_PHY_SPEED _1000BASET /*Force PHYspeed to 1GBPs */

4
include/configs/sheevaplug.h
View File

@ -174,9 +174,9 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_NET_MULTI /* specify more that one ports available */
#define CONFIG_MII /* expose smi ove miiphy interface */
#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable port 0 only */
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
#define CONFIG_PHY_BASE_ADR 0
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */

4
include/netdev.h
View File

@ -43,12 +43,14 @@ int cpu_eth_init(bd_t *bis);
/* Driver initialization prototypes */
int altera_tse_initialize(u8 dev_num, int mac_base,
int sgdma_rx_base, int sgdma_tx_base);
int ax88180_initialize(bd_t *bis);
int au1x00_enet_initialize(bd_t*);
int at91emac_register(bd_t *bis, unsigned long iobase);
int bfin_EMAC_initialize(bd_t *bis);
int cs8900_initialize(u8 dev_num, int base_addr);
int dc21x4x_initialize(bd_t *bis);
int davinci_emac_initialize(void);
int designware_initialize(u32 id, ulong base_addr, u32 phy_addr);
int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr);
int e1000_initialize(bd_t *bis);
int eepro100_initialize(bd_t *bis);
@ -61,7 +63,6 @@ int ftmac100_initialize(bd_t *bits);
int greth_initialize(bd_t *bis);
void gt6426x_eth_initialize(bd_t *bis);
int inca_switch_initialize(bd_t *bis);
int kirkwood_egiga_initialize(bd_t *bis);
int lan91c96_initialize(u8 dev_num, int base_addr);
int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
int mcdmafec_initialize(bd_t *bis);
@ -70,6 +71,7 @@ int mpc512x_fec_initialize(bd_t *bis);
int mpc5xxx_fec_initialize(bd_t *bis);
int mpc8220_fec_initialize(bd_t *bis);
int mpc82xx_scc_enet_initialize(bd_t *bis);
int mvgbe_initialize(bd_t *bis);
int natsemi_initialize(bd_t *bis);
int npe_initialize(bd_t *bis);
int ns8382x_initialize(bd_t *bis);

3
net/eth.c
View File

@ -234,6 +234,9 @@ int eth_initialize(bd_t *bis)
puts (" [PRIME]");
}
if (strchr(dev->name, ' '))
puts("\nWarning: eth device name has a space!\n");
eth_getenv_enetaddr_by_index(eth_number, env_enetaddr);
if (memcmp(env_enetaddr, "\0\0\0\0\0\0", 6)) {