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ColdFire: MCF5329 Update and cleanup 

Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
This commit is contained in:
TsiChungLiew 2007-08-15 15:39:17 -05:00 committed by John Rigby
parent 81735b2568
commit ab77bc547b
12 changed files with 99 additions and 89 deletions
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2
Makefile
View File

@ -1682,7 +1682,7 @@ M5329BFEE_config : unconfig
esac; \ esac; \
>include/config.h ; \ >include/config.h ; \
if [ "$${NAND}" != "0" ] ; then \ if [ "$${NAND}" != "0" ] ; then \
echo "#define NANDFLASH_SIZE $${NAND}" >> include/config.h ; \ echo "#define NANDFLASH_SIZE $${NAND}" > $(obj)include/config.h ; \
fi fi
@$(MKCONFIG) -a M5329EVB m68k mcf532x m5329evb freescale @$(MKCONFIG) -a M5329EVB m68k mcf532x m5329evb freescale

8
board/freescale/m5329evb/mii.c
View File

@ -30,7 +30,7 @@
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) #if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
#undef MII_DEBUG #undef MII_DEBUG
#undef ET_DEBUG #undef ET_DEBUG
@ -50,7 +50,7 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
return 0; return 0;
} }
#if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII) #if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
#include <miiphy.h> #include <miiphy.h>
/* Make MII read/write commands for the FEC. */ /* Make MII read/write commands for the FEC. */
@ -134,7 +134,7 @@ uint mii_send(uint mii_cmd)
return (mii_reply & 0xffff); /* data read from phy */ return (mii_reply & 0xffff); /* data read from phy */
} }
#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */ #endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
#if defined(CFG_DISCOVER_PHY) #if defined(CFG_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev) int mii_discover_phy(struct eth_device *dev)
@ -303,4 +303,4 @@ int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
return 0; return 0;
} }
#endif /* CFG_CMD_NET, FEC_ENET & NET_MULTI */ #endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */

2
board/freescale/m5329evb/nand.c
View File

@ -31,7 +31,7 @@
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
#if (CONFIG_COMMANDS & CFG_CMD_NAND) #if defined(CONFIG_CMD_NAND)
#include <nand.h> #include <nand.h>
#include <linux/mtd/mtd.h> #include <linux/mtd/mtd.h>

4
common/cmd_bdinfo.c
View File

@ -225,7 +225,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
#if defined(CFG_MBAR) #if defined(CFG_MBAR)
print_num ("mbar", bd->bi_mbar_base ); print_num ("mbar", bd->bi_mbar_base );
#endif #endif
#if defined(CFG_CMD_NET) #if defined(CONFIG_CMD_NET)
puts ("ethaddr ="); puts ("ethaddr =");
for (i=0; i<6; ++i) { for (i=0; i<6; ++i) {
printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]); printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
@ -254,7 +254,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
puts ("\nip_addr = "); puts ("\nip_addr = ");
print_IPaddr (bd->bi_ip_addr); print_IPaddr (bd->bi_ip_addr);
#endif /* CFG_CMD_NET */ #endif /* CONFIG_CMD_NET */
printf ("\nbaudrate = %d bps\n", bd->bi_baudrate); printf ("\nbaudrate = %d bps\n", bd->bi_baudrate);
return 0; return 0;

10
drivers/net/mcffec.c
View File

@ -51,7 +51,7 @@
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) #if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
struct fec_info_s fec_info[] = { struct fec_info_s fec_info[] = {
#ifdef CFG_FEC0_IOBASE #ifdef CFG_FEC0_IOBASE
@ -410,7 +410,7 @@ int fec_init(struct eth_device *dev, bd_t * bd)
fec_reset(dev); fec_reset(dev);
#if (CONFIG_COMMANDS & CFG_CMD_MII) || defined (CONFIG_MII) || \ #if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
defined (CFG_DISCOVER_PHY) defined (CFG_DISCOVER_PHY)
mii_init(); mii_init();
@ -420,7 +420,7 @@ int fec_init(struct eth_device *dev, bd_t * bd)
#ifndef CFG_DISCOVER_PHY #ifndef CFG_DISCOVER_PHY
setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) | FECSPEED); setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) | FECSPEED);
#endif /* ifndef CFG_DISCOVER_PHY */ #endif /* ifndef CFG_DISCOVER_PHY */
#endif /* CFG_CMD_MII || CONFIG_MII */ #endif /* CONFIG_CMD_MII || CONFIG_MII */
/* We use strictly polling mode only */ /* We use strictly polling mode only */
fecp->eimr = 0; fecp->eimr = 0;
@ -568,7 +568,7 @@ int mcffec_initialize(bd_t * bis)
eth_register(dev); eth_register(dev);
#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
miiphy_register(dev->name, miiphy_register(dev->name,
mcffec_miiphy_read, mcffec_miiphy_write); mcffec_miiphy_read, mcffec_miiphy_write);
#endif #endif
@ -580,5 +580,5 @@ int mcffec_initialize(bd_t * bis)
return 1; return 1;
} }
#endif /* CFG_CMD_NET, FEC_ENET & NET_MULTI */ #endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
#endif /* CONFIG_MCFFEC */ #endif /* CONFIG_MCFFEC */

2
include/asm-m68k/immap.h
View File

@ -38,8 +38,10 @@
#ifdef CONFIG_MCFTMR #ifdef CONFIG_MCFTMR
#define CFG_UDELAY_BASE (MMAP_DTMR0) #define CFG_UDELAY_BASE (MMAP_DTMR0)
#define CFG_TMR_BASE (MMAP_DTMR1) #define CFG_TMR_BASE (MMAP_DTMR1)
#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
#define CFG_TMRINTR_NO (INT0_HI_DTMR1) #define CFG_TMRINTR_NO (INT0_HI_DTMR1)
#define CFG_TMRINTR_MASK (INTC_IPRH_INT33) #define CFG_TMRINTR_MASK (INTC_IPRH_INT33)
#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
#define CFG_TMRINTR_PRI (6) #define CFG_TMRINTR_PRI (6)
#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) #define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif #endif

14
include/asm-m68k/timer.h
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@ -33,12 +33,26 @@
/****************************************************************************/ /****************************************************************************/
/* DMA Timer module registers */ /* DMA Timer module registers */
typedef struct dtimer_ctrl { typedef struct dtimer_ctrl {
#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
u16 tmr; /* 0x00 Mode register */
u16 res1; /* 0x02 */
u16 trr; /* 0x04 Reference register */
u16 res2; /* 0x06 */
u16 tcr; /* 0x08 Capture register */
u16 res3; /* 0x0A */
u16 tcn; /* 0x0C Counter register */
u16 res4; /* 0x0E */
u8 res6; /* 0x10 */
u8 ter; /* 0x11 Event register */
u16 res7; /* 0x12 */
#else
u16 tmr; /* 0x00 Mode register */ u16 tmr; /* 0x00 Mode register */
u8 txmr; /* 0x02 Extended Mode register */ u8 txmr; /* 0x02 Extended Mode register */
u8 ter; /* 0x03 Event register */ u8 ter; /* 0x03 Event register */
u32 trr; /* 0x04 Reference register */ u32 trr; /* 0x04 Reference register */
u32 tcr; /* 0x08 Capture register */ u32 tcr; /* 0x08 Capture register */
u32 tcn; /* 0x0C Counter register */ u32 tcn; /* 0x0C Counter register */
#endif
} dtmr_t; } dtmr_t;
/*Programmable Interrupt Timer */ /*Programmable Interrupt Timer */

47
include/configs/M5329EVB.h
View File

@ -47,25 +47,23 @@
#undef CONFIG_WATCHDOG #undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
#define DEFAULT_COMMANDS ( CONFIG_CMD_DFL | \ /* Command line configuration */
CFG_CMD_CACHE | \ #include <config_cmd_default.h>
CFG_CMD_DATE | \
CFG_CMD_ELF | \ #define CONFIG_CMD_CACHE
CFG_CMD_FLASH | \ #define CONFIG_CMD_DATE
CFG_CMD_I2C | \ #define CONFIG_CMD_ELF
(CFG_CMD_LOADB | CFG_CMD_LOADS) | \ #define CONFIG_CMD_FLASH
CFG_CMD_MEMORY | \ #define CONFIG_CMD_I2C
CFG_CMD_MISC | \ #define CONFIG_CMD_MEMORY
CFG_CMD_MII | \ #define CONFIG_CMD_MISC
CFG_CMD_NET | \ #define CONFIG_CMD_MII
CFG_CMD_PING | \ #define CONFIG_CMD_NET
CFG_CMD_REGINFO \ #define CONFIG_CMD_PING
) #define CONFIG_CMD_REGINFO
#ifdef NANDFLASH_SIZE #ifdef NANDFLASH_SIZE
# define CONFIG_COMMANDS (DEFAULT_COMMANDS | CFG_CMD_NAND) # define CONFIG_CMD_NAND
#else
# define CONFIG_COMMANDS (DEFAULT_COMMANDS)
#endif #endif
#define CFG_UNIFY_CACHE #define CFG_UNIFY_CACHE
@ -108,9 +106,9 @@
#define CFG_I2C_OFFSET 0x58000 #define CFG_I2C_OFFSET 0x58000
#define CFG_IMMR CFG_MBAR #define CFG_IMMR CFG_MBAR
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
#define CONFIG_UDP_CHECKSUM
#ifdef CONFIG_MCFFEC #ifdef CONFIG_MCFFEC
# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
# define CONFIG_IPADDR 192.162.1.2 # define CONFIG_IPADDR 192.162.1.2
@ -137,7 +135,7 @@
#define CFG_PROMPT "-> " #define CFG_PROMPT "-> "
#define CFG_LONGHELP /* undef to save memory */ #define CFG_LONGHELP /* undef to save memory */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #ifdef CONFIG_CMD_KGDB
# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else #else
# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ # define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@ -168,7 +166,7 @@
#define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ #define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
#define CFG_INIT_RAM_CTRL 0x221 #define CFG_INIT_RAM_CTRL 0x221
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 0x10)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
@ -198,7 +196,7 @@
* have to be in the first 8 MB of memory, since this is * have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ?? * the maximum mapped by the Linux kernel during initialization ??
*/ */
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ #define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* FLASH organization * FLASH organization
@ -226,8 +224,7 @@
# define CONFIG_JFFS2_PART_OFFSET 0x00000000 # define CONFIG_JFFS2_PART_OFFSET 0x00000000
#endif #endif
#define CFG_FLASH_BASE 0 #define CFG_FLASH_BASE (CFG_CS0_BASE << 16)
#define CFG_FLASH0_BASE (CFG_CS0_BASE << 16)
/* Configuration for environment /* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash * Environment is embedded in u-boot in the second sector of the flash
@ -267,6 +264,4 @@
#define CFG_CS2_CTRL 0x00001f60 #define CFG_CS2_CTRL 0x00001f60
#endif #endif
#define CONFIG_UDP_CHECKSUM
#endif /* _M5329EVB_H */ #endif /* _M5329EVB_H */

3
lib_m68k/time.c
View File

@ -347,10 +347,9 @@ void udelay(unsigned long usec)
void dtimer_interrupt(void *not_used) void dtimer_interrupt(void *not_used)
{ {
volatile dtmr_t *timerp = (dtmr_t *) (CFG_TMR_BASE); volatile dtmr_t *timerp = (dtmr_t *) (CFG_TMR_BASE);
volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
/* check for timer interrupt asserted */ /* check for timer interrupt asserted */
if ((intp->iprh0 & CFG_TMRINTR_MASK) == CFG_TMRINTR_MASK) { if ((CFG_TMRPND_REG & CFG_TMRINTR_MASK) == CFG_TMRINTR_PEND) {
timerp->ter = (DTIM_DTER_CAP | DTIM_DTER_REF); timerp->ter = (DTIM_DTER_CAP | DTIM_DTER_REF);
timestamp++; timestamp++;
return; return;

4
rtc/mcfrtc.c
View File

@ -28,7 +28,7 @@
#include <asm/immap.h> #include <asm/immap.h>
#include <asm/rtc.h> #include <asm/rtc.h>
#if defined(CONFIG_MCFRTC) && (CONFIG_COMMANDS & CFG_CMD_DATE) #if defined(CONFIG_MCFRTC) && defined(CONFIG_CMD_DATE)
#undef RTC_DEBUG #undef RTC_DEBUG
@ -118,4 +118,4 @@ void rtc_reset(void)
rtc->cr |= RTC_CR_SWR; rtc->cr |= RTC_CR_SWR;
} }
#endif /* CONFIG_MCFRTC && CFG_CMD_DATE */ #endif /* CONFIG_MCFRTC && CONFIG_CMD_DATE */