mpc5200, digsy_mtc: add support for rev5 board version
difference to previous board version: - M29W128GH flash from Numonyx - SDRAM ISSI IS45S16800 (Option A2 105°C) - rev5 uses RTC RV-3029-C2 - update cs0 and cs1 baseaddr and length depending on the detected flash size. - added Werner Pfister <Pfister_Werner@intercontrol.de> as maintainer for the digsy board variants - As the M29W128GH needs a special flash_cmd_reset() document that in the new file doc/README.cfi. - move "#endif /* CONFIG_CMD_IDE */" to the right place - remove LOWBOOT config option for digsy_mtc and digsy_mtc_rev5 boards - change doc/README.cfi as Stefan Roese suggested Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> cc: Wolfgang Denk <hs@denx.de> cc: Stefan Roese <sr@denx.de> cc: Werner Pfister <Pfister_Werner@intercontrol.de> cc: Detlev Zundel <dzu@denx.de>
This commit is contained in:
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1514579fbf
commit
466f0137e8
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@ -339,6 +339,10 @@ Denis Peter <d.peter@mpl.ch>
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MIP405 PPC4xx
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MIP405 PPC4xx
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PIP405 PPC4xx
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PIP405 PPC4xx
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Werner Pfister <Pfister_Werner@intercontrol.de>
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digsy_mtc mpc5200
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digsy_mtc_rev5 mpc5200
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Kim Phillips <kim.phillips@freescale.com>
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Kim Phillips <kim.phillips@freescale.com>
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MPC8349EMDS MPC8349
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MPC8349EMDS MPC8349
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@ -39,12 +39,29 @@
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#include <asm/processor.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/io.h>
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#include "eeprom.h"
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#include "eeprom.h"
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#if defined(CONFIG_DIGSY_REV5)
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#include "is45s16800a2.h"
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#include <mtd/cfi_flash.h>
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#else
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#include "is42s16800a-7t.h"
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#include "is42s16800a-7t.h"
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#endif
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#include <libfdt.h>
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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extern int usb_cpu_init(void);
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extern int usb_cpu_init(void);
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#if defined(CONFIG_DIGSY_REV5)
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/*
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* The M29W128GH needs a specail reset command function,
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* details see the doc/README.cfi file
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*/
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void flash_cmd_reset(flash_info_t *info)
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{
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flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
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}
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#endif
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#ifndef CONFIG_SYS_RAMBOOT
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#ifndef CONFIG_SYS_RAMBOOT
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static void sdram_start(int hi_addr)
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static void sdram_start(int hi_addr)
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{
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{
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@ -175,6 +192,9 @@ int checkboard(void)
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char *s = getenv("serial#");
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char *s = getenv("serial#");
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puts ("Board: InterControl digsyMTC");
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puts ("Board: InterControl digsyMTC");
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#if defined(CONFIG_DIGSY_REV5)
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puts (" rev5");
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#endif
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if (s != NULL) {
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if (s != NULL) {
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puts(", ");
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puts(", ");
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puts(s);
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puts(s);
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@ -305,12 +325,97 @@ void ide_set_reset(int idereset)
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setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
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setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
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}
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}
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#endif /* CONFIG_IDE_RESET */
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#endif /* CONFIG_IDE_RESET */
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#endif /* CONFIG_CMD_IDE */
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#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
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#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
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static void ft_delete_node(void *fdt, const char *compat)
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{
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int off = -1;
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int ret;
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off = fdt_node_offset_by_compatible(fdt, -1, compat);
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if (off < 0) {
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printf("Could not find %s node.\n", compat);
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return;
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}
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ret = fdt_del_node(fdt, off);
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if (ret < 0)
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printf("Could not delete %s node.\n", compat);
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}
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#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
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static void ft_adapt_flash_base(void *blob)
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{
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flash_info_t *dev = &flash_info[0];
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int off;
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struct fdt_property *prop;
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int len;
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u32 *reg, *reg2;
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off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb");
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if (off < 0) {
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printf("Could not find fsl,mpc5200b-lpb node.\n");
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return;
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}
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/* found compatible property */
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prop = fdt_get_property_w(blob, off, "ranges", &len);
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if (prop) {
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reg = reg2 = (u32 *)&prop->data[0];
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reg[2] = dev->start[0];
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reg[3] = dev->size;
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fdt_setprop(blob, off, "ranges", reg2, len);
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} else
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printf("Could not find ranges\n");
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}
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extern ulong flash_get_size (phys_addr_t base, int banknum);
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/* Update the Flash Baseaddr settings */
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int update_flash_size (int flash_size)
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{
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volatile struct mpc5xxx_mmap_ctl *mm =
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(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
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flash_info_t *dev;
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int i;
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int size = 0;
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unsigned long base = 0x0;
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u32 *cs_reg = (u32 *)&mm->cs0_start;
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for (i = 0; i < 2; i++) {
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dev = &flash_info[i];
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if (dev->size) {
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/* calculate new base addr for this chipselect */
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base -= dev->size;
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out_be32(cs_reg, START_REG(base));
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cs_reg++;
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out_be32(cs_reg, STOP_REG(base, dev->size));
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cs_reg++;
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/* recalculate the sectoraddr in the cfi driver */
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size += flash_get_size(base, i);
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}
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}
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gd->bd->bi_flashstart = base;
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return 0;
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}
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#endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */
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void ft_board_setup(void *blob, bd_t *bd)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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{
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ft_cpu_setup(blob, bd);
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ft_cpu_setup(blob, bd);
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/*
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* There are 2 RTC nodes in the DTS, so remove
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* the unneeded node here.
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*/
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#if defined(CONFIG_DIGSY_REV5)
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ft_delete_node(blob, "dallas,ds1339");
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#else
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ft_delete_node(blob, "mc,rv3029c2");
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#endif
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#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
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ft_adapt_flash_base(blob);
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#endif
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}
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}
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#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
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#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
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#endif /* CONFIG_CMD_IDE */
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@ -0,0 +1,31 @@
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/*
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* (C) Copyright 2010
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* based on:
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* (C) Copyright 2004-2009
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* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#define SDRAM_MODE 0x00CD0000
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#define SDRAM_CONTROL 0x50470000
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#define SDRAM_CONFIG1 0xD2322900
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#define SDRAM_CONFIG2 0x8AD70000
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@ -239,8 +239,9 @@ BC3450 powerpc mpc5xxx bc3450
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canmb powerpc mpc5xxx
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canmb powerpc mpc5xxx
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cm5200 powerpc mpc5xxx
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cm5200 powerpc mpc5xxx
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digsy_mtc powerpc mpc5xxx digsy_mtc
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digsy_mtc powerpc mpc5xxx digsy_mtc
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digsy_mtc_LOWBOOT powerpc mpc5xxx digsy_mtc - - digsy_mtc:SYS_TEXT_BASE=0xFF000000
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digsy_mtc_RAMBOOT powerpc mpc5xxx digsy_mtc - - digsy_mtc:SYS_TEXT_BASE=0x00100000
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digsy_mtc_RAMBOOT powerpc mpc5xxx digsy_mtc - - digsy_mtc:SYS_TEXT_BASE=0x00100000
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digsy_mtc_rev5 powerpc mpc5xxx digsy_mtc - - digsy_mtc:DIGSY_REV5
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digsy_mtc_rev5_RAMBOOT powerpc mpc5xxx digsy_mtc - - digsy_mtc:SYS_TEXT_BASE=0x00100000,DIGSY_REV5
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galaxy5200 powerpc mpc5xxx galaxy5200 - - galaxy5200:galaxy5200
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galaxy5200 powerpc mpc5xxx galaxy5200 - - galaxy5200:galaxy5200
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galaxy5200_LOWBOOT powerpc mpc5xxx galaxy5200 - - galaxy5200:galaxy5200_LOWBOOT
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galaxy5200_LOWBOOT powerpc mpc5xxx galaxy5200 - - galaxy5200:galaxy5200_LOWBOOT
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icecube_5200 powerpc mpc5xxx icecube - - IceCube
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icecube_5200 powerpc mpc5xxx icecube - - IceCube
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@ -0,0 +1,29 @@
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The common CFI driver provides this weak default implementation for
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flash_cmd_reset():
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void __flash_cmd_reset(flash_info_t *info)
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{
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/*
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* We do not yet know what kind of commandset to use, so we issue
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* the reset command in both Intel and AMD variants, in the hope
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* that AMD flash roms ignore the Intel command.
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*/
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flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
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flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
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}
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void flash_cmd_reset(flash_info_t *info)
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__attribute__((weak,alias("__flash_cmd_reset")));
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Some flash chips seems to have trouble with this reset sequence. In this case
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the board specific code can override this weak default version with a board
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specific function. For example the digsy_mtc board equipped with the M29W128GH
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from Numonyx needs this version to function properly:
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void flash_cmd_reset(flash_info_t *info)
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{
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flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
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}
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see also:
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http://www.mail-archive.com/u-boot@lists.denx.de/msg24368.html
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@ -249,9 +249,14 @@
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/*
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/*
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* RTC configuration
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* RTC configuration
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*/
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*/
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#if defined(CONFIG_DIGSY_REV5)
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#define CONFIG_SYS_I2C_RTC_ADDR 0x56
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#define CONFIG_RTC_RV3029
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#else
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#define CONFIG_RTC_DS1337
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#define CONFIG_RTC_DS1337
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68
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#define CONFIG_SYS_DS1339_TCR_VAL 0xAB /* diode + 4k resistor */
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#define CONFIG_SYS_DS1339_TCR_VAL 0xAB /* diode + 4k resistor */
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#endif
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/*
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/*
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* Flash configuration
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* Flash configuration
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@ -259,14 +264,24 @@
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#define CONFIG_SYS_FLASH_CFI 1
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#define CONFIG_SYS_FLASH_CFI 1
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#define CONFIG_FLASH_CFI_DRIVER 1
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#define CONFIG_FLASH_CFI_DRIVER 1
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#if defined(CONFIG_DIGSY_REV5)
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#define CONFIG_SYS_FLASH_BASE 0xFE000000
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#define CONFIG_SYS_FLASH_BASE_CS1 0xFC000000
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#define CONFIG_SYS_MAX_FLASH_BANKS 2
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_CS1, \
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CONFIG_SYS_FLASH_BASE}
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#define CONFIG_SYS_UPDATE_FLASH_SIZE
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#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
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#else
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#define CONFIG_SYS_FLASH_BASE 0xFF000000
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#define CONFIG_SYS_FLASH_BASE 0xFF000000
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#define CONFIG_SYS_FLASH_SIZE 0x01000000
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
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#endif
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#define CONFIG_SYS_MAX_FLASH_SECT 256
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#define CONFIG_SYS_MAX_FLASH_SECT 256
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#define CONFIG_FLASH_16BIT
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#define CONFIG_FLASH_16BIT
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
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#define CONFIG_SYS_FLASH_SIZE 0x01000000
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#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
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#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500
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@ -409,6 +424,12 @@
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#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
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#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
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#define CONFIG_SYS_CS0_CFG 0x0002DD00
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#define CONFIG_SYS_CS0_CFG 0x0002DD00
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#if defined(CONFIG_DIGSY_REV5)
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#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE_CS1
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#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE
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#define CONFIG_SYS_CS1_CFG 0x0002DD00
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#endif
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#define CONFIG_SYS_CS_BURST 0x00000000
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#define CONFIG_SYS_CS_BURST 0x00000000
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#define CONFIG_SYS_CS_DEADCYCLE 0x11111111
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#define CONFIG_SYS_CS_DEADCYCLE 0x11111111
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