ppc, 8xx: remove obsolete km8xx boards from keymile
The MPC852 based mgsuvd and kmsupx4 boards from keymile were initially ported but later on not developed further. So the respective files were removed to avoid unneeded merging and maintenance. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Acked-by: Heiko Schocher<hs@denx.de>
This commit is contained in:
Holger Brunck
Wolfgang Denk
parent
0c51c245a1
commit
1514579fbf
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@ -418,9 +418,7 @@ Heiko Schocher <hs@denx.de>
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ids8247 MPC8247
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jupiter MPC5200
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kmeter1 MPC8360
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kmsupx4 MPC852T
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mgcoge MPC8247
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mgsuvd MPC852
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mucmc52 MPC5200
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muas3001 MPC8270
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municse MPC5200
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@ -1,48 +0,0 @@
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#
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# (C) Copyright 2007
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# Heiko Schocher, DENX Software Engineering, hs@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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ifneq ($(OBJTREE),$(SRCTREE))
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$(shell mkdir -p $(obj)../common)
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endif
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LIB = $(obj)lib$(BOARD).o
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COBJS = $(BOARD).o ../common/common.o ../common/keymile_hdlc_enet.o \
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km8xx_hdlc_enet.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -1,197 +0,0 @@
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/*
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* (C) Copyright 2007
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc8xx.h>
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#include <net.h>
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#include <asm/io.h>
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#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
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#include <libfdt.h>
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#endif
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#include "../common/common.h"
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DECLARE_GLOBAL_DATA_PTR;
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const uint sdram_table[] =
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{
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0x0f07fc04, 0x0ffffc04, 0x00bdfc04, 0x0ff77c00,
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0x1ffffc05, 0xfffffc04, 0xfffffc04, 0xfffffc04,
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/* 0x08 Burst Read */
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0x0f07fc04, 0x0ffffc04, 0x00bdfc04, 0x00fffc00,
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0x00fffc00, 0x00fffc00, 0x0ff77c00, 0x1ffffc05,
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/* 0x10 Load mode register */
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0x0ffffc34, 0x0ff57c04, 0x0ffffc04, 0x1ffffc05,
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0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
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/* 0x18 Single Write */
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0x0f07fc04, 0x0ffffc00, 0x00bd7c04, 0x0ffffc04,
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0x0ff77c04, 0x1ffffc05, 0xfffffc04, 0xfffffc04,
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/* 0x20 Burst Write */
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0x0f07fc04, 0x0ffffc00, 0x00bd7c00, 0x00fffc00,
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0x00fffc00, 0x00fffc04, 0x0ffffc04, 0x0ff77c04,
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0x1ffffc05, 0xfffffc04, 0xfffffc04, 0xfffffc04,
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0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
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/* 0x30 Precharge all and Refresh */
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0x0ff77c04, 0x0ffffc04, 0x0ff5fc84, 0x0ffffc04,
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0x0ffffc04, 0x0ffffc84, 0x1ffffc05, 0xfffffc04,
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0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
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/* 0x3C Exception */
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0x7ffffc04, 0xfffffc07, 0xfffffc04, 0xfffffc04,
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};
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int checkboard (void)
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{
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puts ("Board: Keymile ");
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#if defined(CONFIG_KMSUPX4)
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puts ("kmsupx4");
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#else
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puts ("mgsuvd");
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#endif
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if (ethernet_present ())
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puts (" with PIGGY.");
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puts ("\n");
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return (0);
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}
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phys_size_t initdram (int board_type)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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long int size;
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upmconfig (UPMB, (uint *) sdram_table,
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sizeof (sdram_table) / sizeof (uint));
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/*
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* Preliminary prescaler for refresh (depends on number of
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* banks): This value is selected for four cycles every 62.4 us
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* with two SDRAM banks or four cycles every 31.2 us with one
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* bank. It will be adjusted after memory sizing.
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*/
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memctl->memc_mptpr = CONFIG_SYS_MPTPR;
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/*
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* The following value is used as an address (i.e. opcode) for
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* the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
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* the port size is 32bit the SDRAM does NOT "see" the lower two
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* address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
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* MICRON SDRAMs:
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* -> 0 00 010 0 010
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* | | | | +- Burst Length = 4
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* | | | +----- Burst Type = Sequential
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* | | +------- CAS Latency = 2
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* | +----------- Operating Mode = Standard
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* +-------------- Write Burst Mode = Programmed Burst Length
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*/
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memctl->memc_mar = CONFIG_SYS_MAR;
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/*
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* Map controller banks 1 to the SDRAM banks 1 at
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* preliminary addresses - these have to be modified after the
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* SDRAM size has been determined.
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*/
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memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
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memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
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memctl->memc_mbmr = CONFIG_SYS_MBMR & (~(MBMR_PTBE)); /* no refresh yet */
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udelay (200);
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/* perform SDRAM initializsation sequence */
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memctl->memc_mcr = 0x80802830; /* SDRAM bank 0 */
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udelay (1);
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memctl->memc_mcr = 0x80802110; /* SDRAM bank 0 - execute twice */
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udelay (1);
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memctl->memc_mbmr |= MBMR_PTBE; /* enable refresh */
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udelay (1000);
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/*
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* Check Bank 0 Memory Size for re-configuration
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*
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*/
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size = get_ram_size(SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
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udelay (1000);
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debug ("SDRAM Bank 0: %ld MB\n", size >> 20);
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return (size);
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}
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/*
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* Early board initalization.
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*/
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int board_early_init_r(void)
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{
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/* setup the UPIOx */
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/* General Unit Reset disabled, Flash Bank enabled, UnitLed on */
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out_8((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x02), 0xc2);
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/* SCC4 enable, halfduplex, FCC1 powerdown, ANDI enable*/
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out_8((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x03), 0x35);
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return 0;
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}
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int hush_init_var (void)
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{
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ivm_read_eeprom ();
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return 0;
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}
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#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
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/*
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* update "brg" property in the blob
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*/
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void ft_blob_update (void *blob, bd_t *bd)
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{
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ulong brg_data[1] = {0};
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/* BRG */
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brg_data[0] = cpu_to_be32 (bd->bi_busfreq);
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fdt_set_node_and_value (blob, "/soc/cpm", "brg-frequency", brg_data,
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sizeof (brg_data));
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/* MAC adr */
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fdt_set_node_and_value (blob, "/soc/cpm/ethernet", "mac-address",
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bd->bi_enetaddr, sizeof (u8) * 6);
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}
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void ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup (blob, bd);
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ft_blob_update (blob, bd);
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}
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#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
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int i2c_soft_read_pin (void)
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{
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int val;
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*(unsigned short *)(I2C_BASE_DIR) &= ~SDA_CONF;
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udelay(1);
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val = *(unsigned char *)(I2C_BASE_PORT);
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return ((val & SDA_BIT) == SDA_BIT);
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}
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@ -1,278 +0,0 @@
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/*
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* (C) Copyright 2008
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* Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
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*
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* Based in part on arch/powerpc/cpu/mpc8xx/scc.c.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h> /* commproc.h is included here */
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#include <malloc.h>
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#include <net.h>
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#ifdef CONFIG_KEYMILE_HDLC_ENET
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#include "../common/keymile_hdlc_enet.h"
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char keymile_slot; /* our slot number in the backplane */
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/*
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* Since, except during initialization, ethact is always HDLC
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* while we're in the driver, just use serial_printf() everywhere for
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* output. This avoids possible conflicts when netconsole is being
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* used.
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*/
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#define dprintf(fmt, args...) serial_printf(fmt, ##args)
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static int already_inited;
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/*
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* SCC Ethernet Tx and Rx buffer descriptors allocated at the
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* immr->udata_bd address on Dual-Port RAM
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* Provide for Double Buffering
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*/
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typedef volatile struct CommonBufferDescriptor {
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cbd_t txbd; /* Tx BD */
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cbd_t rxbd[HDLC_PKTBUFSRX]; /* Rx BD */
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} RTXBD;
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static RTXBD *rtx;
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int keymile_hdlc_enet_init(struct eth_device *, bd_t *);
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void keymile_hdlc_enet_halt(struct eth_device *);
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extern void keymile_hdlc_enet_init_bds(RTXBD *);
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extern void initCachedNumbers(int);
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/* Use SCC4 */
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#define MGS_CPM_CR_HDLC CPM_CR_CH_SCC4
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#define MGS_PROFF_HDLC PROFF_SCC4
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#define MGS_SCC_HDLC 3 /* Index, not number! */
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int keymile_hdlc_enet_init(struct eth_device *dev, bd_t *bis)
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{
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/* int i; */
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/* volatile cbd_t *bdp; */
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volatile cpm8xx_t *cp;
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volatile scc_t *sccp;
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volatile hdlc_pram_t *hpr;
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volatile iop8xx_t *iop;
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if (already_inited)
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return 0;
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cp = (cpm8xx_t *)&(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm);
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hpr = (hdlc_pram_t *)(&cp->cp_dparam[MGS_PROFF_HDLC]);
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sccp = (volatile scc_t *)(&cp->cp_scc[MGS_SCC_HDLC]);
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iop = (iop8xx_t *)&(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport);
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/*
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* Disable receive and transmit just in case.
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*/
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sccp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
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#ifndef CONFIG_SYS_ALLOC_DPRAM
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#error "CONFIG_SYS_ALLOC_DPRAM must be defined"
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#else
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/*
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* Avoid exhausting DPRAM, which would cause a panic.
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* Actually this isn't really necessary, but leave it here
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* for safety's sake.
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*/
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if (rtx == NULL) {
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rtx = (RTXBD *) (cp->cp_dpmem +
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dpram_alloc_align(sizeof(RTXBD), 8));
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if (rtx == (RTXBD *)CPM_DP_NOSPACE)
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return -1;
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memset((void *)rtx, 0, sizeof(RTXBD));
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}
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#endif /* !CONFIG_SYS_ALLOC_DPRAM */
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/* We need the slot number for addressing. */
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keymile_slot = *(char *)(CONFIG_SYS_SLOT_ID_BASE +
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CONFIG_SYS_SLOT_ID_OFF) & CONFIG_SYS_SLOT_ID_MASK;
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/*
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* Be consistent with the Linux driver and set
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* only enetaddr[0].
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*
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* Always add 1 to the slot number so that
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* there are no problems with an ethaddr which
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* is all 0s. This should be acceptable because
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* a board should never have a slot number of 255,
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* which is the broadcast address. The HDLC addressing
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* uses only the slot number.
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*/
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dev->enetaddr[0] = keymile_slot + 1;
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#ifdef TEST_IT
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dprintf("slot %d\n", keymile_slot);
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#endif
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/* use pa8, pa9 pins for TXD4, RXD4 respectively */
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iop->iop_papar |= ((0x8000 >> 8) | (0x8000 >> 9));
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iop->iop_padir &= ~((0x8000 >> 8) | (0x8000 >> 9));
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iop->iop_paodr &= ~((0x8000 >> 8) | (0x8000 >> 9));
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/* also use pa0 as CLK8 */
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iop->iop_papar |= 0x8000;
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iop->iop_padir &= ~0x8000;
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iop->iop_paodr &= ~0x8000;
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/* use pc5 as CTS4 */
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iop->iop_pcpar &= ~(0x8000 >> 5);
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iop->iop_pcdir &= ~(0x8000 >> 5);
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iop->iop_pcso |= (0x8000 >> 5);
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/*
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* SI clock routing
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* use CLK8
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* this also connects SCC4 to NMSI
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*/
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cp->cp_sicr = (cp->cp_sicr & ~0xff000000) | 0x3f000000;
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/* keymile_rxIdx = 0; */
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/*
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* Initialize function code registers for big-endian.
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*/
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hpr->rfcr = SCC_EB;
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hpr->tfcr = SCC_EB;
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/*
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* Set maximum bytes per receive buffer.
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*/
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hpr->mrblr = MAX_FRAME_LENGTH;
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/* Setup CRC generator values for HDLC */
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hpr->c_mask = 0x0000F0B8;
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hpr->c_pres = 0x0000FFFF;
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/* Initialize all error counters to 0 */
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hpr->disfc = 0;
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hpr->crcec = 0;
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hpr->abtsc = 0;
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hpr->nmarc = 0;
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hpr->retrc = 0;
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/* Set maximum frame length size */
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hpr->mflr = MAX_FRAME_LENGTH;
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/* set to 1 for per frame processing change later if needed */
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hpr->rfthr = 1;
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hpr->hmask = 0xff;
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hpr->haddr2 = SET_HDLC_UUA(keymile_slot);
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hpr->haddr3 = hpr->haddr2;
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hpr->haddr4 = hpr->haddr2;
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/* broadcast */
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hpr->haddr1 = HDLC_BCAST;
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hpr->rbase = (unsigned int) &rtx->rxbd[0];
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hpr->tbase = (unsigned int) &rtx->txbd;
|
||||
|
||||
#if 0
|
||||
/*
|
||||
* Initialize the buffer descriptors.
|
||||
*/
|
||||
bdp = &rtx->txbd;
|
||||
bdp->cbd_sc = 0;
|
||||
bdp->cbd_bufaddr = 0;
|
||||
bdp->cbd_sc = BD_SC_WRAP;
|
||||
|
||||
/*
|
||||
* Setup RX packet buffers, aligned correctly.
|
||||
* Borrowed from net/net.c.
|
||||
*/
|
||||
MyRxPackets[0] = &MyPktBuf[0] + (PKTALIGN - 1);
|
||||
MyRxPackets[0] -= (ulong)MyRxPackets[0] % PKTALIGN;
|
||||
for (i = 1; i < HDLC_PKTBUFSRX; i++)
|
||||
MyRxPackets[i] = MyRxPackets[0] + i * PKT_MAXBLR_SIZE;
|
||||
|
||||
bdp = &rtx->rxbd[0];
|
||||
for (i = 0; i < HDLC_PKTBUFSRX; i++) {
|
||||
bdp->cbd_sc = BD_SC_EMPTY;
|
||||
/* Leave space at the start for INET header. */
|
||||
bdp->cbd_bufaddr = (unsigned int)(MyRxPackets[i] +
|
||||
INET_HDR_ALIGN);
|
||||
bdp++;
|
||||
}
|
||||
bdp--;
|
||||
bdp->cbd_sc |= BD_SC_WRAP;
|
||||
#else
|
||||
keymile_hdlc_enet_init_bds(rtx);
|
||||
#endif
|
||||
|
||||
/* Let's re-initialize the channel now. We have to do it later
|
||||
* than the manual describes because we have just now finished
|
||||
* the BD initialization.
|
||||
*/
|
||||
cp->cp_cpcr = mk_cr_cmd(MGS_CPM_CR_HDLC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
|
||||
while (cp->cp_cpcr & CPM_CR_FLG);
|
||||
|
||||
sccp->scc_gsmrl = SCC_GSMRL_MODE_HDLC;
|
||||
/* CTSS=1 */
|
||||
sccp->scc_gsmrh = SCC_GSMRH_CTSS;
|
||||
/* NOF=0, RTE=1, DRT=0, BUS=1 */
|
||||
sccp->scc_psmr = ((0x8000 >> 6) | (0x8000 >> 10));
|
||||
|
||||
/* loopback for local testing */
|
||||
#ifdef GJTEST
|
||||
dprintf("LOOPBACK!\n");
|
||||
sccp->scc_gsmrl |= SCC_GSMRL_DIAG_LOOP;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Disable all interrupts and clear all pending
|
||||
* events.
|
||||
*/
|
||||
sccp->scc_sccm = 0;
|
||||
sccp->scc_scce = 0xffff;
|
||||
|
||||
/*
|
||||
* And last, enable the transmit and receive processing.
|
||||
*/
|
||||
sccp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
|
||||
|
||||
dprintf("%s: HDLC ENET Version 0.3 on SCC%d\n", dev->name,
|
||||
MGS_SCC_HDLC + 1);
|
||||
|
||||
/*
|
||||
* We may not get an ARP packet because ARP was already done on
|
||||
* a different interface, so initialize the cached values now.
|
||||
*/
|
||||
initCachedNumbers(1);
|
||||
|
||||
already_inited = 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void keymile_hdlc_enet_halt(struct eth_device *dev)
|
||||
{
|
||||
#if 0 /* just return, but keep this for reference */
|
||||
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
|
||||
|
||||
/* maybe should do a graceful stop here? */
|
||||
immr->im_cpm.cp_scc[MGS_SCC_HDLC].scc_gsmrl &=
|
||||
~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* CONFIG_KEYMILE_HDLC_ENET */
|
||||
|
|
@ -1,97 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2000-2010
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.text :
|
||||
{
|
||||
arch/powerpc/cpu/mpc8xx/start.o (.text*)
|
||||
arch/powerpc/cpu/mpc8xx/traps.o (.text*)
|
||||
|
||||
*(.text*)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
}
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
KEEP(*(.got))
|
||||
_GOT2_TABLE_ = .;
|
||||
KEEP(*(.got2))
|
||||
_FIXUP_TABLE_ = .;
|
||||
KEEP(*(.fixup))
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data*)
|
||||
*(.sdata*)
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
*(.bss*)
|
||||
*(.sbss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
|
|
@ -584,8 +584,6 @@ SXNI855T powerpc mpc8xx sixnet
|
|||
v37 powerpc mpc8xx
|
||||
MHPC powerpc mpc8xx mhpc eltec
|
||||
TOP860 powerpc mpc8xx top860 emk
|
||||
kmsupx4 powerpc mpc8xx km8xx keymile
|
||||
mgsuvd powerpc mpc8xx km8xx keymile
|
||||
KUP4K powerpc mpc8xx kup4k kup
|
||||
KUP4X powerpc mpc8xx kup4x kup
|
||||
ELPT860 powerpc mpc8xx elpt860 LEOX
|
||||
|
|
|
|||
|
|
@ -1,332 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2009
|
||||
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* configuration options, keymile 8xx board specific
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_KM8XX_H
|
||||
#define __CONFIG_KM8XX_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_KM8XX 1 /* on a km8xx board */
|
||||
|
||||
/* include common defines/options for all Keymile boards */
|
||||
#include "keymile-common.h"
|
||||
|
||||
#if defined(CONFIG_KMSUPX4)
|
||||
#undef CONFIG_I2C_MUX /* no I2C mux on this board */
|
||||
#endif
|
||||
|
||||
#define CONFIG_8xx_GCLK_FREQ 66000000
|
||||
|
||||
#define CONFIG_SYS_SMC_UCODE_PATCH 1 /* Relocate SMC1 */
|
||||
#define CONFIG_SYS_SMC_DPMEM_OFFSET 0x1fc0
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
|
||||
#define CONFIG_SYS_SMC_RXBUFLEN 128
|
||||
#define CONFIG_SYS_MAXIDLE 10
|
||||
|
||||
#define CONFIG_SYS_CPM_BOOTCOUNT_ADDR 0x1eb0 /* In case of SMC relocation,
|
||||
* the default value is not
|
||||
* working
|
||||
*/
|
||||
|
||||
#define BOOTFLASH_START F0000000
|
||||
#define CONFIG_PRAM 512 /* protected RAM [KBytes] */
|
||||
|
||||
#define CONFIG_PREBOOT "echo;" \
|
||||
"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
|
||||
"echo"
|
||||
|
||||
#define BOOTFLASH_START F0000000
|
||||
#define CONFIG_PRAM 512 /* protected RAM [KBytes] */
|
||||
|
||||
#if defined(CONFIG_MGSUVD)
|
||||
#define CONFIG_ENV_IVM "EEprom_ivm=pca9544a:70:4 \0"
|
||||
#else
|
||||
#define CONFIG_ENV_IVM ""
|
||||
#endif
|
||||
|
||||
#define MTDIDS_DEFAULT "nor0=app"
|
||||
#define MTDPARTS_DEFAULT \
|
||||
"mtdparts=app:384k(u-boot),128k(env),128k(envred),128k(free)," \
|
||||
"1536k(esw0),8704k(rootfs0),1536k(esw1),2432k(rootfs1),640k(var)," \
|
||||
"768k(cfg)"
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
CONFIG_KM_DEF_ENV \
|
||||
"rootpath=/opt/eldk/ppc_8xx\0" \
|
||||
"addcon=setenv bootargs ${bootargs} " \
|
||||
"console=ttyCPM0,${baudrate}\0" \
|
||||
"mtdids=nor0=app \0" \
|
||||
"mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0" \
|
||||
"partition=nor0,9 \0" \
|
||||
"new_env=prot off F0060000 F009FFFF; era F0060000 F009FFFF \0" \
|
||||
CONFIG_ENV_IVM \
|
||||
""
|
||||
|
||||
#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */
|
||||
|
||||
#define CONFIG_TIMESTAMP /* but print image timestmps */
|
||||
|
||||
/*
|
||||
* Low Level Configuration Settings
|
||||
* (address mappings, register initial values, etc.)
|
||||
* You should know what you are doing if you make changes here.
|
||||
*/
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register
|
||||
*/
|
||||
#define CONFIG_SYS_IMMR 0xFFF00000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_FLASH_BASE 0xf0000000
|
||||
#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* 384 kB for Monitor */
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
/* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
||||
#define CONFIG_SYS_FLASH_SIZE 32
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
/* max num of sects on one chip */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* (in ms) */
|
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
|
||||
#define CONFIG_ENV_BUFFER_PRINT 1
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9
|
||||
* SYPCR can only be written once after reset!
|
||||
*-----------------------------------------------------------------------
|
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
|
||||
*/
|
||||
#define CONFIG_SYS_SYPCR 0xffffff89
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#if defined(CONFIG_MGSUVD)
|
||||
#define CONFIG_SYS_SIUMCR 0x00610480
|
||||
#else
|
||||
#define CONFIG_SYS_SIUMCR 0x00610400
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Reference Interrupt Status, Timebase freezing enabled
|
||||
*/
|
||||
#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
|
||||
*/
|
||||
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27
|
||||
*-----------------------------------------------------------------------
|
||||
* Set clock output, timebase and RTC source and divider,
|
||||
* power management and some other internal clocks
|
||||
*/
|
||||
#if defined(CONFIG_MGSUVD)
|
||||
#define SCCR_MASK 0x01800000
|
||||
#else
|
||||
#define SCCR_MASK 0x00000000
|
||||
#endif
|
||||
#define CONFIG_SYS_SCCR 0x01800000
|
||||
|
||||
#define CONFIG_SYS_DER 0
|
||||
|
||||
/*
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* BR0/1 and OR0/1 (FLASH)
|
||||
*/
|
||||
|
||||
#define FLASH_BASE0_PRELIM 0xf0000000 /* FLASH bank #0 */
|
||||
|
||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||
* restrict access enough to keep SRAM working (if any)
|
||||
* but not too much to meddle with FLASH accesses
|
||||
*/
|
||||
#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
|
||||
#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
|
||||
|
||||
/*
|
||||
* FLASH timing: Default value of OR0 after reset
|
||||
*/
|
||||
#define CONFIG_SYS_OR0_PRELIM 0xfe000954
|
||||
#define CONFIG_SYS_BR0_PRELIM 0xf0000401
|
||||
|
||||
/*
|
||||
* BR1 and OR1 (SDRAM)
|
||||
*
|
||||
*/
|
||||
#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
|
||||
#define SDRAM_MAX_SIZE (64 << 20) /* max 64 MB per bank */
|
||||
|
||||
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
|
||||
#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
|
||||
|
||||
#define CONFIG_SYS_OR1_PRELIM 0xfc000800
|
||||
#define CONFIG_SYS_BR1_PRELIM (0x000000C0 | 0x01)
|
||||
|
||||
#define CONFIG_SYS_MPTPR 0x0200
|
||||
/* PTB=16, AMB=001, FIXME 1 RAS precharge cycles, 1 READ loop cycle (not used),
|
||||
1 Write loop Cycle (not used), 1 Timer Loop Cycle */
|
||||
#if defined(CONFIG_MGSUVD)
|
||||
#define CONFIG_SYS_MBMR 0x10964111
|
||||
#else
|
||||
#define CONFIG_SYS_MBMR 0x20964111
|
||||
#endif
|
||||
#define CONFIG_SYS_MAR 0x00000088
|
||||
|
||||
/*
|
||||
* 4096 Rows from SDRAM example configuration
|
||||
* 1000 factor s -> ms
|
||||
* 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
|
||||
* 4 Number of refresh cycles per period
|
||||
* 64 Refresh cycle in ms per number of rows
|
||||
*/
|
||||
#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
|
||||
|
||||
/* GPIO/PIGGY on CS3 initialization values
|
||||
*/
|
||||
#define CONFIG_SYS_PIGGY_BASE (0x30000000)
|
||||
#if defined(CONFIG_MGSUVD)
|
||||
#define CONFIG_SYS_OR3_PRELIM (0xfe000d24)
|
||||
#define CONFIG_SYS_BR3_PRELIM (0x30000401)
|
||||
#else
|
||||
#define CONFIG_SYS_OR3_PRELIM (0xf8000d26)
|
||||
#define CONFIG_SYS_BR3_PRELIM (0x30000401)
|
||||
#endif
|
||||
|
||||
#define CONFIG_SCC3_ENET
|
||||
#define CONFIG_ETHPRIME "SCC"
|
||||
#define CONFIG_HAS_ETH0
|
||||
|
||||
/* pass open firmware flat tree */
|
||||
#define CONFIG_OF_LIBFDT 1
|
||||
#define CONFIG_OF_BOARD_SETUP 1
|
||||
|
||||
#define OF_STDOUT_PATH "/soc/cpm/serial@a80"
|
||||
|
||||
/* enable I2C and select the hardware/software driver */
|
||||
#undef CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
|
||||
/* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SPEED 50000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define I2C_SOFT_DECLARATIONS
|
||||
|
||||
/*
|
||||
* Software (bit-bang) I2C driver configuration
|
||||
*/
|
||||
#define I2C_BASE_DIR ((u16 *)(CONFIG_SYS_PIGGY_BASE + 0x04))
|
||||
#define I2C_BASE_PORT ((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x09))
|
||||
|
||||
#define SDA_BIT 0x40
|
||||
#define SCL_BIT 0x80
|
||||
#define SDA_CONF 0x1000
|
||||
#define SCL_CONF 0x2000
|
||||
|
||||
#define I2C_ACTIVE do {} while (0)
|
||||
#define I2C_TRISTATE do {} while (0)
|
||||
#define I2C_READ ((in_8(I2C_BASE_PORT) & SDA_BIT) == SDA_BIT)
|
||||
#define I2C_SDA(bit) if(bit) { \
|
||||
clrbits(be16, I2C_BASE_DIR, SDA_CONF); \
|
||||
} else { \
|
||||
clrbits(8, I2C_BASE_PORT, SDA_BIT); \
|
||||
setbits(be16, I2C_BASE_DIR, SDA_CONF); \
|
||||
}
|
||||
#define I2C_SCL(bit) if(bit) { \
|
||||
clrbits(be16, I2C_BASE_DIR, SCL_CONF); \
|
||||
} else { \
|
||||
clrbits(8, I2C_BASE_PORT, SCL_BIT); \
|
||||
setbits(be16, I2C_BASE_DIR, SCL_CONF); \
|
||||
}
|
||||
#define I2C_DELAY udelay(50) /* 1/4 I2C clock duration */
|
||||
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||
|
||||
/* I2C SYSMON (LM75, AD7414 is almost compatible) */
|
||||
#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
|
||||
#if defined(CONFIG_MGSUVD)
|
||||
#define CONFIG_DTT_SENSORS {0, 2, 4, 6} /* Sensor addresses */
|
||||
#else
|
||||
#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
|
||||
#endif
|
||||
#define CONFIG_SYS_DTT_MAX_TEMP 70
|
||||
#define CONFIG_SYS_DTT_LOW_TEMP -30
|
||||
#define CONFIG_SYS_DTT_HYSTERESIS 3
|
||||
#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
|
||||
#endif /* __CONFIG_KM8XX_H */
|
||||
|
|
@ -1,43 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2009
|
||||
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define CONFIG_MPC852T 1 /* This is a MPC852T CPU */
|
||||
#define CONFIG_KMSUPX4 1 /* ...on a kmsupx4 board */
|
||||
#define CONFIG_HOSTNAME kmsupx4
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xf0000000
|
||||
|
||||
/* include common defines/options for all Keymile 8xx boards */
|
||||
#include "km8xx.h"
|
||||
|
||||
#define CONFIG_SYS_DELAYED_ICACHE 1 /* enable ICache not before
|
||||
* running in RAM.
|
||||
*/
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define CONFIG_MPC866 1 /* This is a MPC866 CPU */
|
||||
#define CONFIG_MGSUVD 1 /* ...on a mgsuvd board */
|
||||
#define CONFIG_HOSTNAME mgsuvd
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xf0000000
|
||||
|
||||
/* include common defines/options for all Keymile 8xx boards */
|
||||
#include "km8xx.h"
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue