Turns out, there's lots of common code for flash. Pull up prefetch
on/off to start with, as there's only a single bit name different.
Pull up the definitions of common API functions too, starting with
flash_set_ws. Even if the implementations are different, things that
meant to be the same, should be defined centrally.
split spi stuff in three part:
- v1 : basic spi peripheral
- v1_frf : v1 spi with frf mode additional bit in spi_cr2 / spi_sr
- v2 : spi with variable datasize, fifo and other fancy stuff.
v1 maps to f1 chips
v1_frf to f2, f4 and l0,l1
v2 to f0, f3 and l4
This breaks spi_master_init API for v2 devices : function prototype from
common spi header used to be abused, with DFF bit reused for CRCL bit.
New v2 spi_master_init does not handle anymore CRCL bits, as it does not
usually mess with other crc configuration.
According to reference manuals both l0 and l4 have "v2" i2c peripheral.
This patch adds i2c support to l0 and l4 using previously unified "v2" i2c
headers and implementation.
No real hardware has been tested so far. Only compilation tests for both
libopencm3 and libopencm3-examples for all stm32 families.
Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com>
L4 and F3 actually have the same bits to write in the same order, but F3 hides
the name of the deep power down bit. Keep the like that for now, but there's a
standard API for enabling and disabling the regulator.
Just the basic core common functionality gained for free by being a common
peripheral. Enough for a miniblink.
Fixes some errors in the GPIO memory map. ST's naming of AHB2 vs AHB3 is
confusing.
Values from RM0351rev1, with the correction of the duplicate TIM1_CC entry.
Only stub support so far, but this opens up the beginning of build testing.
Marek Koza